From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 02/12] ARM: socfpga: Sort the DT Makefile
Date: Sat, 12 May 2018 22:30:10 +0200 [thread overview]
Message-ID: <20180512203020.17422-2-marex@denx.de> (raw)
In-Reply-To: <20180512203020.17422-1-marex@denx.de>
Sort the Makefile entries, no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/dts/Makefile | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f94940a7dd..b29ecb0060 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -182,20 +182,20 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
- socfpga_arria10_socdk_sdmmc.dtb \
socfpga_arria5_socdk.dtb \
+ socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_is1.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_socdk.dtb \
socfpga_cyclone5_dbm_soc1.dtb \
- socfpga_cyclone5_de0_nano_soc.dtb \
+ socfpga_cyclone5_de0_nano_soc.dtb \
socfpga_cyclone5_de1_soc.dtb \
socfpga_cyclone5_de10_nano.dtb \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
- socfpga_stratix10_socdk.dtb \
- socfpga_cyclone5_vining_fpga.dtb
+ socfpga_cyclone5_vining_fpga.dtb \
+ socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb
--
2.16.2
next prev parent reply other threads:[~2018-05-12 20:30 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-12 20:30 [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Marek Vasut
2018-05-12 20:30 ` Marek Vasut [this message]
2018-05-16 10:13 ` [U-Boot] [PATCH 02/12] ARM: socfpga: Sort the DT Makefile Ley Foon Tan
2018-05-12 20:30 ` [U-Boot] [PATCH 03/12] ARM: socfpga: Synchronize Arria10 DTs Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 04/12] ARM: socfpga: Synchronize Arria10 SoCDK SDMMC handoff Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 05/12] ARM: socfpga: Repair A10 EMAC reset handling Marek Vasut
2018-05-16 10:24 ` Ley Foon Tan
2018-05-12 20:30 ` [U-Boot] [PATCH 06/12] ARM: socfpga: Rename the gen5 sdram driver to more specific name Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 07/12] ARM: socfpga: Add DRAM bank size initialization function Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 08/12] ARM: socfpga: Add DDR driver for Arria 10 Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 09/12] configs: Add DDR Kconfig support " Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 10/12] ARM: socfpga: Enable SPL memory allocation Marek Vasut
2018-05-16 10:26 ` Ley Foon Tan
2018-05-12 20:30 ` [U-Boot] [PATCH 11/12] ARM: socfpga: Adding clock frequency info for U-Boot Marek Vasut
2018-05-12 20:30 ` [U-Boot] [PATCH 12/12] ARM: socfpga: Adding SoCFPGA info for both SPL and U-Boot Marek Vasut
2018-05-17 4:38 ` [U-Boot] [PATCH 01/12] ARM: socfpga: Sync A10 clock manager binding parser Chee, Tien Fong
2018-05-17 8:24 ` Marek Vasut
2018-05-17 8:44 ` Chee, Tien Fong
2018-05-17 9:38 ` Marek Vasut
2018-05-18 4:41 ` Chee, Tien Fong
2018-05-18 7:50 ` Marek Vasut
2018-05-18 8:39 ` Chee, Tien Fong
2018-05-18 8:42 ` Marek Vasut
2018-05-18 8:53 ` Chee, Tien Fong
2018-05-18 8:58 ` Marek Vasut
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