[U-Boot] [PATCH] armv7r: K3: Allow SPL to run only on core 0

[U-Boot] [PATCH] armv7r: K3: Allow SPL to run only on core 0

[Lokesh Vutla]

Based on the MCU R5 efuse settings, R5F cores in MCU domain
either work in split mode or in lock step mode.

If efuse settings are in lockstep mode: ROM release R5 cores
and SPL continues to run on the R5 core is lockstep mode.

If efuse settings are in split mode: ROM releases both the R5
cores simultaneously and allow SPL to run on both the cores.
In this case it is bootloader's responsibility to detect core
1 and park it. Else both the core will be running bootloader
independently which might result in an unexpected behaviour.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
- Depends on the series: https://patchwork.ozlabs.org/project/uboot/list/?series=73801

 arch/arm/mach-k3/Makefile        |  2 +-
 arch/arm/mach-k3/lowlevel_init.S | 20 ++++++++++++++++++++
 include/configs/am65x_evm.h      |  2 ++
 3 files changed, 23 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-k3/lowlevel_init.S

diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 406dda3b02..bd4ab361b2 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -5,5 +5,5 @@
 
 obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
 obj-$(CONFIG_ARM64) += arm64-mmu.o
-obj-$(CONFIG_CPU_V7R) += r5_mpu.o
+obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
 obj-y += common.o
diff --git a/arch/arm/mach-k3/lowlevel_init.S b/arch/arm/mach-k3/lowlevel_init.S
new file mode 100644
index 0000000000..70c5d1cade
--- /dev/null
+++ b/arch/arm/mach-k3/lowlevel_init.S
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+
+	mrc	p15, 0, r0, c0, c0, 5		@ Read MPIDR
+	and	r0, #0xff
+	cmp	r0, #0x0
+	bne	park_cpu
+	bx	lr
+park_cpu:
+	wfi
+	b	park_cpu
+
+ENDPROC(lowlevel_init)
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index 484c5ef2fe..31749c6d06 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -29,7 +29,9 @@
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"tispl.bin"
 #endif
 
+#ifndef CONFIG_CPU_V7R
 #define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
 
 #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SPL_TEXT_BASE +	\
-- 
2.19.1

[U-Boot] [PATCH] armv7r: K3: Allow SPL to run only on core 0

[Tom Rini]

On Thu, Nov 15, 2018 at 11:04:50AM +0530, Lokesh Vutla wrote:

> Based on the MCU R5 efuse settings, R5F cores in MCU domain
> either work in split mode or in lock step mode.
> 
> If efuse settings are in lockstep mode: ROM release R5 cores
> and SPL continues to run on the R5 core is lockstep mode.
> 
> If efuse settings are in split mode: ROM releases both the R5
> cores simultaneously and allow SPL to run on both the cores.
> In this case it is bootloader's responsibility to detect core
> 1 and park it. Else both the core will be running bootloader
> independently which might result in an unexpected behaviour.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Reviewed-by: Tom Rini <trini@konsulko.com>

-- 
Tom
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[U-Boot] armv7r: K3: Allow SPL to run only on core 0

[Tom Rini]

On Thu, Nov 15, 2018 at 11:04:50AM +0530, Lokesh Vutla wrote:

> Based on the MCU R5 efuse settings, R5F cores in MCU domain
> either work in split mode or in lock step mode.
> 
> If efuse settings are in lockstep mode: ROM release R5 cores
> and SPL continues to run on the R5 core is lockstep mode.
> 
> If efuse settings are in split mode: ROM releases both the R5
> cores simultaneously and allow SPL to run on both the cores.
> In this case it is bootloader's responsibility to detect core
> 1 and park it. Else both the core will be running bootloader
> independently which might result in an unexpected behaviour.
> 
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!

-- 
Tom
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