* [PATCH 0/2] arm: allwinner: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C @ 2021-07-15 10:18 Ivan Uvarov 2021-07-15 10:18 ` [PATCH 1/2] arm: allwinner: r40: add pinmux settings for MMC3 and UARTs 2, 4, 5&7 Ivan Uvarov 2021-07-15 10:19 ` [PATCH 2/2] arm: allwinner: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C Ivan Uvarov 0 siblings, 2 replies; 5+ messages in thread From: Ivan Uvarov @ 2021-07-15 10:18 UTC (permalink / raw) To: u-boot; +Cc: Andre Przywara, Chen-Yu Tsai, Ivan Uvarov This patchset adds a devicetree for the Forlinx FETA40i-C SoM and OKA40i-C carrier board/devboard, mirroring changes merged into Linux 5.14-rc1. Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com> Ivan Uvarov (2): arm: allwinner: r40: add pinmux settings for MMC3 and UARTs 2,4,5&7 arm: allwinner: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C arch/arm/dts/Makefile | 3 +- arch/arm/dts/sun8i-r40-feta40i.dtsi | 106 +++++++++++++++ arch/arm/dts/sun8i-r40-oka40i-c.dts | 203 ++++++++++++++++++++++++++++ arch/arm/dts/sun8i-r40.dtsi | 43 ++++++ configs/OKA40i_defconfig | 35 +++++ 5 files changed, 389 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/sun8i-r40-feta40i.dtsi create mode 100644 arch/arm/dts/sun8i-r40-oka40i-c.dts create mode 100644 configs/OKA40i_defconfig -- 2.32.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] arm: allwinner: r40: add pinmux settings for MMC3 and UARTs 2, 4, 5&7 2021-07-15 10:18 [PATCH 0/2] arm: allwinner: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C Ivan Uvarov @ 2021-07-15 10:18 ` Ivan Uvarov 2021-07-15 22:23 ` [PATCH 1/2] arm: allwinner: r40: add pinmux settings for MMC3 and UARTs 2,4,5&7 Andre Przywara 2021-07-15 10:19 ` [PATCH 2/2] arm: allwinner: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C Ivan Uvarov 1 sibling, 1 reply; 5+ messages in thread From: Ivan Uvarov @ 2021-07-15 10:18 UTC (permalink / raw) To: u-boot; +Cc: Andre Przywara, Chen-Yu Tsai, Ivan Uvarov The Forlinx OKA40i-C devboard makes use of UARTs 0,2,3,4,5 and 7 of the R40 SoC, of which UART 0 is connected to an RS232 converter, UART 5 routed to an RS485 converter, and the rest broken out directly via labeled headers. The board also contains a micro-SD slot connected to SDC3. This patch adds settings to R40's pinmux node for those UARTs that were not already mapped, which would allow us to make use of all available UARTs and the micro-SD slot on this board in a further patch. The patch also adds the /omit-if-no-ref/ keyword to the existing nodes for UART0 and UART3 for consistency. Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com> 1 file changed, 43 insertions(+) diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi index d5ad3b9efd..51031a0e59 100644 --- a/arch/arm/dts/sun8i-r40.dtsi +++ b/arch/arm/dts/sun8i-r40.dtsi @@ -357,6 +357,8 @@ clock-names = "ahb", "mmc"; resets = <&ccu RST_BUS_MMC3>; reset-names = "ahb"; + pinctrl-0 = <&mmc3_pins>; + pinctrl-names = "default"; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; #address-cells = <1>; @@ -601,6 +603,14 @@ bias-pull-up; }; + mmc3_pins: mmc3-pins { + pins = "PI4", "PI5", "PI6", + "PI7", "PI8", "PI9"; + function = "mmc3"; + drive-strength = <30>; + bias-pull-up; + }; + /omit-if-no-ref/ spi0_pc_pins: spi0-pc-pins { pins = "PC0", "PC1", "PC2"; @@ -631,20 +641,53 @@ function = "spi1"; }; + /omit-if-no-ref/ uart0_pb_pins: uart0-pb-pins { pins = "PB22", "PB23"; function = "uart0"; }; + /omit-if-no-ref/ + uart2_pi_pins: uart2-pi-pins { + pins = "PI18", "PI19"; + function = "uart2"; + }; + + /omit-if-no-ref/ + uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{ + pins = "PI16", "PI17"; + function = "uart2"; + }; + + /omit-if-no-ref/ uart3_pg_pins: uart3-pg-pins { pins = "PG6", "PG7"; function = "uart3"; }; + /omit-if-no-ref/ uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { pins = "PG8", "PG9"; function = "uart3"; }; + + /omit-if-no-ref/ + uart4_pg_pins: uart4-pg-pins { + pins = "PG10", "PG11"; + function = "uart4"; + }; + + /omit-if-no-ref/ + uart5_ph_pins: uart5-ph-pins { + pins = "PH6", "PH7"; + function = "uart5"; + }; + + /omit-if-no-ref/ + uart7_pi_pins: uart7-pi-pins { + pins = "PI20", "PI21"; + function = "uart7"; + }; }; wdt: watchdog@1c20c90 { -- 2.32.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] arm: allwinner: r40: add pinmux settings for MMC3 and UARTs 2,4,5&7 2021-07-15 10:18 ` [PATCH 1/2] arm: allwinner: r40: add pinmux settings for MMC3 and UARTs 2, 4, 5&7 Ivan Uvarov @ 2021-07-15 22:23 ` Andre Przywara 0 siblings, 0 replies; 5+ messages in thread From: Andre Przywara @ 2021-07-15 22:23 UTC (permalink / raw) To: Ivan Uvarov; +Cc: u-boot, Chen-Yu Tsai, Jagan Teki On Thu, 15 Jul 2021 13:18:59 +0300 Ivan Uvarov <i.uvarov@cognitivepilot.com> wrote: Hi Ivan, > The Forlinx OKA40i-C devboard makes use of UARTs 0,2,3,4,5 and 7 of the R40 > SoC, of which UART 0 is connected to an RS232 converter, UART 5 routed to > an RS485 converter, and the rest broken out directly via labeled headers. > The board also contains a micro-SD slot connected to SDC3. > > This patch adds settings to R40's pinmux node for those UARTs that were not > already mapped, which would allow us to make use of all available UARTs and > the micro-SD slot on this board in a further patch. > > The patch also adds the /omit-if-no-ref/ keyword to the existing nodes for > UART0 and UART3 for consistency. Please keep exactly to the files as committed to Linux. Just copy the file from v5.14-rc1 over, as you did before, on the last r40.dtsi update - and adjust the subject accordingly (update .dtsi ...). You can then mention what thing brings and why briefly in the commit message. > Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com> > > 1 file changed, 43 insertions(+) Not sure where this line comes from, that's typically not part of the patch (but created by git on-the-fly, if needed). Cheers, Andre > > diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi > index d5ad3b9efd..51031a0e59 100644 > --- a/arch/arm/dts/sun8i-r40.dtsi > +++ b/arch/arm/dts/sun8i-r40.dtsi > @@ -357,6 +357,8 @@ > clock-names = "ahb", "mmc"; > resets = <&ccu RST_BUS_MMC3>; > reset-names = "ahb"; > + pinctrl-0 = <&mmc3_pins>; > + pinctrl-names = "default"; > interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; > status = "disabled"; > #address-cells = <1>; > @@ -601,6 +603,14 @@ > bias-pull-up; > }; > > + mmc3_pins: mmc3-pins { > + pins = "PI4", "PI5", "PI6", > + "PI7", "PI8", "PI9"; > + function = "mmc3"; > + drive-strength = <30>; > + bias-pull-up; > + }; > + > /omit-if-no-ref/ > spi0_pc_pins: spi0-pc-pins { > pins = "PC0", "PC1", "PC2"; > @@ -631,20 +641,53 @@ > function = "spi1"; > }; > > + /omit-if-no-ref/ > uart0_pb_pins: uart0-pb-pins { > pins = "PB22", "PB23"; > function = "uart0"; > }; > > + /omit-if-no-ref/ > + uart2_pi_pins: uart2-pi-pins { > + pins = "PI18", "PI19"; > + function = "uart2"; > + }; > + > + /omit-if-no-ref/ > + uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{ > + pins = "PI16", "PI17"; > + function = "uart2"; > + }; > + > + /omit-if-no-ref/ > uart3_pg_pins: uart3-pg-pins { > pins = "PG6", "PG7"; > function = "uart3"; > }; > > + /omit-if-no-ref/ > uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { > pins = "PG8", "PG9"; > function = "uart3"; > }; > + > + /omit-if-no-ref/ > + uart4_pg_pins: uart4-pg-pins { > + pins = "PG10", "PG11"; > + function = "uart4"; > + }; > + > + /omit-if-no-ref/ > + uart5_ph_pins: uart5-ph-pins { > + pins = "PH6", "PH7"; > + function = "uart5"; > + }; > + > + /omit-if-no-ref/ > + uart7_pi_pins: uart7-pi-pins { > + pins = "PI20", "PI21"; > + function = "uart7"; > + }; > }; > > wdt: watchdog@1c20c90 { ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] arm: allwinner: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C 2021-07-15 10:18 [PATCH 0/2] arm: allwinner: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C Ivan Uvarov 2021-07-15 10:18 ` [PATCH 1/2] arm: allwinner: r40: add pinmux settings for MMC3 and UARTs 2, 4, 5&7 Ivan Uvarov @ 2021-07-15 10:19 ` Ivan Uvarov 2021-07-15 22:58 ` Andre Przywara 1 sibling, 1 reply; 5+ messages in thread From: Ivan Uvarov @ 2021-07-15 10:19 UTC (permalink / raw) To: u-boot; +Cc: Andre Przywara, Chen-Yu Tsai, Ivan Uvarov The FETA40i-C is a SoM by Forlinx based on the Allwinner R40/A40i. SoM specifications: - SoC: R40 or A40i - PMIC: AXP221S - RAM: 1GiB/2GiB DDR3 (dual-rank) - eMMC: 8GB, - Mates with carrier board via four 80-pin connectors (AXK6F80337YG). OKA40i-C is a carrier board by the same manufacturer for this SoM, whose main purpose is as a development board with a wide variety of peripherals: - Power: DC5V barrel or USB OTG or 4.2V Lipo battery - Video out: HDMI, TV out, LVDS - WiFi+Bluetooth: RL-UM02WBS-8723BU-V1.2 (802.11 b/g/n, BT V2.1/3.0/4.0) - Ethernet: 10/100Mbps - Storage: µSD, fullsize SD, eMMC (on SoM), SATA - USB: 3 x USB2.0 Host (2 via hub, 1 native), 1 x USB2.0 OTG (micro-B) - UART: RS232, RS485, 4 3.3v uarts (of which 2 have RTS/CTS) - Other I/O: SPI x2, TWI, SDIO header, GPIO header, JTAG header - Mini PCIe slot with sim holder for WLAN modem - Smart card holder - RTC (RX8010SJ) - Two user LEDs - Three user buttons (via KeyADC). This patch adds a devicetree for the aforementioned SoM and devboard. In order to reflect the modularity of this devboard and simplify adding support for future hardware based on the same SoM, the devicetree is split: Everything pertaining to the SoM itself is described in a separate .dtsi file, which is included by the devboard's .dts. Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com> 4 files changed, 346 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9fb38682e6..a6e6fd99c8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -611,7 +611,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h3-rervision-dvk.dtb dtb-$(CONFIG_MACH_SUN8I_R40) += \ sun8i-r40-bananapi-m2-ultra.dtb \ - sun8i-v40-bananapi-m2-berry.dtb + sun8i-v40-bananapi-m2-berry.dtb \ + sun8i-r40-oka40i-c.dtb dtb-$(CONFIG_MACH_SUN8I_V3S) += \ sun8i-s3-pinecube.dtb \ sun8i-v3s-licheepi-zero.dtb diff --git a/arch/arm/dts/sun8i-r40-feta40i.dtsi b/arch/arm/dts/sun8i-r40-feta40i.dtsi new file mode 100644 index 0000000000..265e0fa57a --- /dev/null +++ b/arch/arm/dts/sun8i-r40-feta40i.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com> +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is: +// Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org> +// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> + +#include "sun8i-r40.dtsi" + +&i2c0 { + status = "okay"; + + axp22x: pmic@34 { + compatible = "x-powers,axp221"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +&mmc2 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_aldo2>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&pio { + pinctrl-names = "default"; + pinctrl-0 = <&clk_out_a_pin>; + vcc-pa-supply = <®_dcdc1>; + vcc-pc-supply = <®_aldo2>; + vcc-pd-supply = <®_dcdc1>; + vcc-pf-supply = <®_dldo4>; + vcc-pg-supply = <®_dldo1>; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pa"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-io"; +}; + +®_dldo4 { + regulator-always-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-name = "vdd2v5-sata"; +}; + +®_eldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd1v2-sata"; +}; + +®_eldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc-pe"; +}; diff --git a/arch/arm/dts/sun8i-r40-oka40i-c.dts b/arch/arm/dts/sun8i-r40-oka40i-c.dts new file mode 100644 index 0000000000..0bd1336206 --- /dev/null +++ b/arch/arm/dts/sun8i-r40-oka40i-c.dts @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com> +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is: +// Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org> +// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> + +/dts-v1/; +#include "sun8i-r40-feta40i.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +/ { + model = "Forlinx OKA40i-C"; + compatible = "forlinx,oka40i-c", "forlinx,feta40i-c", "allwinner,sun8i-r40"; + + aliases { + ethernet0 = &gmac; + serial0 = &uart0; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; /* RS485 */ + serial7 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-5 { /* this is how the leds are labeled on the board */ + gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */ + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + }; + + led-6 { + gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_STATUS; + }; + }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN + clocks = <&ccu CLK_OUTA>; + clock-names = "ext_clock"; + }; +}; + +&ahci { + ahci-supply = <®_dldo4>; + phy-supply = <®_eldo2>; + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_rgmii_pins>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + phy-supply = <®_dcdc1>; + status = "okay"; +}; + +&gmac_mdio { + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 8 11 GPIO_ACTIVE_LOW>; // PI11 + status = "okay"; +}; + +&mmc3 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 8 10 GPIO_ACTIVE_LOW>; // PI10 + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +®_dc1sw { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-lcd"; +}; + +®_dldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +&tcon_tv0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pi_pins>, <&uart2_rts_cts_pi_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pg_pins>; + status = "okay"; +}; + +&uart5 { /* RS485 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart5_ph_pins>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pi_pins>; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v0>; + usb2_vbus-supply = <®_vcc5v0>; + status = "okay"; +}; diff --git a/configs/OKA40i_defconfig b/configs/OKA40i_defconfig new file mode 100644 index 0000000000..fbd54e3843 --- /dev/null +++ b/configs/OKA40i_defconfig @@ -0,0 +1,35 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN8I_R40=y +CONFIG_DRAM_CLK=576 +# CONFIG_DRAM_ZQ=0x003b3bfb +#CONFIG_DRAM_EMR1=4 +#CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y +CONFIG_MMC0_CD_PIN="PI11" +CONFIG_MMC3_CD_PIN="PI10" +CONFIG_USB0_VBUS_DET="PH17" +CONFIG_USB0_VBUS_PIN="PH13" +CONFIG_USB0_ID_DET="PH21" +CONFIG_USB1_VBUS_PIN="" +CONFIG_USB2_VBUS_PIN="" +#CONFIG_USB1_VBUS_PIN="PH23" +#CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-feta40i-c" +CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-oka40i-c" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +# CONFIG_AHCI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C_SUPPORT=y +# CONFIG_SCSI_AHCI=y +CONFIG_RGMII=y +CONFIG_SUN4I_EMAC=y +CONFIG_SUNXI_GMAC=y +CONFIG_SUN8I_EMAC=y +CONFIG_AXP_ALDO2_VOLT=1800 +CONFIG_AXP_DLDO4_VOLT=2500 +#CONFIG_AXP_ELDO3_VOLT=1200 +CONFIG_AXP_ELDO2_VOLT=1200 +CONFIG_SCSI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_RTC_DRV_RX8010=y -- 2.32.0 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] arm: allwinner: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C 2021-07-15 10:19 ` [PATCH 2/2] arm: allwinner: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C Ivan Uvarov @ 2021-07-15 22:58 ` Andre Przywara 0 siblings, 0 replies; 5+ messages in thread From: Andre Przywara @ 2021-07-15 22:58 UTC (permalink / raw) To: Ivan Uvarov; +Cc: u-boot, Chen-Yu Tsai On Thu, 15 Jul 2021 13:19:00 +0300 Ivan Uvarov <i.uvarov@cognitivepilot.com> wrote: Hi Ivan, thanks for sending this upstream! > The FETA40i-C is a SoM by Forlinx based on the Allwinner R40/A40i. > > SoM specifications: > > - SoC: R40 or A40i > - PMIC: AXP221S > - RAM: 1GiB/2GiB DDR3 (dual-rank) > - eMMC: 8GB, > - Mates with carrier board via four 80-pin connectors (AXK6F80337YG). > > OKA40i-C is a carrier board by the same manufacturer for this SoM, > whose main purpose is as a development board with a wide variety of > peripherals: > > - Power: DC5V barrel or USB OTG or 4.2V Lipo battery > - Video out: HDMI, TV out, LVDS > - WiFi+Bluetooth: RL-UM02WBS-8723BU-V1.2 (802.11 b/g/n, BT V2.1/3.0/4.0) > - Ethernet: 10/100Mbps > - Storage: µSD, fullsize SD, eMMC (on SoM), SATA > - USB: 3 x USB2.0 Host (2 via hub, 1 native), 1 x USB2.0 OTG (micro-B) > - UART: RS232, RS485, 4 3.3v uarts (of which 2 have RTS/CTS) > - Other I/O: SPI x2, TWI, SDIO header, GPIO header, JTAG header > - Mini PCIe slot with sim holder for WLAN modem > - Smart card holder > - RTC (RX8010SJ) > - Two user LEDs > - Three user buttons (via KeyADC). > > This patch adds a devicetree for the aforementioned SoM and devboard. > In order to reflect the modularity of this devboard and simplify adding > support for future hardware based on the same SoM, the devicetree is split: > Everything pertaining to the SoM itself is described in a separate .dtsi > file, which is included by the devboard's .dts. So the .dts and .dtsi files are fine, as they are direct copies of the Linux versions. However I am not so happy with the defconfig, see below: > > Signed-off-by: Ivan Uvarov <i.uvarov@cognitivepilot.com> > > 4 files changed, 346 insertions(+), 1 deletion(-) again weird line here ... > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index 9fb38682e6..a6e6fd99c8 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -611,7 +611,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ > sun8i-h3-rervision-dvk.dtb > dtb-$(CONFIG_MACH_SUN8I_R40) += \ > sun8i-r40-bananapi-m2-ultra.dtb \ > - sun8i-v40-bananapi-m2-berry.dtb > + sun8i-v40-bananapi-m2-berry.dtb \ > + sun8i-r40-oka40i-c.dtb > dtb-$(CONFIG_MACH_SUN8I_V3S) += \ > sun8i-s3-pinecube.dtb \ > sun8i-v3s-licheepi-zero.dtb > diff --git a/arch/arm/dts/sun8i-r40-feta40i.dtsi b/arch/arm/dts/sun8i-r40-feta40i.dtsi > new file mode 100644 > index 0000000000..265e0fa57a > --- /dev/null > +++ b/arch/arm/dts/sun8i-r40-feta40i.dtsi > @@ -0,0 +1,106 @@ > +// SPDX-License-Identifier: GPL-2.0+ OR MIT > +// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com> > +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is: > +// Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org> > +// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> > + > +#include "sun8i-r40.dtsi" > + > +&i2c0 { > + status = "okay"; > + > + axp22x: pmic@34 { > + compatible = "x-powers,axp221"; > + reg = <0x34>; > + interrupt-parent = <&nmi_intc>; > + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; > + }; > +}; > + > +#include "axp22x.dtsi" > + > +&mmc2 { > + vmmc-supply = <®_dcdc1>; > + vqmmc-supply = <®_aldo2>; > + bus-width = <8>; > + non-removable; > + status = "okay"; > +}; > + > +&pio { > + pinctrl-names = "default"; > + pinctrl-0 = <&clk_out_a_pin>; > + vcc-pa-supply = <®_dcdc1>; > + vcc-pc-supply = <®_aldo2>; > + vcc-pd-supply = <®_dcdc1>; > + vcc-pf-supply = <®_dldo4>; > + vcc-pg-supply = <®_dldo1>; > +}; > + > +®_aldo2 { > + regulator-always-on; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-name = "vcc-pa"; > +}; > + > +®_aldo3 { > + regulator-always-on; > + regulator-min-microvolt = <3000000>; > + regulator-max-microvolt = <3000000>; > + regulator-name = "avcc"; > +}; > + > +®_dcdc1 { > + regulator-always-on; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-name = "vcc-3v3"; > +}; > + > +®_dcdc2 { > + regulator-always-on; > + regulator-min-microvolt = <1100000>; > + regulator-max-microvolt = <1100000>; > + regulator-name = "vdd-cpu"; > +}; > + > +®_dcdc3 { > + regulator-always-on; > + regulator-min-microvolt = <1100000>; > + regulator-max-microvolt = <1100000>; > + regulator-name = "vdd-sys"; > +}; > + > +®_dcdc5 { > + regulator-always-on; > + regulator-min-microvolt = <1500000>; > + regulator-max-microvolt = <1500000>; > + regulator-name = "vcc-dram"; > +}; > + > +®_dldo1 { > + regulator-always-on; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-name = "vcc-wifi-io"; > +}; > + > +®_dldo4 { > + regulator-always-on; > + regulator-min-microvolt = <2500000>; > + regulator-max-microvolt = <2500000>; > + regulator-name = "vdd2v5-sata"; > +}; > + > +®_eldo2 { > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + regulator-name = "vdd1v2-sata"; > +}; > + > +®_eldo3 { > + regulator-min-microvolt = <2800000>; > + regulator-max-microvolt = <2800000>; > + regulator-name = "vcc-pe"; > +}; > diff --git a/arch/arm/dts/sun8i-r40-oka40i-c.dts b/arch/arm/dts/sun8i-r40-oka40i-c.dts > new file mode 100644 > index 0000000000..0bd1336206 > --- /dev/null > +++ b/arch/arm/dts/sun8i-r40-oka40i-c.dts > @@ -0,0 +1,203 @@ > +// SPDX-License-Identifier: GPL-2.0+ OR MIT > +// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com> > +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is: > +// Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org> > +// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> > + > +/dts-v1/; > +#include "sun8i-r40-feta40i.dtsi" > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/leds/common.h> > + > +/ { > + model = "Forlinx OKA40i-C"; > + compatible = "forlinx,oka40i-c", "forlinx,feta40i-c", "allwinner,sun8i-r40"; > + > + aliases { > + ethernet0 = &gmac; > + serial0 = &uart0; > + serial2 = &uart2; > + serial3 = &uart3; > + serial4 = &uart4; > + serial5 = &uart5; /* RS485 */ > + serial7 = &uart7; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + connector { > + compatible = "hdmi-connector"; > + type = "a"; > + > + port { > + hdmi_con_in: endpoint { > + remote-endpoint = <&hdmi_out_con>; > + }; > + }; > + }; > + > + leds { > + compatible = "gpio-leds"; > + > + led-5 { /* this is how the leds are labeled on the board */ > + gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */ > + color = <LED_COLOR_ID_GREEN>; > + function = LED_FUNCTION_STATUS; > + }; > + > + led-6 { > + gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */ > + color = <LED_COLOR_ID_BLUE>; > + function = LED_FUNCTION_STATUS; > + }; > + }; > + > + reg_vcc5v0: vcc5v0 { > + compatible = "regulator-fixed"; > + regulator-name = "vcc5v0"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + }; > + > + wifi_pwrseq: wifi_pwrseq { > + compatible = "mmc-pwrseq-simple"; > + reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN > + clocks = <&ccu CLK_OUTA>; > + clock-names = "ext_clock"; > + }; > +}; > + > +&ahci { > + ahci-supply = <®_dldo4>; > + phy-supply = <®_eldo2>; > + status = "okay"; > +}; > + > +&de { > + status = "okay"; > +}; > + > +&ehci1 { > + status = "okay"; > +}; > + > +&ehci2 { > + status = "okay"; > +}; > + > +&gmac { > + pinctrl-names = "default"; > + pinctrl-0 = <&gmac_rgmii_pins>; > + phy-handle = <&phy1>; > + phy-mode = "rgmii-id"; > + phy-supply = <®_dcdc1>; > + status = "okay"; > +}; > + > +&gmac_mdio { > + phy1: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; > + }; > +}; > + > +&hdmi { > + status = "okay"; > +}; > + > +&hdmi_out { > + hdmi_out_con: endpoint { > + remote-endpoint = <&hdmi_con_in>; > + }; > +}; > + > +&i2c2 { > + status = "okay"; > +}; > + > +&mmc0 { > + vmmc-supply = <®_dcdc1>; > + vqmmc-supply = <®_dcdc1>; > + bus-width = <4>; > + cd-gpios = <&pio 8 11 GPIO_ACTIVE_LOW>; // PI11 > + status = "okay"; > +}; > + > +&mmc3 { > + vmmc-supply = <®_dcdc1>; > + vqmmc-supply = <®_dcdc1>; > + bus-width = <4>; > + cd-gpios = <&pio 8 10 GPIO_ACTIVE_LOW>; // PI10 > + status = "okay"; > +}; > + > +&ohci1 { > + status = "okay"; > +}; > + > +&ohci2 { > + status = "okay"; > +}; > + > +®_dc1sw { > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-name = "vcc-lcd"; > +}; > + > +®_dldo2 { > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-name = "vcc-wifi"; > +}; > + > +&tcon_tv0 { > + status = "okay"; > +}; > + > +&uart0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart0_pb_pins>; > + status = "okay"; > +}; > + > +&uart2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart2_pi_pins>, <&uart2_rts_cts_pi_pins>; > + uart-has-rtscts; > + status = "okay"; > +}; > + > +&uart3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>; > + uart-has-rtscts; > + status = "okay"; > +}; > + > +&uart4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart4_pg_pins>; > + status = "okay"; > +}; > + > +&uart5 { /* RS485 */ > + pinctrl-names = "default"; > + pinctrl-0 = <&uart5_ph_pins>; > + status = "okay"; > +}; > + > +&uart7 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart7_pi_pins>; > + status = "okay"; > +}; > + > +&usbphy { > + usb1_vbus-supply = <®_vcc5v0>; > + usb2_vbus-supply = <®_vcc5v0>; > + status = "okay"; > +}; > diff --git a/configs/OKA40i_defconfig b/configs/OKA40i_defconfig > new file mode 100644 > index 0000000000..fbd54e3843 > --- /dev/null > +++ b/configs/OKA40i_defconfig > @@ -0,0 +1,35 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_SUNXI=y > +CONFIG_SPL=y > +CONFIG_MACH_SUN8I_R40=y > +CONFIG_DRAM_CLK=576 > +# CONFIG_DRAM_ZQ=0x003b3bfb > +#CONFIG_DRAM_EMR1=4 > +#CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y What are all those commented lines about? > +CONFIG_MMC0_CD_PIN="PI11" > +CONFIG_MMC3_CD_PIN="PI10" > +CONFIG_USB0_VBUS_DET="PH17" > +CONFIG_USB0_VBUS_PIN="PH13" > +CONFIG_USB0_ID_DET="PH21" > +CONFIG_USB1_VBUS_PIN="" > +CONFIG_USB2_VBUS_PIN="" > +#CONFIG_USB1_VBUS_PIN="PH23" > +#CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-feta40i-c" same here > +CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-oka40i-c" > +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 > +# CONFIG_AHCI=y Why is this disabled? I think you need all of CONFIG_AHCI, CONFIG_SCSI_AHCI and CONFIG_SCSI for SATA to work? > +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set > +CONFIG_SPL_I2C_SUPPORT=y > +# CONFIG_SCSI_AHCI=y > +CONFIG_RGMII=y > +CONFIG_SUN4I_EMAC=y While the R40 might have this IP, this doesn't work without the respective DT node, does it? And I don't see a second Ethernet connector on the board, so would this actually be usable on this hardware? Does the board expose the PH MII pins somewhere, so that one could connect a PHY and use EMAC and GMAC at the same time? > +CONFIG_SUNXI_GMAC=y This one does not exist? > +CONFIG_SUN8I_EMAC=y > +CONFIG_AXP_ALDO2_VOLT=1800 > +CONFIG_AXP_DLDO4_VOLT=2500 > +#CONFIG_AXP_ELDO3_VOLT=1200 > +CONFIG_AXP_ELDO2_VOLT=1200 > +CONFIG_SCSI=y > +CONFIG_USB_EHCI_HCD=y > +CONFIG_USB_OHCI_HCD=y > +CONFIG_RTC_DRV_RX8010=y In general remove everything that is "=y", but commented. An easy way to get the shortest defconfig is: $ make OKA40i_defconfig $ make savedefconfig $ cp defconfig configs/OKA40i_defconfig The latter will be done automatically at some point anyway, so you could start clean as well. Cheers, Andre ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-07-15 22:59 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-07-15 10:18 [PATCH 0/2] arm: allwinner: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C Ivan Uvarov 2021-07-15 10:18 ` [PATCH 1/2] arm: allwinner: r40: add pinmux settings for MMC3 and UARTs 2, 4, 5&7 Ivan Uvarov 2021-07-15 22:23 ` [PATCH 1/2] arm: allwinner: r40: add pinmux settings for MMC3 and UARTs 2,4,5&7 Andre Przywara 2021-07-15 10:19 ` [PATCH 2/2] arm: allwinner: r40: add devicetree for Forlinx FETA40i-C & OKA40i-C Ivan Uvarov 2021-07-15 22:58 ` Andre Przywara
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