[PATCH 0/9] j721e: Add HyperFlash boot support

[PATCH 0/9] j721e: Add HyperFlash boot support

[Vaishnav Achath]

This series adds support for Hyperflash boot for J721E, the changeset
includes the missing pieces from:
https://lore.kernel.org/all/20191010055207.26831-1-vigneshr@ti.com/T/#r2f1578fff04474473c82261670b88d2af16841ef
and minor changes to support both OSPI and HyperFlash boot based on
the Hypermux selection state similar to as done for J7200.

Changes were tested on J721E SR1.1 for Hyperflash and OSPI boot.

Thanks and Regards,
Vaishnav

Vaishnav Achath (9):
  arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node
  arm: dts: k3-j721e-som-p0: Add HyperFlash node
  arm: dts: k3-j721e-r5-common-proc-board: Add HyperFlash node
  arm: dts: k3-j721e-common-proc-board-u-boot: enable HyperFlash in SPL
  arm: dts: k3-j721e-common-proc-board: enable  hyperflash mux sel GPIO
  arm: k3: sysfw-loader: add hyperflash support
  configs: j721e_evm.h: define CONFIG_SYS_FLASH_BASE
  ti: j721e: enable hyperflash spl fixup for j721e
  configs: j721e_evm_defconfig: Add HBMC related configs

 .../k3-j721e-common-proc-board-u-boot.dtsi    | 24 ++++++++
 arch/arm/dts/k3-j721e-common-proc-board.dts   | 11 ++++
 arch/arm/dts/k3-j721e-mcu-wakeup.dtsi         | 20 ++++++-
 .../arm/dts/k3-j721e-r5-common-proc-board.dts | 45 +++++++++++++++
 arch/arm/dts/k3-j721e-som-p0.dtsi             | 32 +++++++++++
 arch/arm/mach-k3/sysfw-loader.c               | 28 +++++++++
 board/ti/j721e/evm.c                          | 57 ++++++++++++++++++-
 configs/j721e_evm_a72_defconfig               |  5 ++
 configs/j721e_evm_r5_defconfig                | 14 +++++
 include/configs/j721e_evm.h                   |  2 +
 10 files changed, 234 insertions(+), 4 deletions(-)

-- 
2.17.1

[PATCH 1/9] arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node

[Vaishnav Achath]

Add DT node for HyperBus Memory Controller and hbmc-mux in the
FSS. hbmc-am654 driver uses syscon_get_regmap() call which fails
with current compatible setting.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
 arch/arm/dts/k3-j721e-mcu-wakeup.dtsi | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
index d2dceda72f..22166c7942 100644
--- a/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j721e-mcu-wakeup.dtsi
@@ -170,12 +170,30 @@
 	};
 
 	fss: fss@47000000 {
-		compatible = "simple-bus";
+		compatible = "syscon", "simple-mfd";
 		reg = <0x0 0x47000000 0x0 0x100>;
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;
 
+		hbmc_mux: hbmc-mux {
+			compatible = "mmio-mux";
+			#mux-control-cells = <1>;
+			mux-reg-masks = <0x4 0x2>; /* HBMC select */
+		};
+
+		hbmc: hyperbus@47034000 {
+			compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
+			reg = <0x0 0x47034000 0x0 0x100>,
+				<0x5 0x00000000 0x1 0x0000000>;
+			power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+			#address-cells = <2>;
+			#size-cells = <1>;
+			mux-controls = <&hbmc_mux 0>;
+			assigned-clocks = <&k3_clks 102 0>;
+			assigned-clock-rates = <250000000>;
+		};
+
 		ospi0: spi@47040000 {
 			compatible = "ti,am654-ospi", "cdns,qspi-nor";
 			reg = <0x0 0x47040000 0x0 0x100>,
-- 
2.17.1

Re: [PATCH 1/9] arm: dts: k3-j721e-mcu-wakeup: Add HyperBus Controller node

[Tom Rini]

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On Mon, May 09, 2022 at 11:50:09AM +0530, Vaishnav Achath wrote:

> Add DT node for HyperBus Memory Controller and hbmc-mux in the
> FSS. hbmc-am654 driver uses syscon_get_regmap() call which fails
> with current compatible setting.
> 
> Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>

For the series, applied to u-boot/next, thanks!

-- 
Tom

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[PATCH 2/9] arm: dts: k3-j721e-som-p0: Add HyperFlash node

[Vaishnav Achath]

J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node
for the same.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
 arch/arm/dts/k3-j721e-som-p0.dtsi | 32 +++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/dts/k3-j721e-som-p0.dtsi b/arch/arm/dts/k3-j721e-som-p0.dtsi
index 2fee290618..a725435849 100644
--- a/arch/arm/dts/k3-j721e-som-p0.dtsi
+++ b/arch/arm/dts/k3-j721e-som-p0.dtsi
@@ -150,6 +150,25 @@
 		>;
 	};
 
+	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
+			J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
+			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
+			J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
+			J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
+			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
+			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
+			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
+			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
+			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
+			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
+			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
+			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
+			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
+		>;
+	};
+
 	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
 		pinctrl-single,pins = <
 			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
@@ -167,6 +186,19 @@
 	};
 };
 
+&hbmc {
+	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
+	ranges = <0x0 0x0 0x5 0x0 0x4000000>, /* 64MB Flash on CS0 */
+		 <0x1 0x0 0x5 0x4000000 0x800000>; /* 8MB RAM on CS1 */
+
+	flash@0,0 {
+		compatible = "cypress,hyperflash", "cfi-flash";
+		reg = <0x0 0x0 0x4000000>;
+	};
+};
+
 &ospi0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-- 
2.17.1

[PATCH 3/9] arm: dts: k3-j721e-r5-common-proc-board: Add HyperFlash node

[Vaishnav Achath]

J721e SoM as a 64MB HyperFlash on board. Add pinmux and DT node
for the same.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
 .../arm/dts/k3-j721e-r5-common-proc-board.dts | 45 +++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index a14b148e11..ab9d6e65d8 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -129,6 +129,31 @@
 		>;
 	};
 
+	mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
+			J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
+			J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
+			J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
+			J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
+			J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
+			J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
+			J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
+			J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
+			J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
+			J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
+			J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
+			J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
+			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
+		>;
+	};
+
+	wkup_gpio_pins_default: wkup-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* WKUP_GPIO0_8 */
+		>;
+	};
+
 	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
 		pinctrl-single,pins = <
 			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
@@ -207,6 +232,11 @@
 	status = "okay";
 };
 
+&wkup_gpio0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&wkup_gpio_pins_default>;
+};
+
 &mcu_uart0 {
 	/delete-property/ power-domains;
 	/delete-property/ clocks;
@@ -307,6 +337,21 @@
 	};
 };
 
+&hbmc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
+	reg = <0x0 0x47040000 0x0 0x100>,
+		<0x0 0x50000000 0x0 0x8000000>;
+	ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
+		 <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
+
+	flash@0,0 {
+		compatible = "cypress,hyperflash", "cfi-flash";
+		reg = <0x0 0x0 0x4000000>;
+	};
+};
+
 &ospi0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-- 
2.17.1

[PATCH 4/9] arm: dts: k3-j721e-common-proc-board-u-boot: enable HyperFlash in SPL

[Vaishnav Achath]

add u-boot,dm-spl pre-relocation property to enable hbmc in SPL.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
 .../k3-j721e-common-proc-board-u-boot.dtsi    | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 677a72d2a2..b2b81f804d 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -192,6 +192,22 @@
 	u-boot,dm-spl;
 };
 
+&hbmc {
+	u-boot,dm-spl;
+
+	flash@0,0 {
+		u-boot,dm-spl;
+	};
+};
+
+&hbmc_mux {
+	u-boot,dm-spl;
+};
+
+&wkup_gpio0 {
+	u-boot,dm-spl;
+};
+
 &ospi0 {
 	u-boot,dm-spl;
 
@@ -208,6 +224,14 @@
 	};
 };
 
+&mcu_fss0_hpb0_pins_default {
+	u-boot,dm-spl;
+};
+
+&wkup_gpio_pins_default {
+	u-boot,dm-spl;
+};
+
 &mcu_fss0_ospi1_pins_default {
 	u-boot,dm-spl;
 };
-- 
2.17.1

[PATCH 5/9] arm: dts: k3-j721e-common-proc-board: enable hyperflash mux sel GPIO

[Vaishnav Achath]

Add wkup_gpio pinmux setting which will be used for performing the
DT fixup for hbmc node according to mux selection state, on J721E
EVM, hypermux sel is tied to ·WKUP_GPIO0_8.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
 arch/arm/dts/k3-j721e-common-proc-board.dts | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts b/arch/arm/dts/k3-j721e-common-proc-board.dts
index f3b6302a43..1b600547c0 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -213,6 +213,12 @@
 		>;
 	};
 
+	wkup_gpio_pins_default: wkup-gpio-pins-default {
+		pinctrl-single,pins = <
+			J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
+		>;
+	};
+
 	mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
 		pinctrl-single,pins = <
 			J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
@@ -381,6 +387,11 @@
 	phy-names = "cdns3,usb3-phy";
 };
 
+&wkup_gpio0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&wkup_gpio_pins_default>;
+};
+
 &usbss1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&main_usbss1_pins_default>;
-- 
2.17.1

[PATCH 6/9] arm: k3: sysfw-loader: add hyperflash support

[Vaishnav Achath]

add support for loading system firmware from hyperflash.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
 arch/arm/mach-k3/sysfw-loader.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 5e48c36ccd..988e758629 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -346,6 +346,25 @@ static void k3_sysfw_spi_copy(u32 *dst, u32 *src, size_t len)
 }
 #endif
 
+#if CONFIG_IS_ENABLED(NOR_SUPPORT)
+static void *get_sysfw_hf_addr(void)
+{
+	struct udevice *dev;
+	fdt_addr_t addr;
+	int ret;
+
+	ret = uclass_find_first_device(UCLASS_MTD, &dev);
+	if (ret)
+		return NULL;
+
+	addr = dev_read_addr_index(dev, 1);
+	if (addr == FDT_ADDR_T_NONE)
+		return NULL;
+
+	return (void *)(addr + CONFIG_K3_SYSFW_IMAGE_SPI_OFFS);
+}
+#endif
+
 void k3_sysfw_loader(bool rom_loaded_sysfw,
 		     void (*config_pm_pre_callback)(void),
 		     void (*config_pm_done_callback)(void))
@@ -413,6 +432,15 @@ void k3_sysfw_loader(bool rom_loaded_sysfw,
 				  CONFIG_K3_SYSFW_IMAGE_SIZE_MAX);
 		break;
 #endif
+#if CONFIG_IS_ENABLED(NOR_SUPPORT)
+	case BOOT_DEVICE_HYPERFLASH:
+		sysfw_spi_base = get_sysfw_hf_addr();
+		if (!sysfw_spi_base)
+			ret = -ENODEV;
+		k3_sysfw_spi_copy(sysfw_load_address, sysfw_spi_base,
+				  CONFIG_K3_SYSFW_IMAGE_SIZE_MAX);
+		break;
+#endif
 #if CONFIG_IS_ENABLED(YMODEM_SUPPORT)
 	case BOOT_DEVICE_UART:
 #ifdef CONFIG_K3_EARLY_CONS
-- 
2.17.1

[PATCH 7/9] configs: j721e_evm.h: define CONFIG_SYS_FLASH_BASE

[Vaishnav Achath]

Define CONFIG_SYS_FLASH_BASE to indicate start address of
Flash memory

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
 include/configs/j721e_evm.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index 2590ee6b01..91dc52b9fd 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -17,6 +17,8 @@
 
 /* DDR Configuration */
 #define CONFIG_SYS_SDRAM_BASE1		0x880000000
+/* FLASH Configuration */
+#define CONFIG_SYS_FLASH_BASE		0x000000000
 
 /* SPL Loader Configuration */
 #if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM)
-- 
2.17.1

[PATCH 8/9] ti: j721e: enable hyperflash spl fixup for j721e

[Vaishnav Achath]

On j721e, its not possible to use OSPI0 and HBMC simultaneously as they
are muxed within the Flash Subsystem hence disable HBMC by default and
keep OSPI enabled. Bootloader will fixup DT when it detects HyperFlash
mux selection instead of OSPI.

Also updated detect_enable_hyperflash to use correct GPIO when checking
hypermux selection state:
* J7200 - hypermux sel connected to WKUP_GPIO0_6
* J721E - hypermux·sel·connected·to·WKUP_GPIO0_8

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
 board/ti/j721e/evm.c | 57 +++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 54 insertions(+), 3 deletions(-)

diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index e6ff54c065..105461e1db 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -109,11 +109,12 @@ int board_fit_config_name_match(const char *name)
 static void __maybe_unused detect_enable_hyperflash(void *blob)
 {
 	struct gpio_desc desc = {0};
+	char *hypermux_sel_gpio = (board_is_j721e_som()) ? "8" : "6";
 
-	if (dm_gpio_lookup_name("6", &desc))
+	if (dm_gpio_lookup_name(hypermux_sel_gpio, &desc))
 		return;
 
-	if (dm_gpio_request(&desc, "6"))
+	if (dm_gpio_request(&desc, hypermux_sel_gpio))
 		return;
 
 	if (dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN))
@@ -132,7 +133,8 @@ static void __maybe_unused detect_enable_hyperflash(void *blob)
 }
 #endif
 
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TARGET_J7200_A72_EVM)
+#if defined(CONFIG_SPL_BUILD) && (defined(CONFIG_TARGET_J7200_A72_EVM) || defined(CONFIG_TARGET_J7200_R5_EVM) || \
+					defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J721E_R5_EVM))
 void spl_perform_fixups(struct spl_image_info *spl_image)
 {
 	detect_enable_hyperflash(spl_image->fdt_addr);
@@ -490,6 +492,41 @@ int board_late_init(void)
 }
 #endif
 
+static int __maybe_unused detect_SW3_1_state(void)
+{
+	if (IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM)) {
+		struct gpio_desc desc = {0};
+		int ret;
+		char *hypermux_sel_gpio = (board_is_j721e_som()) ? "8" : "6";
+
+		ret = dm_gpio_lookup_name(hypermux_sel_gpio, &desc);
+		if (ret) {
+			printf("error getting GPIO lookup name: %d\n", ret);
+			return ret;
+		}
+
+		ret = dm_gpio_request(&desc, hypermux_sel_gpio);
+		if (ret) {
+			printf("error requesting GPIO: %d\n", ret);
+			goto err_free_gpio;
+		}
+
+		ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN);
+		if (ret) {
+			printf("error setting direction flag of GPIO: %d\n", ret);
+			goto err_free_gpio;
+		}
+
+		ret = dm_gpio_get_value(&desc);
+		if (ret < 0)
+			printf("error getting value of GPIO: %d\n", ret);
+
+err_free_gpio:
+		dm_gpio_free(desc.dev, &desc);
+		return ret;
+	}
+}
+
 void spl_board_init(void)
 {
 #if defined(CONFIG_ESM_K3) || defined(CONFIG_ESM_PMIC)
@@ -522,4 +559,18 @@ void spl_board_init(void)
 			printf("ESM PMIC init failed: %d\n", ret);
 	}
 #endif
+	if ((IS_ENABLED(CONFIG_TARGET_J7200_A72_EVM) || IS_ENABLED(CONFIG_TARGET_J721E_A72_EVM)) &&
+	    IS_ENABLED(CONFIG_HBMC_AM654)) {
+		struct udevice *dev;
+		int ret;
+
+		ret = detect_SW3_1_state();
+		if (ret == 1) {
+			ret = uclass_get_device_by_driver(UCLASS_MTD,
+							  DM_DRIVER_GET(hbmc_am654),
+							  &dev);
+			if (ret)
+				debug("Failed to probe hyperflash\n");
+		}
+	}
 }
-- 
2.17.1

[PATCH 9/9] configs: j721e_evm_defconfig: Add HBMC related configs

[Vaishnav Achath]

Enable HBMC and HyperFlash in R5SPL, A72 SPL and A72 U-Boot

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
---
 configs/j721e_evm_a72_defconfig |  5 +++++
 configs/j721e_evm_r5_defconfig  | 14 ++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 931abf5e59..08ca638b00 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -127,6 +127,9 @@ CONFIG_MMC_SDHCI_AM654=y
 CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_NOR_FLASH=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_CFI_FLASH=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
 CONFIG_FLASH_CFI_MTD=y
@@ -176,6 +179,7 @@ CONFIG_HAS_CQSPI_REF_CLK=y
 CONFIG_CQSPI_REF_CLK=133333333
 CONFIG_SYSRESET=y
 CONFIG_SPL_SYSRESET=y
+CONFIG_SPL_SYSCON=y
 CONFIG_SYSRESET_TI_SCI=y
 CONFIG_USB=y
 CONFIG_DM_USB_GADGET=y
@@ -193,3 +197,4 @@ CONFIG_UFS=y
 CONFIG_CADENCE_UFS=y
 CONFIG_TI_J721E_UFS=y
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 6553212de8..e23ae8849b 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -21,6 +21,9 @@ CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_OF_BOARD_SETUP=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
@@ -101,6 +104,17 @@ CONFIG_MMC_SDHCI=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_AM654=y
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_HBMC_AM654=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_STMICRO=y
-- 
2.17.1