From: Georgi Vlaev <g-vlaev@ti.com>
To: Vignesh Raghavendra <vigneshr@ti.com>,
Anand Gadiyar <gadiyar@ti.com>, Tom Rini <trini@konsulko.com>
Cc: <u-boot@lists.denx.de>, Georgi Vlaev <g-vlaev@ti.com>
Subject: [PATCH 1/5] arm: mach-k3: common: Use ddr_init in spl_enable_dcache
Date: Tue, 14 Jun 2022 17:45:30 +0300 [thread overview]
Message-ID: <20220614144534.317407-2-g-vlaev@ti.com> (raw)
In-Reply-To: <20220614144534.317407-1-g-vlaev@ti.com>
The spl_enable_dcache() function calls dram_init_banksize()
to get the total memory size. Normally the dram_init_banksize()
setups the memory banks, while the total size is reported
by ddr_init(). This worked so far for K3 since we set the
gd->ram_size in dram_init_banksize() as well.
Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
---
arch/arm/mach-k3/common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index b4b75f4e6c86..70f6444e7988 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -516,7 +516,7 @@ void spl_enable_dcache(void)
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
- dram_init_banksize();
+ dram_init();
/* reserve TLB table */
gd->arch.tlb_size = PGTABLE_SIZE;
--
2.30.2
next prev parent reply other threads:[~2022-06-14 15:23 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-14 14:45 [PATCH 0/5] board: ti: am62x: Add support for 1-bit inline DDRSS ECC Georgi Vlaev
2022-06-14 14:45 ` Georgi Vlaev [this message]
2022-06-16 14:38 ` [PATCH 1/5] arm: mach-k3: common: Use ddr_init in spl_enable_dcache Tom Rini
2022-07-07 1:55 ` Tom Rini
2022-06-14 14:45 ` [PATCH 2/5] arm: dts: k3-am625-*: Mark memory with u-boot,dm-spl Georgi Vlaev
2022-06-16 14:38 ` Tom Rini
2022-07-07 1:55 ` Tom Rini
2022-06-14 14:45 ` [PATCH 3/5] board: ti: am62x: Use fdt functions for ram and bank init Georgi Vlaev
2022-06-16 14:38 ` Tom Rini
2022-07-07 1:55 ` Tom Rini
2022-06-14 14:45 ` [PATCH 4/5] board: ti: am62x: Account for DDR size fixups if ECC is enabled Georgi Vlaev
2022-06-16 14:39 ` Tom Rini
2022-07-07 1:55 ` Tom Rini
2022-06-14 14:45 ` [PATCH 5/5] configs: am62x_evm_r5: Add CONFIG_NR_DRAM_BANKS as done in a53 defconfig Georgi Vlaev
2022-06-16 14:39 ` Tom Rini
2022-07-07 1:55 ` Tom Rini
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