[PATCH v2 0/2] imx6: fix LDB clock guard and clk0/clk1 swap

[PATCH v2 0/2] imx6: fix LDB clock guard and clk0/clk1 swap

[Md Shofiqul Islam]

This v2 series fixes two issues with LDB display clock initialisation on
NXP i.MX6Q boards.

Changes since v1:
- Squashed original patches 1 and 3 into a single patch. Patch 3 was a
  correction to patch 1 based on Brian Ruley's review feedback
  (CONFIG_SPL_BUILD is too broad; CONFIG_SPL_VIDEO is the correct guard).
  Folding them together makes the intent clearer.
- Fixed Fixes: SHA to meet the 12-character minimum.

Regarding checkpatch IS_ENABLED() warnings in patch 1/2:
The guards in drivers/clk/imx/clk-imx6q.c wrap a static function
definition and its call site. IS_ENABLED() cannot be used for function
definitions, so #if is the only option there. The board-file guards
follow the same established pattern in adjacent code.

Md Shofiqul Islam (2):
  clk: imx6q: guard LDB clock init with appropriate video config
  imx6: clock: fix clk0/clk1 swap in select_ldb_di_clock_source()

 arch/arm/mach-imx/mx6/clock.c     |  4 ++--
 board/aristainetos/aristainetos.c  |  2 ++
 board/ge/b1x5v2/b1x5v2.c          |  3 ++-
 drivers/clk/imx/clk-imx6q.c       |  6 +++---
 4 files changed, 9 insertions(+), 6 deletions(-)

[PATCH v2 1/2] clk: imx6q: guard LDB clock init with appropriate video config

[Md Shofiqul Islam]

Guard calls to select_ldb_di_clock_source() with the correct video
Kconfig symbol rather than the broad !CONFIG_SPL_BUILD guard.

SPL can support VIDEO, PANEL, and SPLASH_SCREEN so !CONFIG_SPL_BUILD
excluded SPL builds that legitimately need to configure the LDB clocks.

- board/ge/b1x5v2: guard with CONFIG_SPL_VIDEO — LDB init is needed
  in SPL only when display support is enabled
- board/aristainetos: guard with CONFIG_VIDEO_IPUV3 — this board does
  not use SPL so CONFIG_SPL_VIDEO is not the right guard here
- drivers/clk/imx/clk-imx6q: update both the definition of
  imx6q_init_ldb_clks() and its call site to use
  (!CONFIG_SPL_BUILD || CONFIG_SPL_VIDEO) — the function is needed
  in SPL when CONFIG_SPL_VIDEO is set, and on all non-SPL builds

Signed-off-by: Md Shofiqul Islam <shofiqtest@gmail.com>
---
 board/aristainetos/aristainetos.c | 2 ++
 board/ge/b1x5v2/b1x5v2.c          | 3 ++-
 drivers/clk/imx/clk-imx6q.c       | 4 ++++
 3 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index 4a2349e165b..c163b49209e 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -218,7 +218,9 @@ static void set_gpr_register(void)
 
 int board_early_init_f(void)
 {
+#if defined(CONFIG_VIDEO_IPUV3)
 	select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK);
+#endif
 	set_gpr_register();
 
 	/*
diff --git a/board/ge/b1x5v2/b1x5v2.c b/board/ge/b1x5v2/b1x5v2.c
index f7751fd6fb1..da7cb880eeb 100644
--- a/board/ge/b1x5v2/b1x5v2.c
+++ b/board/ge/b1x5v2/b1x5v2.c
@@ -320,8 +320,9 @@ int overwrite_console(void)
 
 int board_early_init_f(void)
 {
+#if defined(CONFIG_SPL_VIDEO)
 	select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK);
-
+#endif
 	return 0;
 }
 
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index a4649a1a9d9..5be303468a9 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -156,6 +156,7 @@ static struct clk_div_table video_div_table[] = {
 
 static unsigned int share_count_mipi_core_cfg;
 
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_VIDEO)
 static void of_assigned_ldb_sels(struct udevice *dev, int *ldb_di0_sel,
 				 int *ldb_di1_sel)
 {
@@ -270,6 +271,7 @@ static void imx6q_init_ldb_clks(struct udevice *dev)
 
 	select_ldb_di_clock_source(ldb_di_clk[0], ldb_di_clk[1]);
 }
+#endif /* !CONFIG_SPL_BUILD || CONFIG_SPL_VIDEO */
 
 static int imx6q_clk_probe(struct udevice *dev)
 {
@@ -488,7 +490,9 @@ static int imx6q_clk_probe(struct udevice *dev)
 		 * Need to set the clocks now and make them read-only due to a
 		 * hardware bug. Fixed on the i.MX6 QuadPlus
 		 */
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_VIDEO)
 		imx6q_init_ldb_clks(dev);
+#endif
 		clk_dm(IMX6QDL_CLK_LDB_DI0_SEL,
 		       imx_clk_mux_flags(dev, "ldb_di0_sel", base + 0x2c, 9, 3,
 					 ldb_di_sels, ARRAY_SIZE(ldb_di_sels),
-- 
2.51.1

[PATCH v2 2/2] imx6: clock: fix clk0/clk1 swap in select_ldb_di_clock_source()

[Md Shofiqul Islam]

clk0 was being written to LDB_DI1_CLK_SEL and clk1 to LDB_DI0_CLK_SEL.
The arguments were silently effective before because all callers passed
the same value for both, but the mapping was reversed.

Fixes: bd3e19dbd901 ("imx6: clock: allow different clock sources for ldb")
Signed-off-by: Md Shofiqul Islam <shofiqtest@gmail.com>
---
 arch/arm/mach-imx/mx6/clock.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index 828a101ba05..646d1fff6d7 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -1525,8 +1525,8 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk0, enum ldb_di_clock clk1)
 	reg = readl(&mxc_ccm->cs2cdr);
 	reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
 	      | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
-	reg |= ((clk0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
-	      | (clk1 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+	reg |= ((clk1 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
+	      | (clk0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
 	writel(reg, &mxc_ccm->cs2cdr);
 
 	/* Unbypass pll3_sw_clk */
-- 
2.51.1