[PATCH 0/8] *** Add Ethernet boot support for AM62Ax + phyCORE-AM62 SoMs ***

[PATCH 0/8] *** Add Ethernet boot support for AM62Ax + phyCORE-AM62 SoMs ***

[Wadim Egorov]

Add general ethernet boot support for AM62Ax SoC.
Some of the work is based on TI's downstream u-boot patches found in
[1], patches touching code in mach-k3 and *.yaml board config files.

Also, provide defconfigs and device tree changes for phyCORE-AM62x and
phyCORE-AM62Ax to support booting via ethernet.

[1] https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1307981/sk-am62a-lp-rgmii-boot-mode-problem

Andreas Dannenberg (1):
  arch: arm: mach-k3: r5: am62ax: Update SoC auto-gen data to enable
    CPSW boot

Daniel Schultz (1):
  arch: arm: dts: k3-am62a7-phyboard-lyra-rdk-u-boot: Disable Ethernet2

Nathan Morrisson (2):
  arch: arm: mach-k3: am62a7: Probe CPSW NUSS in board_init_f()
  board: phytec: phycore_am62ax: Share ethernet resources with boot r5
    core

Wadim Egorov (4):
  arm: dts: k3-am625-phyboard-lyra-rdk: Add boot phase tag to
    phy_gmii_sel
  configs: Add phycore_am62x_r5_ethboot_defconfig
  configs: phycore_am62x_a53_defconfig: Update for ethernet boot
  configs: Add phycore_am62ax_r5_ethboot_defconfig

 .../k3-am625-phyboard-lyra-rdk-u-boot.dtsi    | 14 ++---
 .../k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi   |  2 +-
 arch/arm/mach-k3/am62ax/am62a7_init.c         |  9 ++++
 arch/arm/mach-k3/r5/am62ax/clk-data.c         | 51 ++++++++++++++++++-
 arch/arm/mach-k3/r5/am62ax/dev-data.c         | 29 ++++++-----
 board/phytec/phycore_am62ax/MAINTAINERS       |  1 +
 board/phytec/phycore_am62ax/rm-cfg.yaml       | 10 ++--
 board/phytec/phycore_am62ax/tifs-rm-cfg.yaml  | 48 +++++++++--------
 board/phytec/phycore_am62x/MAINTAINERS        |  1 +
 configs/phycore_am62ax_r5_ethboot_defconfig   | 43 ++++++++++++++++
 configs/phycore_am62x_a53_defconfig           |  9 +++-
 configs/phycore_am62x_r5_ethboot_defconfig    | 43 ++++++++++++++++
 12 files changed, 206 insertions(+), 54 deletions(-)
 create mode 100644 configs/phycore_am62ax_r5_ethboot_defconfig
 create mode 100644 configs/phycore_am62x_r5_ethboot_defconfig

-- 
2.34.1

[PATCH 1/8] arm: dts: k3-am625-phyboard-lyra-rdk: Add boot phase tag to phy_gmii_sel

[Wadim Egorov]

Add bootph-all tag to phy_gmii_sel node. This is needed for booting via
Ethernet. While at it, drop main_pktdma reg redefinitions which are already
provided by the top-level SoC device tree file.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
 .../arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
index 2bc5acbec23..253ca297e12 100644
--- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
@@ -42,6 +42,10 @@
 	bootph-all;
 };
 
+&phy_gmii_sel {
+	bootph-all;
+};
+
 &fss {
 	bootph-all;
 };
@@ -86,16 +90,6 @@
 
 &main_pktdma {
 	bootph-all;
-	reg = <0x00 0x485c0000 0x00 0x100>,
-	      <0x00 0x4a800000 0x00 0x20000>,
-	      <0x00 0x4aa00000 0x00 0x20000>,
-	      <0x00 0x4b800000 0x00 0x200000>,
-	      <0x00 0x485e0000 0x00 0x10000>,
-	      <0x00 0x484a0000 0x00 0x2000>,
-	      <0x00 0x484c0000 0x00 0x2000>,
-	      <0x00 0x48430000 0x00 0x1000>;
-	reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
-		    "cfg", "tchan", "rchan", "rflow";
 };
 
 &main_rgmii1_pins_default {
-- 
2.34.1

[PATCH 2/8] configs: Add phycore_am62x_r5_ethboot_defconfig

[Wadim Egorov]

Provide a defconfig for booting the phycore-am62x via Ethernet.
We need a separate defconfig because the AM62x has not enough internal
SRAM to support all boot sources.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
 board/phytec/phycore_am62x/MAINTAINERS     |  1 +
 configs/phycore_am62x_r5_ethboot_defconfig | 43 ++++++++++++++++++++++
 2 files changed, 44 insertions(+)
 create mode 100644 configs/phycore_am62x_r5_ethboot_defconfig

diff --git a/board/phytec/phycore_am62x/MAINTAINERS b/board/phytec/phycore_am62x/MAINTAINERS
index 670c7473481..106b4b80121 100644
--- a/board/phytec/phycore_am62x/MAINTAINERS
+++ b/board/phytec/phycore_am62x/MAINTAINERS
@@ -9,6 +9,7 @@ F:	arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts
 F:	board/phytec/phycore_am62x/
 F:	configs/phycore_am62x_a53_defconfig
 F:	configs/phycore_am62x_r5_defconfig
+F:	configs/phycore_am62x_r5_ethboot_defconfig
 F:	configs/phycore_am62x_r5_usbdfu_defconfig
 F:	include/configs/phycore_am62x.h
 F:	doc/board/phytec/phycore-am62x.rst
diff --git a/configs/phycore_am62x_r5_ethboot_defconfig b/configs/phycore_am62x_r5_ethboot_defconfig
new file mode 100644
index 00000000000..3bc426821e9
--- /dev/null
+++ b/configs/phycore_am62x_r5_ethboot_defconfig
@@ -0,0 +1,43 @@
+#include <configs/phycore_am62x_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_AM625=y
+CONFIG_TARGET_PHYCORE_AM62X_R5=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-phycore-som-2gb"
+
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM62X U-Boot R5 SPL"
+CONFIG_SPL_SYSCON=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_SPL_MMC=n
+CONFIG_SPL_DM_SPI=n
+CONFIG_SPL_MMC=n
+CONFIG_SPL_SPI_FLASH_SUPPORT=n
+CONFIG_SPL_SPI=n
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=n
+CONFIG_SPL_SPI_LOAD=n
+CONFIG_SPL_YMODEM_SUPPORT=n
+CONFIG_DM_SPI_FLASH=n
+CONFIG_SPI_FLASH_SFDP_SUPPORT=n
+CONFIG_SPI_FLASH_SOFT_RESET=n
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=n
+CONFIG_SPI_FLASH_STMICRO=n
+CONFIG_SPI_FLASH_MT35XU=n
+CONFIG_SPI=n
+CONFIG_DM_SPI=n
+CONFIG_CADENCE_QSPI=n
+CONFIG_SPL_DM_SPI=n
-- 
2.34.1

[PATCH 3/8] configs: phycore_am62x_a53_defconfig: Update for ethernet boot

[Wadim Egorov]

Add support for ethernet boot in the A53 SPL. Increase the SPL Size
limit and update SPL_STACK_R_ADDR.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
 configs/phycore_am62x_a53_defconfig | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig
index 0494fc408b7..0111ad12e20 100644
--- a/configs/phycore_am62x_a53_defconfig
+++ b/configs/phycore_am62x_a53_defconfig
@@ -19,14 +19,15 @@ CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x83000000
 CONFIG_SPL_TEXT_BASE=0x80080000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x80c80000
 CONFIG_SPL_BSS_MAX_SIZE=0x80000
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_BOOTM_LEN=0x800000
-CONFIG_SPL_SIZE_LIMIT=0x40000
+CONFIG_SPL_SIZE_LIMIT=0x80000
 CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800
 CONFIG_ENV_OFFSET_REDUND=0x6c0000
 CONFIG_SPL_FS_FAT=y
@@ -51,11 +52,15 @@ CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
 CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_ETH=y
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
 CONFIG_SPL_I2C=y
 CONFIG_SPL_DM_MAILBOX=y
 CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM62X U-Boot A53 SPL"
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_DEVICE=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
-- 
2.34.1

[PATCH 4/8] arch: arm: dts: k3-am62a7-phyboard-lyra-rdk-u-boot: Disable Ethernet2

[Wadim Egorov]

From: Daniel Schultz <d.schultz@phytec.de>

Don't initialize Ethernet2 in SPL. We cannot boot from that source anyways
and it throws an error during boot.

This will remove following error message during network boot:

Error: ethernet@8000000port@2 No valid MAC address found.ethernet@8000000port@1
Waiting for PHY auto negotiation to complete....... done

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
 arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
index 41692c8f670..e2a086e6b90 100644
--- a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi
@@ -66,7 +66,7 @@
 };
 
 &cpsw_port2 {
-	bootph-all;
+	status = "disabled";
 };
 
 &dmsc {
-- 
2.34.1

[PATCH 5/8] arch: arm: mach-k3: am62a7: Probe CPSW NUSS in board_init_f()

[Wadim Egorov]

From: Nathan Morrisson <nmorrisson@phytec.com>

Probe CPSW NUSS in am62a7 board_init_f() to support ethernet boot.

Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
 arch/arm/mach-k3/am62ax/am62a7_init.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/mach-k3/am62ax/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c
index 698e6d5c587..52a21277227 100644
--- a/arch/arm/mach-k3/am62ax/am62a7_init.c
+++ b/arch/arm/mach-k3/am62ax/am62a7_init.c
@@ -194,6 +194,15 @@ void board_init_f(ulong dummy)
 
 	setup_qos();
 
+	if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) &&
+	    spl_boot_device() == BOOT_DEVICE_ETHERNET) {
+		struct udevice *cpswdev;
+
+		if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss),
+						&cpswdev))
+			printf("Failed to probe am65_cpsw_nuss driver\n");
+	}
+
 	debug("am62a_init: %s done\n", __func__);
 }
 
-- 
2.34.1

[PATCH 6/8] arch: arm: mach-k3: r5: am62ax: Update SoC auto-gen data to enable CPSW boot

[Wadim Egorov]

From: Andreas Dannenberg <dannenberg@ti.com>

This data was generated using the ksswtool-autogen project with the
followig commit:

eed7492 ("soc: am62ax: Add cpsw_3guss_main_0 id to the dev list")

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
 arch/arm/mach-k3/r5/am62ax/clk-data.c | 51 +++++++++++++++++++++++++--
 arch/arm/mach-k3/r5/am62ax/dev-data.c | 29 ++++++++-------
 2 files changed, 65 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-k3/r5/am62ax/clk-data.c b/arch/arm/mach-k3/r5/am62ax/clk-data.c
index d950b35e0be..7f1b6d5b4e0 100644
--- a/arch/arm/mach-k3/r5/am62ax/clk-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/clk-data.c
@@ -67,6 +67,17 @@ static const char * const clkout0_ctrl_out0_parents[] = {
 	"hsdiv4_16fft_main_2_hsdivout1_clk",
 };
 
+static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
+	"postdiv4_16ff_main_2_hsdivout5_clk",
+	"postdiv4_16ff_main_0_hsdivout6_clk",
+	"board_0_cp_gemac_cpts0_rft_clk_out",
+	NULL,
+	"board_0_mcu_ext_refclk0_out",
+	"board_0_ext_refclk1_out",
+	"sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
+	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
 static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
 	"postdiv4_16ff_main_0_hsdivout5_clk",
 	"hsdiv4_16fft_main_2_hsdivout2_clk",
@@ -137,7 +148,16 @@ static const struct clk_data clk_list[] = {
 	CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
 	CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
+	CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0),
+	CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0),
+	CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0),
+	CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0),
+	CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
+	CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_tck_out", 0, 0),
+	CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0),
+	CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0),
+	CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0),
 	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
 	CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0),
 	CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -187,6 +207,7 @@ static const struct clk_data clk_list[] = {
 	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
 	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
 	CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
+	CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
 	CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
 	CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
 	CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
@@ -203,6 +224,29 @@ static const struct clk_data clk_list[] = {
 };
 
 static const struct dev_clk soc_dev_clk_data[] = {
+	DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
+	DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
+	DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
+	DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
+	DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
+	DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
+	DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
+	DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"),
+	DEV_CLK(13, 20, "board_0_rgmii1_txc_out"),
+	DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"),
+	DEV_CLK(13, 23, "board_0_rgmii2_txc_out"),
+	DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"),
+	DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"),
 	DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
 	DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
 	DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -277,11 +321,14 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
 	DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
 	DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
+	DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"),
 	DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
 	DEV_CLK(157, 85, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
 	DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 	DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 	DEV_CLK(157, 130, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
+	DEV_CLK(157, 133, "cpsw_3guss_main_0_rgmii1_txc_o"),
+	DEV_CLK(157, 136, "cpsw_3guss_main_0_rgmii2_txc_o"),
 	DEV_CLK(157, 146, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
 	DEV_CLK(157, 159, "wkup_clkout_sel_io_out0"),
 	DEV_CLK(157, 160, "wkup_clkout_sel_out0"),
@@ -311,7 +358,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
 
 const struct ti_k3_clk_platdata am62ax_clk_platdata = {
 	.clk_list = clk_list,
-	.clk_list_cnt = 80,
+	.clk_list_cnt = 90,
 	.soc_dev_clk_data = soc_dev_clk_data,
-	.soc_dev_clk_data_cnt = 104,
+	.soc_dev_clk_data_cnt = 130,
 };
diff --git a/arch/arm/mach-k3/r5/am62ax/dev-data.c b/arch/arm/mach-k3/r5/am62ax/dev-data.c
index 6cced9efd08..fe025923f1b 100644
--- a/arch/arm/mach-k3/r5/am62ax/dev-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/dev-data.c
@@ -17,9 +17,10 @@ static struct ti_psc soc_psc_list[] = {
 
 static struct ti_pd soc_pd_list[] = {
 	[0] = PSC_PD(0, &soc_psc_list[1], NULL),
-	[1] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]),
-	[2] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[1]),
-	[3] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]),
+	[1] = PSC_PD(2, &soc_psc_list[1], &soc_pd_list[0]),
+	[2] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]),
+	[3] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[2]),
+	[4] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]),
 };
 
 static struct ti_lpsc soc_lpsc_list[] = {
@@ -32,11 +33,12 @@ static struct ti_lpsc soc_lpsc_list[] = {
 	[6] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
 	[7] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
 	[8] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
-	[9] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]),
-	[10] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[9]),
-	[11] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[8]),
-	[12] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[11]),
-	[13] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[12]),
+	[9] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]),
+	[10] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[8]),
+	[11] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[10]),
+	[12] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[8]),
+	[13] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[12]),
+	[14] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[13]),
 };
 
 static struct ti_dev soc_dev_list[] = {
@@ -55,11 +57,12 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(36, &soc_lpsc_list[8]),
 	PSC_DEV(102, &soc_lpsc_list[8]),
 	PSC_DEV(146, &soc_lpsc_list[8]),
-	PSC_DEV(166, &soc_lpsc_list[9]),
-	PSC_DEV(135, &soc_lpsc_list[10]),
-	PSC_DEV(170, &soc_lpsc_list[11]),
-	PSC_DEV(177, &soc_lpsc_list[12]),
-	PSC_DEV(55, &soc_lpsc_list[13]),
+	PSC_DEV(13, &soc_lpsc_list[9]),
+	PSC_DEV(166, &soc_lpsc_list[10]),
+	PSC_DEV(135, &soc_lpsc_list[11]),
+	PSC_DEV(170, &soc_lpsc_list[12]),
+	PSC_DEV(177, &soc_lpsc_list[13]),
+	PSC_DEV(55, &soc_lpsc_list[14]),
 };
 
 const struct ti_k3_pd_platdata am62ax_pd_platdata = {
-- 
2.34.1

[PATCH 7/8] board: phytec: phycore_am62ax: Share ethernet resources with boot r5 core

[Wadim Egorov]

From: Nathan Morrisson <nmorrisson@phytec.com>

During the U-Boot SPL R5 boot stage the code is running on the MAIN R5
core, which means a host ID of 36 is used for DM/TIFS communication,
see [1]. In order to enable Ethernet boot update the DMA resources used
to be shared with the MAIN R5 core instead of the MCU R5 core.

[1] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62ax/hosts.html

Based on patch 19 from https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1307981/sk-am62a-lp-rgmii-boot-mode-problem

Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com>
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
 board/phytec/phycore_am62ax/rm-cfg.yaml      | 10 ++--
 board/phytec/phycore_am62ax/tifs-rm-cfg.yaml | 48 +++++++++++---------
 2 files changed, 32 insertions(+), 26 deletions(-)

diff --git a/board/phytec/phycore_am62ax/rm-cfg.yaml b/board/phytec/phycore_am62ax/rm-cfg.yaml
index cbd087de797..0f34b8c1bc0 100644
--- a/board/phytec/phycore_am62ax/rm-cfg.yaml
+++ b/board/phytec/phycore_am62ax/rm-cfg.yaml
@@ -713,7 +713,7 @@ rm-cfg:
             start_resource: 19
             num_resource: 64
             type: 1937
-            host_id: 30
+            host_id: 36
             reserved: 0
         -
             start_resource: 83
@@ -767,7 +767,7 @@ rm-cfg:
             start_resource: 118
             num_resource: 16
             type: 1943
-            host_id: 30
+            host_id: 36
             reserved: 0
         -
             start_resource: 134
@@ -833,7 +833,7 @@ rm-cfg:
             start_resource: 19
             num_resource: 8
             type: 1956
-            host_id: 30
+            host_id: 36
             reserved: 0
         -
             start_resource: 27
@@ -917,7 +917,7 @@ rm-cfg:
             start_resource: 19
             num_resource: 1
             type: 1963
-            host_id: 30
+            host_id: 36
             reserved: 0
         -
             start_resource: 19
@@ -929,7 +929,7 @@ rm-cfg:
             start_resource: 19
             num_resource: 16
             type: 1964
-            host_id: 30
+            host_id: 36
             reserved: 0
         -
             start_resource: 20
diff --git a/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml b/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml
index 151cd599b1b..23dcd784615 100644
--- a/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml
+++ b/board/phytec/phycore_am62ax/tifs-rm-cfg.yaml
@@ -24,26 +24,26 @@ tifs-rm-cfg:
                     allowed_priority: 0xAAAA
                     allowed_sched_priority: 0xAA
                 -  # 2
-                    host_id: 30
+                    host_id: 20
                     allowed_atype: 0x2A
                     allowed_qos: 0xAAAA
                     allowed_orderid: 0xAAAAAAAA
                     allowed_priority: 0xAAAA
                     allowed_sched_priority: 0xAA
                 -  # 3
-                    host_id: 36
+                    host_id: 30
                     allowed_atype: 0x2A
                     allowed_qos: 0xAAAA
                     allowed_orderid: 0xAAAAAAAA
                     allowed_priority: 0xAAAA
                     allowed_sched_priority: 0xAA
                 -  # 4
-                    host_id: 0
-                    allowed_atype: 0
-                    allowed_qos: 0
-                    allowed_orderid: 0
-                    allowed_priority: 0
-                    allowed_sched_priority: 0
+                    host_id: 36
+                    allowed_atype: 0x2A
+                    allowed_qos: 0xAAAA
+                    allowed_orderid: 0xAAAAAAAA
+                    allowed_priority: 0xAAAA
+                    allowed_sched_priority: 0xAA
                 -  # 5
                     host_id: 0
                     allowed_atype: 0
@@ -244,7 +244,7 @@ tifs-rm-cfg:
             subhdr:
                 magic: 0x7B25
                 size: 8
-            resasg_entries_size: 872
+            resasg_entries_size: 880
             reserved: 0
     resasg_entries:
         -
@@ -257,7 +257,7 @@ tifs-rm-cfg:
             start_resource: 18
             num_resource: 6
             type: 1677
-            host_id: 35
+            host_id: 20
             reserved: 0
         -
             start_resource: 18
@@ -287,7 +287,7 @@ tifs-rm-cfg:
             start_resource: 72
             num_resource: 6
             type: 1678
-            host_id: 35
+            host_id: 20
             reserved: 0
         -
             start_resource: 72
@@ -317,7 +317,7 @@ tifs-rm-cfg:
             start_resource: 44
             num_resource: 6
             type: 1679
-            host_id: 35
+            host_id: 20
             reserved: 0
         -
             start_resource: 44
@@ -347,7 +347,7 @@ tifs-rm-cfg:
             start_resource: 18
             num_resource: 6
             type: 1696
-            host_id: 35
+            host_id: 20
             reserved: 0
         -
             start_resource: 18
@@ -377,7 +377,7 @@ tifs-rm-cfg:
             start_resource: 18
             num_resource: 6
             type: 1697
-            host_id: 35
+            host_id: 20
             reserved: 0
         -
             start_resource: 18
@@ -407,7 +407,7 @@ tifs-rm-cfg:
             start_resource: 12
             num_resource: 6
             type: 1698
-            host_id: 35
+            host_id: 20
             reserved: 0
         -
             start_resource: 12
@@ -429,10 +429,16 @@ tifs-rm-cfg:
             reserved: 0
         -
             start_resource: 6
-            num_resource: 34
+            num_resource: 26
             type: 1802
             host_id: 12
             reserved: 0
+        -
+            start_resource: 32
+            num_resource: 8
+            type: 1802
+            host_id: 20
+            reserved: 0
         -
             start_resource: 44
             num_resource: 36
@@ -587,7 +593,7 @@ tifs-rm-cfg:
             start_resource: 19
             num_resource: 64
             type: 1937
-            host_id: 30
+            host_id: 36
             reserved: 0
         -
             start_resource: 83
@@ -641,7 +647,7 @@ tifs-rm-cfg:
             start_resource: 118
             num_resource: 16
             type: 1943
-            host_id: 30
+            host_id: 36
             reserved: 0
         -
             start_resource: 134
@@ -707,7 +713,7 @@ tifs-rm-cfg:
             start_resource: 19
             num_resource: 8
             type: 1956
-            host_id: 30
+            host_id: 36
             reserved: 0
         -
             start_resource: 27
@@ -791,7 +797,7 @@ tifs-rm-cfg:
             start_resource: 19
             num_resource: 1
             type: 1963
-            host_id: 30
+            host_id: 36
             reserved: 0
         -
             start_resource: 19
@@ -803,7 +809,7 @@ tifs-rm-cfg:
             start_resource: 19
             num_resource: 16
             type: 1964
-            host_id: 30
+            host_id: 36
             reserved: 0
         -
             start_resource: 20
-- 
2.34.1

[PATCH 8/8] configs: Add phycore_am62ax_r5_ethboot_defconfig

[Wadim Egorov]

Provide a defconfig for booting the phycore-am62ax via Ethernet.

Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
---
 board/phytec/phycore_am62ax/MAINTAINERS     |  1 +
 configs/phycore_am62ax_r5_ethboot_defconfig | 43 +++++++++++++++++++++
 2 files changed, 44 insertions(+)
 create mode 100644 configs/phycore_am62ax_r5_ethboot_defconfig

diff --git a/board/phytec/phycore_am62ax/MAINTAINERS b/board/phytec/phycore_am62ax/MAINTAINERS
index 3e4e2feff4e..9169651c459 100644
--- a/board/phytec/phycore_am62ax/MAINTAINERS
+++ b/board/phytec/phycore_am62ax/MAINTAINERS
@@ -10,5 +10,6 @@ F:	arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts
 F:	board/phytec/phycore_am62ax/
 F:	configs/phycore_am62ax_a53_defconfig
 F:	configs/phycore_am62ax_r5_defconfig
+F:	configs/phycore_am62ax_r5_ethboot_defconfig
 F:	include/configs/phycore_am62ax.h
 F:	doc/board/phytec/phycore-am62ax.rst
diff --git a/configs/phycore_am62ax_r5_ethboot_defconfig b/configs/phycore_am62ax_r5_ethboot_defconfig
new file mode 100644
index 00000000000..81a7f5b0784
--- /dev/null
+++ b/configs/phycore_am62ax_r5_ethboot_defconfig
@@ -0,0 +1,43 @@
+#include <configs/phycore_am62ax_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_AM62A7=y
+CONFIG_TARGET_PHYCORE_AM62AX_R5=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am62a7-r5-phycore-som-2gb"
+
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
+CONFIG_SPL_BSS_MAX_SIZE=0x3100
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM62AX U-Boot R5 SPL"
+CONFIG_SPL_SYSCON=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_SPL_MMC=n
+CONFIG_SPL_DM_SPI=n
+CONFIG_SPL_MMC=n
+CONFIG_SPL_SPI_FLASH_SUPPORT=n
+CONFIG_SPL_SPI=n
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=n
+CONFIG_SPL_SPI_LOAD=n
+CONFIG_SPL_YMODEM_SUPPORT=n
+CONFIG_DM_SPI_FLASH=n
+CONFIG_SPI_FLASH_SFDP_SUPPORT=n
+CONFIG_SPI_FLASH_SOFT_RESET=n
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=n
+CONFIG_SPI_FLASH_STMICRO=n
+CONFIG_SPI_FLASH_MT35XU=n
+CONFIG_SPI=n
+CONFIG_DM_SPI=n
+CONFIG_CADENCE_QSPI=n
-- 
2.34.1

Re: [PATCH 1/8] arm: dts: k3-am625-phyboard-lyra-rdk: Add boot phase tag to phy_gmii_sel

[Daniel Schultz]

On 3/25/25 04:58, Wadim Egorov wrote:
> Add bootph-all tag to phy_gmii_sel node. This is needed for booting via
> Ethernet. While at it, drop main_pktdma reg redefinitions which are already
> provided by the top-level SoC device tree file.
>
> Signed-off-by: Wadim Egorov <w.egorov@phytec.de>

For entire series,
Tested-by: Daniel Schultz <d.schultz@phytec.de>

> ---
>   .../arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi | 14 ++++----------
>   1 file changed, 4 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
> index 2bc5acbec23..253ca297e12 100644
> --- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
> +++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi
> @@ -42,6 +42,10 @@
>   	bootph-all;
>   };
>   
> +&phy_gmii_sel {
> +	bootph-all;
> +};
> +
>   &fss {
>   	bootph-all;
>   };
> @@ -86,16 +90,6 @@
>   
>   &main_pktdma {
>   	bootph-all;
> -	reg = <0x00 0x485c0000 0x00 0x100>,
> -	      <0x00 0x4a800000 0x00 0x20000>,
> -	      <0x00 0x4aa00000 0x00 0x20000>,
> -	      <0x00 0x4b800000 0x00 0x200000>,
> -	      <0x00 0x485e0000 0x00 0x10000>,
> -	      <0x00 0x484a0000 0x00 0x2000>,
> -	      <0x00 0x484c0000 0x00 0x2000>,
> -	      <0x00 0x48430000 0x00 0x1000>;
> -	reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
> -		    "cfg", "tchan", "rchan", "rflow";
>   };
>   
>   &main_rgmii1_pins_default {

Re: [PATCH 0/8] *** Add Ethernet boot support for AM62Ax + phyCORE-AM62 SoMs ***

[Tom Rini]

On Tue, 25 Mar 2025 04:58:16 +0100, Wadim Egorov wrote:

> Add general ethernet boot support for AM62Ax SoC.
> Some of the work is based on TI's downstream u-boot patches found in
> [1], patches touching code in mach-k3 and *.yaml board config files.
> 
> Also, provide defconfigs and device tree changes for phyCORE-AM62x and
> phyCORE-AM62Ax to support booting via ethernet.
> 
> [...]

Applied to u-boot/master, thanks!

[1/8] arm: dts: k3-am625-phyboard-lyra-rdk: Add boot phase tag to phy_gmii_sel
      commit: a936352f9e00206016badaaa217f034dde7b00a2
[2/8] configs: Add phycore_am62x_r5_ethboot_defconfig
      commit: 1acffb571149879094012bb69f54da2c958d552a
[3/8] configs: phycore_am62x_a53_defconfig: Update for ethernet boot
      commit: 93d22aca3d3266f759c0f293e96e210ca3fec663
[4/8] arch: arm: dts: k3-am62a7-phyboard-lyra-rdk-u-boot: Disable Ethernet2
      commit: 77183dfbbcfa466c9a7a646f9f9468f6276e94e3
[5/8] arch: arm: mach-k3: am62a7: Probe CPSW NUSS in board_init_f()
      commit: 2dec0fc59c55aa78ff737d3238cac6cc968348c5
[6/8] arch: arm: mach-k3: r5: am62ax: Update SoC auto-gen data to enable CPSW boot
      commit: a0f73e847d17302751ad358bf387700b08fa5e98
[7/8] board: phytec: phycore_am62ax: Share ethernet resources with boot r5 core
      commit: 5327b62c12cf0a1393481fb2f402806bad6dc280
[8/8] configs: Add phycore_am62ax_r5_ethboot_defconfig
      commit: e41c21acced75002f54240c277e46ee585af2cf9
-- 
Tom