From: "Michael Walle" <mwalle@kernel.org>
To: "Chintan Vankar" <c-vankar@ti.com>,
"Richard Genoud" <richard.genoud@bootlin.com>,
"Sam Protsenko" <semen.protsenko@linaro.org>,
"Santhosh Kumar K" <s-k6@ti.com>,
"Jonathan Humphreys" <j-humphreys@ti.com>,
"Mattijs Korpershoek" <mkorpershoek@kernel.org>,
"Ilias Apalodimas" <ilias.apalodimas@linaro.org>,
"Bhavya Kapoor" <b-kapoor@ti.com>,
"Parth Pancholi" <parth.pancholi@toradex.com>,
"Andreas Dannenberg" <dannenberg@ti.com>,
"Moteen Shah" <m-shah@ti.com>, "Beleswar Padhi" <b-padhi@ti.com>,
"Anshul Dalal" <anshuld@ti.com>,
"Sughosh Ganu" <sughosh.ganu@linaro.org>,
"Neha Malcom Francis" <n-francis@ti.com>,
"Prasanth Babu Mantena" <p-mantena@ti.com>,
"Wadim Egorov" <w.egorov@phytec.de>,
"Simon Glass" <sjg@chromium.org>,
"Alexander Sverdlin" <alexander.sverdlin@siemens.com>,
"Siddharth Vadapalli" <s-vadapalli@ti.com>,
"Kishon Vijay Abraham I" <kishon@ti.com>,
"Ramon Fried" <rfried.dev@gmail.com>,
"Joe Hershberger" <joe.hershberger@ni.com>,
"Jayesh Choudhary" <j-choudhary@ti.com>,
"Vaishnav Achath" <vaishnav.a@ti.com>,
"Bryan Brattlof" <bb@ti.com>,
"Vignesh Raghavendra" <vigneshr@ti.com>,
"Tom Rini" <trini@konsulko.com>
Cc: <u-boot@lists.denx.de>
Subject: Re: [PATCH v4 14/21] arm: mach-k3: j722s: Update SoC autogenerated data to enable Ethernet boot
Date: Fri, 21 Nov 2025 17:08:39 +0100 [thread overview]
Message-ID: <DEEI48KL4PLG.2CACJ40DOAAMS@kernel.org> (raw)
In-Reply-To: <20250731075956.605474-15-c-vankar@ti.com>
[-- Attachment #1: Type: text/plain, Size: 10691 bytes --]
Hi,
On Thu Jul 31, 2025 at 9:59 AM CEST, Chintan Vankar wrote:
> Update dev-data and clk-data to include CPSW device which is required to
> enable Ethernet boot.
>
This breaks eMMC boot on our board:
U-Boot SPL 2026.01-rc2-00054-g32334645579c (Nov 21 2025 - 15:49:13 +0100)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.3--v11.01.03 (Fancy Rat)')
SPL initial stack usage: 17048 bytes
ti_power_domain_of_xlate: invalid dev-id: 57
ti_power_domain_of_xlate: invalid dev-id: 57
Trying to boot from eMMC (boot0)
ti_power_domain_of_xlate: invalid dev-id: 57
ti_power_domain_of_xlate: invalid dev-id: 57
spl: could not initialize mmc. error: -2
Error: -2
SPL: Unsupported Boot Device!
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###
Not sure how this file was autogenerated but it removes ID 57.. see
more below.
Reverting this patch will make (at least) the r5 SPL work again.
There seems to be more issues with the u-boot proper, but I haven't
investigated that yet.
> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
> ---
>
> Link to v3:
> https://lore.kernel.org/u-boot/20250225114903.2080616-13-c-vankar@ti.com/
>
> Changes from v3 to v4:
> - No changes.
>
> arch/arm/mach-k3/r5/j722s/clk-data.c | 50 ++++++++++++++++++++++------
> arch/arm/mach-k3/r5/j722s/dev-data.c | 34 +++++++++----------
> 2 files changed, 56 insertions(+), 28 deletions(-)
>
> diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c b/arch/arm/mach-k3/r5/j722s/clk-data.c
> index b4f27af333d..238d57d0aa0 100644
> --- a/arch/arm/mach-k3/r5/j722s/clk-data.c
> +++ b/arch/arm/mach-k3/r5/j722s/clk-data.c
> @@ -5,7 +5,7 @@
> * This file is auto generated. Please do not hand edit and report any issues
> * to Bryan Brattlof <bb@ti.com>.
> *
> - * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> #include <linux/clk-provider.h>
> @@ -57,9 +57,15 @@ static const char * const clkout0_ctrl_out0_parents[] = {
> "hsdiv4_16fft_main_2_hsdivout1_clk",
> };
>
> -static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
> - "postdiv4_16ff_main_0_hsdivout5_clk",
> - "hsdiv4_16fft_main_2_hsdivout2_clk",
> +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
> + "postdiv4_16ff_main_2_hsdivout5_clk",
> + "postdiv4_16ff_main_0_hsdivout6_clk",
> + "board_0_cp_gemac_cpts0_rft_clk_out",
> + NULL,
> + "board_0_mcu_ext_refclk0_out",
> + "board_0_ext_refclk1_out",
> + NULL,
> + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
> };
>
> static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
> @@ -94,8 +100,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = {
> "board_0_cp_gemac_cpts0_rft_clk_out",
> "hsdiv4_16fft_main_1_hsdivout3_clk",
> "postdiv4_16ff_main_2_hsdivout6_clk",
> - NULL,
> - NULL,
> + "cpsw_3guss_am67_main_0_cpts_genf0",
> + "cpsw_3guss_am67_main_0_cpts_genf1",
> NULL,
> NULL,
> NULL,
> @@ -143,7 +149,12 @@ static const struct clk_data clk_list[] = {
> CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
> CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
> CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
> + CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
> + CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
> CLK_FIXED_RATE("board_0_tck_out", 0, 0),
> + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0),
> + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0),
> + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0),
> CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
> CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
> CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
> @@ -194,7 +205,7 @@ static const struct clk_data clk_list[] = {
> CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
> CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
> CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
> - CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
> + CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
> CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
> CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
> CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
> @@ -209,6 +220,24 @@ static const struct clk_data clk_list[] = {
> };
>
> static const struct dev_clk soc_dev_clk_data[] = {
> + DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
> + DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
> + DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
> + DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
> + DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
> + DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
> + DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> + DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
> + DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
> + DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
> + DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
> + DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
> + DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"),
> + DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"),
> + DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
> + DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"),
> + DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"),
> DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
> DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
> DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
> @@ -233,10 +262,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
> DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
> DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
> DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
> - DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> - DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
> - DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
> - DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
> + DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"),
> + DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"),
> DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
> DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
> DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
> @@ -279,6 +306,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
> DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> DEV_CLK(157, 74, "mshsi2c_main_0_porscl"),
> DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
> + DEV_CLK(157, 140, "cpsw_3guss_am67_main_0_mdio_mdclk_o"),
> DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
> DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
> DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
> diff --git a/arch/arm/mach-k3/r5/j722s/dev-data.c b/arch/arm/mach-k3/r5/j722s/dev-data.c
> index 59176c98999..d6832266884 100644
> --- a/arch/arm/mach-k3/r5/j722s/dev-data.c
> +++ b/arch/arm/mach-k3/r5/j722s/dev-data.c
> @@ -5,7 +5,7 @@
> * This file is auto generated. Please do not hand edit and report any issues
> * to Bryan Brattlof <bb@ti.com>.
> *
> - * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> #include "k3-dev.h"
> @@ -23,16 +23,16 @@ static struct ti_pd soc_pd_list[] = {
>
> static struct ti_lpsc soc_lpsc_list[] = {
> [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
> - [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
> - [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
> - [3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
> - [4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
> - [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
> - [6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
> - [7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
> - [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[7]),
> + [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
> + [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
> + [3] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
> + [4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
> + [5] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
> + [6] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
> + [7] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
> + [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[6]),
> [9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]),
> - [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]),
> + [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]),
> [11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]),
> [12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
> };
> @@ -43,13 +43,13 @@ static struct ti_dev soc_dev_list[] = {
> PSC_DEV(61, &soc_lpsc_list[0]),
> PSC_DEV(178, &soc_lpsc_list[1]),
> PSC_DEV(179, &soc_lpsc_list[2]),
> - PSC_DEV(57, &soc_lpsc_list[3]),
This seems to be relevant.
-michael
> - PSC_DEV(58, &soc_lpsc_list[4]),
> - PSC_DEV(161, &soc_lpsc_list[5]),
> - PSC_DEV(75, &soc_lpsc_list[6]),
> - PSC_DEV(36, &soc_lpsc_list[7]),
> - PSC_DEV(102, &soc_lpsc_list[7]),
> - PSC_DEV(146, &soc_lpsc_list[7]),
> + PSC_DEV(58, &soc_lpsc_list[3]),
> + PSC_DEV(161, &soc_lpsc_list[4]),
> + PSC_DEV(75, &soc_lpsc_list[5]),
> + PSC_DEV(36, &soc_lpsc_list[6]),
> + PSC_DEV(102, &soc_lpsc_list[6]),
> + PSC_DEV(146, &soc_lpsc_list[6]),
> + PSC_DEV(13, &soc_lpsc_list[7]),
> PSC_DEV(166, &soc_lpsc_list[8]),
> PSC_DEV(135, &soc_lpsc_list[9]),
> PSC_DEV(170, &soc_lpsc_list[10]),
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next prev parent reply other threads:[~2025-11-21 16:08 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-31 7:59 [PATCH v4 00/21] Add support for Ethernet boot Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 01/21] net: ti: am65-cpsw-nuss: Define bind method for CPSW driver Chintan Vankar
2025-11-21 12:55 ` Wadim Egorov
2025-11-21 13:24 ` Siddharth Vadapalli
2025-07-31 7:59 ` [PATCH v4 02/21] arch: mach-k3: common: Remove explicit probing of " Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 03/21] Revert "mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPL" Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 04/21] Revert "arm: mach-k3: am62x: am625_init: Probe AM65 CPSW NUSS" Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 05/21] arm: mach-k3: j721s2: Update SoC auto-gen data to enable Ethernet boot Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 06/21] arm: mach-k3: j721s2_spl: Alias Ethernet boot to CPGMAC Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 07/21] net: ti: Kconfig: Enable SPL_SYSCON config for CPSW Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 08/21] configs: am68_sk_r5_ethboot: Add configs for enabling Ethernet boot in R5SPL Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 09/21] configs: am68_sk_a72_ethboot: Enable configs required for Ethernet boot Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 10/21] arm: mach-k3: am62p: Update SoC auto-gen data to enable " Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 11/21] board: ti: am62px: evm: Enable cache for AM62p Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 12/21] configs: am62px_evm_r5_ethboot: Add configs to enable Ethernet boot in R5SPL Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 13/21] configs: am62px_evm_a53_ethboot: Enable configs required for Ethboot Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 14/21] arm: mach-k3: j722s: Update SoC autogenerated data to enable Ethernet boot Chintan Vankar
2025-11-21 16:08 ` Michael Walle [this message]
2025-07-31 7:59 ` [PATCH v4 15/21] board: ti: j722s: evm: Enable cache for J722s Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 16/21] configs: j722s_evm_r5_ethboot: Add configs to enable Ethernet boot in R5SPL Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 17/21] configs: j722s_evm_a53_ethboot: Enable configs required for Ethernet boot Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 18/21] arm: mach-k3: j784s4: Update SoC auto-gen data to enable " Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 19/21] arm: mach-k3: j784s4_spl: Alias Ethernet boot to CPGMAC Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 20/21] configs: am69_sk_r5_ethboot: Add configs to enable Ethernet boot in R5SPL Chintan Vankar
2025-07-31 7:59 ` [PATCH v4 21/21] configs: am69_sk_a72_ethboot: Add configs to enable Ethernet boot Chintan Vankar
2025-08-20 18:41 ` [PATCH v4 00/21] Add support for " Tom Rini
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