[PATCH v4 00/21] Add support for Ethernet boot

[PATCH v4 00/21] Add support for Ethernet boot

[Chintan Vankar]

Hello All,

This series adds bind method for CPSW to avoid explicit probing, removes
explicit probing of CPSW, adds support for Ethernet boot on SK-AM68,
SK-AM62P-LP, J722S, SK-AM69.

This series is based on commit 'a8f20bb6650df56d' of origin/master
branch of U-Boot.

Link to v3: 
https://lore.kernel.org/u-boot/20250225114903.2080616-1-c-vankar@ti.com/

Changes from v3 to v4: 
- Updated bind method to avoid initializing fields in cpsw data structure.
- Revert commits to avoid explicit probing of CPSW driver as per Roger's
  suggestion.
- Updated commit messages of adding SoC auto-gen data for J721s2.
- Collected Reviewed-by tag from Alexander Sverdlin on [PATCH v3 05/15]
  and [PATCH v3 13/15].
- Added support of Ethernet boot for SK-AM69.

Andreas Dannenberg (3):
  arm: mach-k3: am62p: Update SoC auto-gen data to enable Ethernet boot
  board: ti: am62px: evm: Enable cache for AM62p
  configs: am62px_evm_r5_ethboot: Add configs to enable Ethernet boot in
    R5SPL

Chintan Vankar (18):
  net: ti: am65-cpsw-nuss: Define bind method for CPSW driver
  arch: mach-k3: common: Remove explicit probing of CPSW driver
  Revert "mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPL"
  Revert "arm: mach-k3: am62x: am625_init: Probe AM65 CPSW NUSS"
  arm: mach-k3: j721s2: Update SoC auto-gen data to enable Ethernet boot
  arm: mach-k3: j721s2_spl: Alias Ethernet boot to CPGMAC
  net: ti: Kconfig: Enable SPL_SYSCON config for CPSW
  configs: am68_sk_r5_ethboot: Add configs for enabling Ethernet boot in
    R5SPL
  configs: am68_sk_a72_ethboot: Enable configs required for Ethernet
    boot
  configs: am62px_evm_a53_ethboot: Enable configs required for Ethboot
  arm: mach-k3: j722s: Update SoC autogenerated data to enable Ethernet
    boot
  board: ti: j722s: evm: Enable cache for J722s
  configs: j722s_evm_r5_ethboot: Add configs to enable Ethernet boot in
    R5SPL
  configs: j722s_evm_a53_ethboot: Enable configs required for Ethernet
    boot
  arm: mach-k3: j784s4: Update SoC auto-gen data to enable Ethernet boot
  arm: mach-k3: j784s4_spl: Alias Ethernet boot to CPGMAC
  configs: am69_sk_r5_ethboot: Add configs to enable Ethernet boot in
    R5SPL
  configs: am69_sk_a72_ethboot: Add configs to enable Ethernet boot

 arch/arm/mach-k3/am62x/am625_init.c        |  9 ----
 arch/arm/mach-k3/am64x/am642_init.c        |  7 ---
 arch/arm/mach-k3/common.c                  | 11 ----
 arch/arm/mach-k3/include/mach/j721s2_spl.h |  1 +
 arch/arm/mach-k3/include/mach/j784s4_spl.h |  2 +
 arch/arm/mach-k3/r5/am62px/clk-data.c      | 44 ++++++++++++++--
 arch/arm/mach-k3/r5/am62px/dev-data.c      | 24 +++++----
 arch/arm/mach-k3/r5/j721s2/clk-data.c      | 58 ++++++++++++++++++++--
 arch/arm/mach-k3/r5/j721s2/dev-data.c      |  3 +-
 arch/arm/mach-k3/r5/j722s/clk-data.c       | 50 +++++++++++++++----
 arch/arm/mach-k3/r5/j722s/dev-data.c       | 34 ++++++-------
 arch/arm/mach-k3/r5/j784s4/clk-data.c      | 54 ++++++++++++++++++--
 arch/arm/mach-k3/r5/j784s4/dev-data.c      |  1 +
 board/ti/am62px/evm.c                      |  8 +++
 board/ti/j722s/evm.c                       |  8 +++
 configs/am62px_evm_a53_ethboot_defconfig   | 13 +++++
 configs/am62px_evm_r5_ethboot_defconfig    | 29 +++++++++++
 configs/am68_sk_a72_ethboot_defconfig      | 14 ++++++
 configs/am68_sk_r5_ethboot_defconfig       | 23 +++++++++
 configs/am69_sk_a72_ethboot_defconfig      | 11 ++++
 configs/am69_sk_r5_ethboot_defconfig       | 15 ++++++
 configs/j722s_evm_a53_ethboot_defconfig    | 13 +++++
 configs/j722s_evm_r5_ethboot_defconfig     | 30 +++++++++++
 drivers/net/ti/Kconfig                     |  1 +
 drivers/net/ti/am65-cpsw-nuss.c            | 40 ++++++++++++---
 25 files changed, 418 insertions(+), 85 deletions(-)
 create mode 100644 configs/am62px_evm_a53_ethboot_defconfig
 create mode 100644 configs/am62px_evm_r5_ethboot_defconfig
 create mode 100644 configs/am68_sk_a72_ethboot_defconfig
 create mode 100644 configs/am68_sk_r5_ethboot_defconfig
 create mode 100644 configs/am69_sk_a72_ethboot_defconfig
 create mode 100644 configs/am69_sk_r5_ethboot_defconfig
 create mode 100644 configs/j722s_evm_a53_ethboot_defconfig
 create mode 100644 configs/j722s_evm_r5_ethboot_defconfig

-- 
2.34.1

[PATCH v4 01/21] net: ti: am65-cpsw-nuss: Define bind method for CPSW driver

[Chintan Vankar]

CPSW driver is defined as UCLASS_MISC driver which needs to be probed
explicitly. Define bind method for CPSW driver to scan and bind
ethernet-ports with UCLASS_ETH driver which will eventually probe CPSW
driver and avoid probing CPSW driver explicitly.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

Link to v3:
https://lore.kernel.org/u-boot/20250225114903.2080616-2-c-vankar@ti.com/

Changes from v3 to v4:
- Moved initialization part from "am65_cpsw_probe_nuss()" to
  "am65_cpsw_nuss_bind()" method.

 drivers/net/ti/am65-cpsw-nuss.c | 40 +++++++++++++++++++++++++++------
 1 file changed, 33 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index 9b69f36d04d..754076d807c 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -705,7 +705,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev)
 	struct am65_cpsw_common *cpsw_common = dev_get_priv(dev);
 	ofnode ports_np, node;
 	int ret, i;
-	struct udevice *port_dev;
 
 	cpsw_common->dev = dev;
 	cpsw_common->ss_base = dev_read_addr(dev);
@@ -732,6 +731,7 @@ static int am65_cpsw_probe_nuss(struct udevice *dev)
 	ports_np = dev_read_subnode(dev, "ethernet-ports");
 	if (!ofnode_valid(ports_np)) {
 		ret = -ENOENT;
+		dev_err(dev, "Invalid device tree node %d\n", ret);
 		goto out;
 	}
 
@@ -763,12 +763,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev)
 			continue;
 
 		cpsw_common->ports[port_id].disabled = disabled;
-		if (disabled)
-			continue;
-
-		ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", ofnode_get_name(node), node, &port_dev);
-		if (ret)
-			dev_err(dev, "Failed to bind to %s node\n", ofnode_get_name(node));
 	}
 
 	for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) {
@@ -798,6 +792,37 @@ out:
 	return ret;
 }
 
+static int am65_cpsw_nuss_bind(struct udevice *dev)
+{
+	struct uclass_driver *drv;
+	struct udevice *port_dev;
+	ofnode ports_np, node;
+	int ret;
+
+	drv = lists_uclass_lookup(UCLASS_ETH);
+	if (!drv) {
+		puts("Cannot find eth driver");
+		return -ENOENT;
+	}
+
+	ports_np = dev_read_subnode(dev, "ethernet-ports");
+	if (!ofnode_valid(ports_np))
+		return -ENOENT;
+
+	ofnode_for_each_subnode(node, ports_np) {
+		const char *node_name;
+
+		node_name = ofnode_get_name(node);
+
+		ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", node_name, node,
+						 &port_dev);
+		if (ret)
+			dev_err(dev, "Failed to bind to %s node\n", node_name);
+	}
+
+	return ret;
+}
+
 static const struct udevice_id am65_cpsw_nuss_ids[] = {
 	{ .compatible = "ti,am654-cpsw-nuss" },
 	{ .compatible = "ti,j721e-cpsw-nuss" },
@@ -809,6 +834,7 @@ U_BOOT_DRIVER(am65_cpsw_nuss) = {
 	.name	= "am65_cpsw_nuss",
 	.id	= UCLASS_MISC,
 	.of_match = am65_cpsw_nuss_ids,
+	.bind	= am65_cpsw_nuss_bind,
 	.probe	= am65_cpsw_probe_nuss,
 	.priv_auto = sizeof(struct am65_cpsw_common),
 };
-- 
2.34.1

[PATCH v4 02/21] arch: mach-k3: common: Remove explicit probing of CPSW driver

[Chintan Vankar]

This reverts commit e58d9284850fa78d364d264087fe744717963675.

Bind method of am65_cpsw_nuss driver will ensure binding of it's child
driver am65_cpsw_nuss_ports, and there is no need to call CPSW driver
explicitly. Remove explicit probing of CPSW driver for AM62x.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

This patch is newly introduced in this series.

 arch/arm/mach-k3/common.c | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index f8c53b286eb..5483ac9906c 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -322,17 +322,6 @@ void spl_board_prepare_for_linux(void)
 
 int misc_init_r(void)
 {
-	if (IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS)) {
-		struct udevice *dev;
-		int ret;
-
-		ret = uclass_get_device_by_driver(UCLASS_MISC,
-						  DM_DRIVER_GET(am65_cpsw_nuss),
-						  &dev);
-		if (ret)
-			printf("Failed to probe am65_cpsw_nuss driver\n");
-	}
-
 	if (IS_ENABLED(CONFIG_TI_ICSSG_PRUETH)) {
 		struct udevice *dev;
 		int ret;
-- 
2.34.1

[PATCH v4 03/21] Revert "mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPL"

[Chintan Vankar]

This reverts commit 93c43a8365fae0f188ac091d129542470ddaf62d.

Bind method of "am65_cpsw_nuss" driver will ensure binding of it's child
driver "am65_cpsw_nuss_ports", and there is no need to probe CPSW driver
explicitly.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

This patch is newly introduced in this series.

 arch/arm/mach-k3/am64x/am642_init.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/arch/arm/mach-k3/am64x/am642_init.c b/arch/arm/mach-k3/am64x/am642_init.c
index 41812b7dbf7..219798315db 100644
--- a/arch/arm/mach-k3/am64x/am642_init.c
+++ b/arch/arm/mach-k3/am64x/am642_init.c
@@ -263,13 +263,6 @@ void board_init_f(ulong dummy)
 	if (ret)
 		panic("DRAM init failed: %d\n", ret);
 #endif
-	if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) &&
-	    spl_boot_device() == BOOT_DEVICE_ETHERNET) {
-		struct udevice *cpswdev;
-
-		if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), &cpswdev))
-			printf("Failed to probe am65_cpsw_nuss driver\n");
-	}
 }
 
 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
-- 
2.34.1

[PATCH v4 04/21] Revert "arm: mach-k3: am62x: am625_init: Probe AM65 CPSW NUSS"

[Chintan Vankar]

This reverts commit 35bddf889652081f150f60740618851b5d4817f4.

Bind method of "am65_cpsw_nuss" driver will ensure binding of it's child
driver "am65_cpsw_nuss_ports", and there is no need to probe CPSW driver
explicitly.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

Link to v3:
https://lore.kernel.org/u-boot/20250225114903.2080616-3-c-vankar@ti.com/

Changes from v3 to v4:
- Revert the commit which has introduced this patch instead of updating
  the content.

 arch/arm/mach-k3/am62x/am625_init.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c
index a422919fab1..8f4ddf59753 100644
--- a/arch/arm/mach-k3/am62x/am625_init.c
+++ b/arch/arm/mach-k3/am62x/am625_init.c
@@ -294,15 +294,6 @@ void board_init_f(ulong dummy)
 	}
 	spl_enable_cache();
 
-	if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) &&
-	    spl_boot_device() == BOOT_DEVICE_ETHERNET) {
-		struct udevice *cpswdev;
-
-		if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss),
-						&cpswdev))
-			printf("Failed to probe am65_cpsw_nuss driver\n");
-	}
-
 	fixup_a53_cpu_freq_by_speed_grade();
 }
 
-- 
2.34.1

[PATCH v4 05/21] arm: mach-k3: j721s2: Update SoC auto-gen data to enable Ethernet boot

[Chintan Vankar]

Update dev-data and clk-data to include CPSW device which is required to
enable Ethernet boot.

Reviewed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

Link to v3:
https://lore.kernel.org/u-boot/20250225114903.2080616-4-c-vankar@ti.com/

Changes from v3 to v4:
- Updated commit message.

 arch/arm/mach-k3/r5/j721s2/clk-data.c | 58 +++++++++++++++++++++++++--
 arch/arm/mach-k3/r5/j721s2/dev-data.c |  3 +-
 2 files changed, 57 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-k3/r5/j721s2/clk-data.c b/arch/arm/mach-k3/r5/j721s2/clk-data.c
index 0c5c321c1eb..0130c9c4b86 100644
--- a/arch/arm/mach-k3/r5/j721s2/clk-data.c
+++ b/arch/arm/mach-k3/r5/j721s2/clk-data.c
@@ -5,7 +5,7 @@
  * This file is auto generated. Please do not hand edit and report any issues
  * to Dave Gerlach <d-gerlach@ti.com>.
  *
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <linux/clk-provider.h>
@@ -55,6 +55,32 @@ static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
 	"hsdiv4_16fft_mcu_2_hsdivout4_clk",
 };
 
+static const char * const wkup_gpio0_clksel_out0_parents[] = {
+	"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+	"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+	"j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
+	"j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = {
+	"hsdiv4_16fft_main_3_hsdivout1_clk",
+	"postdiv3_16fft_main_0_hsdivout6_clk",
+	"board_0_mcu_cpts0_rft_clk_out",
+	"board_0_cpts0_rft_clk_out",
+	"board_0_mcu_ext_refclk0_out",
+	"board_0_ext_refclk1_out",
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"hsdiv4_16fft_mcu_2_hsdivout1_clk",
+	"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+};
+
 static const char * const mcu_usart_clksel_out0_parents[] = {
 	"hsdiv4_16fft_mcu_1_hsdivout3_clk",
 	"postdiv3_16fft_main_1_hsdivout5_clk",
@@ -174,7 +200,11 @@ static const struct clk_data clk_list[] = {
 	CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
 	CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
+	CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0),
+	CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0),
 	CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
 	CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
 	CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -199,6 +229,8 @@ static const struct clk_data clk_list[] = {
 	CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0),
 	CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
 	CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
+	CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
+	CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0),
 	CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
 	CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
 	CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
@@ -275,6 +307,24 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
 	DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
 	DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(29, 3, "cpsw2g_cpts_rclk_sel_out0"),
+	DEV_CLK(29, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"),
+	DEV_CLK(29, 5, "postdiv3_16fft_main_0_hsdivout6_clk"),
+	DEV_CLK(29, 6, "board_0_mcu_cpts0_rft_clk_out"),
+	DEV_CLK(29, 7, "board_0_cpts0_rft_clk_out"),
+	DEV_CLK(29, 8, "board_0_mcu_ext_refclk0_out"),
+	DEV_CLK(29, 9, "board_0_ext_refclk1_out"),
+	DEV_CLK(29, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
+	DEV_CLK(29, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(29, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(29, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(29, 22, "board_0_mcu_rgmii1_rxc_out"),
+	DEV_CLK(29, 26, "board_0_mcu_rmii1_ref_clk_out"),
+	DEV_CLK(29, 28, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(29, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(29, 30, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(29, 32, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(29, 33, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
 	DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
 	DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"),
 	DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"),
@@ -367,6 +417,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
 	DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 	DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"),
+	DEV_CLK(157, 207, "cpsw_2guss_mcu_0_mdio_mdclk_o"),
 	DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"),
 	DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
 	DEV_CLK(157, 221, "mcu_clkout_mux_out0"),
@@ -374,6 +425,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
 	DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"),
 	DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
+	DEV_CLK(157, 244, "cpsw_2guss_mcu_0_rgmii1_txc_o"),
 	DEV_CLK(157, 352, "dpi0_ext_clksel_out0"),
 	DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"),
 	DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
@@ -400,7 +452,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
 
 const struct ti_k3_clk_platdata j721s2_clk_platdata = {
 	.clk_list = clk_list,
-	.clk_list_cnt = 105,
+	.clk_list_cnt = ARRAY_SIZE(clk_list),
 	.soc_dev_clk_data = soc_dev_clk_data,
-	.soc_dev_clk_data_cnt = 124,
+	.soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
 };
diff --git a/arch/arm/mach-k3/r5/j721s2/dev-data.c b/arch/arm/mach-k3/r5/j721s2/dev-data.c
index df70c5e5d7c..b78550707c5 100644
--- a/arch/arm/mach-k3/r5/j721s2/dev-data.c
+++ b/arch/arm/mach-k3/r5/j721s2/dev-data.c
@@ -5,7 +5,7 @@
  * This file is auto generated. Please do not hand edit and report any issues
  * to Dave Gerlach <d-gerlach@ti.com>.
  *
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "k3-dev.h"
@@ -47,6 +47,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
 };
 
 static struct ti_dev soc_dev_list[] = {
+	PSC_DEV(29, &soc_lpsc_list[0]),
 	PSC_DEV(35, &soc_lpsc_list[0]),
 	PSC_DEV(108, &soc_lpsc_list[0]),
 	PSC_DEV(109, &soc_lpsc_list[0]),
-- 
2.34.1

[PATCH v4 06/21] arm: mach-k3: j721s2_spl: Alias Ethernet boot to CPGMAC

[Chintan Vankar]

This is required to enable spl_net boot on SK-AM68.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

Link to v3:
https://lore.kernel.org/u-boot/20250225114903.2080616-5-c-vankar@ti.com/

Changes from v3 to v4:
- No changes.

 arch/arm/mach-k3/include/mach/j721s2_spl.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-k3/include/mach/j721s2_spl.h b/arch/arm/mach-k3/include/mach/j721s2_spl.h
index d8fae2c8b45..47a61281d94 100644
--- a/arch/arm/mach-k3/include/mach/j721s2_spl.h
+++ b/arch/arm/mach-k3/include/mach/j721s2_spl.h
@@ -12,6 +12,7 @@
 #define BOOT_DEVICE_OSPI		0x01
 #define BOOT_DEVICE_QSPI		0x02
 #define BOOT_DEVICE_SPI			0x03
+#define BOOT_DEVICE_CPGMAC		0x04
 #define BOOT_DEVICE_ETHERNET		0x04
 #define BOOT_DEVICE_I2C			0x06
 #define BOOT_DEVICE_UART		0x07
-- 
2.34.1

[PATCH v4 07/21] net: ti: Kconfig: Enable SPL_SYSCON config for CPSW

[Chintan Vankar]

TI's Ethernet switch needs system controllers enabled in R5SPL stage while
booting via Ethernet. Enable SPL_SYSCON config for
CONFIG_TI_AM65_CPSW_NUSS.

Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

Link to v3:
https://lore.kernel.org/u-boot/20250225114903.2080616-6-c-vankar@ti.com/

Changes from v3 to v4:
- Collected Reviewed-by tag from Alexander Sverdlin.

 drivers/net/ti/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index ddfa95a0b7e..3d495a56670 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -46,6 +46,7 @@ config TI_AM65_CPSW_NUSS
 	imply MISC
 	imply SYSCON
 	imply MDIO_TI_CPSW
+	imply SPL_SYSCON
 	select PHYLIB
 	help
 	  This driver supports TI K3 MCU CPSW Nuss Ethernet controller
-- 
2.34.1

[PATCH v4 08/21] configs: am68_sk_r5_ethboot: Add configs for enabling Ethernet boot in R5SPL

[Chintan Vankar]

Add configs for enabling Ethernet boot in R5SPL, also disable not required
configs to avoid memory limitation.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

Link to v3:
https://lore.kernel.org/u-boot/20250225114903.2080616-7-c-vankar@ti.com/

Changes from v3 to v4:
- No changes.

 configs/am68_sk_r5_ethboot_defconfig | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 configs/am68_sk_r5_ethboot_defconfig

diff --git a/configs/am68_sk_r5_ethboot_defconfig b/configs/am68_sk_r5_ethboot_defconfig
new file mode 100644
index 00000000000..f0815b781d5
--- /dev/null
+++ b/configs/am68_sk_r5_ethboot_defconfig
@@ -0,0 +1,23 @@
+#include <configs/am68_sk_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J721S2=y
+CONFIG_TARGET_J721S2_R5_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am68-sk-r5-base-board"
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM68 U-Boot R5 SPL"
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_SPI=n
+CONFIG_SPL_SPI=n
+CONFIG_DM_SPI=n
+CONFIG_MTD=n
+CONFIG_SPL_MTD=n
+CONFIG_SPL_NAND_SPI_SUPPORT=n
+CONFIG_NOR_SUPPORT=n
+CONFIG_SPL_NOR_SUPPORT=n
+CONFIG_SYS_MALLOC_CLEAR_ON_INIT=n
-- 
2.34.1

[PATCH v4 09/21] configs: am68_sk_a72_ethboot: Enable configs required for Ethernet boot

[Chintan Vankar]

Enable config options needed to support Ethernet boot on AM68-SK.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

Link to v3:
https://lore.kernel.org/u-boot/20250225114903.2080616-8-c-vankar@ti.com/

Changes from v3 to v4:
- No changes.

 configs/am68_sk_a72_ethboot_defconfig | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 configs/am68_sk_a72_ethboot_defconfig

diff --git a/configs/am68_sk_a72_ethboot_defconfig b/configs/am68_sk_a72_ethboot_defconfig
new file mode 100644
index 00000000000..d9d6ca6088e
--- /dev/null
+++ b/configs/am68_sk_a72_ethboot_defconfig
@@ -0,0 +1,14 @@
+#include <configs/am68_sk_a72_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J721S2=y
+CONFIG_TARGET_J721S2_A72_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am68-sk-base-board"
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM68 U-Boot A72 SPL"
-- 
2.34.1

[PATCH v4 10/21] arm: mach-k3: am62p: Update SoC auto-gen data to enable Ethernet boot

[Chintan Vankar]

From: Andreas Dannenberg <dannenberg@ti.com>

Update dev-data and clk-data to enable Ethernet boot using CPSW on
SK-AM62P-LP.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

Link to v3:
https://lore.kernel.org/u-boot/20250225114903.2080616-9-c-vankar@ti.com/

Changes from v3 to v4:
- No changes.

 arch/arm/mach-k3/r5/am62px/clk-data.c | 44 +++++++++++++++++++++++++--
 arch/arm/mach-k3/r5/am62px/dev-data.c | 24 ++++++++-------
 2 files changed, 54 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c b/arch/arm/mach-k3/r5/am62px/clk-data.c
index bc62d1d0d08..b552a2be74d 100644
--- a/arch/arm/mach-k3/r5/am62px/clk-data.c
+++ b/arch/arm/mach-k3/r5/am62px/clk-data.c
@@ -5,7 +5,7 @@
  * This file is auto generated. Please do not hand edit and report any issues
  * to Bryan Brattlof <bb@ti.com>.
  *
- * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <linux/clk-provider.h>
@@ -62,6 +62,17 @@ static const char * const clkout0_ctrl_out0_parents[] = {
 	"hsdiv4_16fft_main_2_hsdivout1_clk10",
 };
 
+static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
+	"postdiv4_16ff_main_2_hsdivout5_clk",
+	"postdiv4_16ff_main_0_hsdivout6_clk",
+	"board_0_cp_gemac_cpts0_rft_clk_out",
+	NULL,
+	"board_0_mcu_ext_refclk0_out",
+	"board_0_ext_refclk1_out",
+	NULL,
+	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
 static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
 	"postdiv4_16ff_main_0_hsdivout5_clk",
 	"hsdiv4_16fft_main_2_hsdivout2_clk",
@@ -99,8 +110,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = {
 	"board_0_cp_gemac_cpts0_rft_clk_out",
 	"hsdiv4_16fft_main_1_hsdivout3_clk",
 	"postdiv4_16ff_main_2_hsdivout6_clk",
-	NULL,
-	NULL,
+	"cpsw_3guss_am67_main_0_cpts_genf0",
+	"cpsw_3guss_am67_main_0_cpts_genf1",
 	NULL,
 	NULL,
 	NULL,
@@ -148,7 +159,12 @@ static const struct clk_data clk_list[] = {
 	CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
 	CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
+	CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
+	CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_tck_out", 0, 0),
+	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0),
+	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0),
+	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0),
 	CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
 	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
 	CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -201,6 +217,7 @@ static const struct clk_data clk_list[] = {
 	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
 	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
 	CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
+	CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
 	CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
 	CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
 	CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
@@ -216,6 +233,24 @@ static const struct clk_data clk_list[] = {
 };
 
 static const struct dev_clk soc_dev_clk_data[] = {
+	DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
+	DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
+	DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
+	DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
+	DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
+	DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
+	DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"),
+	DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"),
 	DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
 	DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
 	DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -240,6 +275,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
 	DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
 	DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
+	DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"),
+	DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"),
 	DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
 	DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
@@ -286,6 +323,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(157, 54, "mshsi2c_main_0_porscl"),
 	DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
+	DEV_CLK(157, 96, "cpsw_3guss_am67_main_0_mdio_mdclk_o"),
 	DEV_CLK(157, 101, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 	DEV_CLK(157, 103, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 	DEV_CLK(157, 143, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
diff --git a/arch/arm/mach-k3/r5/am62px/dev-data.c b/arch/arm/mach-k3/r5/am62px/dev-data.c
index 3cc211ea202..63e6beb4d57 100644
--- a/arch/arm/mach-k3/r5/am62px/dev-data.c
+++ b/arch/arm/mach-k3/r5/am62px/dev-data.c
@@ -5,7 +5,7 @@
  * This file is auto generated. Please do not hand edit and report any issues
  * to Bryan Brattlof <bb@ti.com>.
  *
- * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "k3-dev.h"
@@ -31,11 +31,12 @@ static struct ti_lpsc soc_lpsc_list[] = {
 	[6] = PSC_LPSC(24, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
 	[7] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
 	[8] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
-	[9] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]),
-	[10] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[9]),
-	[11] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
-	[12] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
-	[13] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]),
+	[9] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]),
+	[10] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]),
+	[11] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[10]),
+	[12] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
+	[13] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]),
+	[14] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[13]),
 };
 
 static struct ti_dev soc_dev_list[] = {
@@ -52,11 +53,12 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(36, &soc_lpsc_list[8]),
 	PSC_DEV(102, &soc_lpsc_list[8]),
 	PSC_DEV(146, &soc_lpsc_list[8]),
-	PSC_DEV(166, &soc_lpsc_list[9]),
-	PSC_DEV(135, &soc_lpsc_list[10]),
-	PSC_DEV(170, &soc_lpsc_list[11]),
-	PSC_DEV(177, &soc_lpsc_list[12]),
-	PSC_DEV(55, &soc_lpsc_list[13]),
+	PSC_DEV(13, &soc_lpsc_list[9]),
+	PSC_DEV(166, &soc_lpsc_list[10]),
+	PSC_DEV(135, &soc_lpsc_list[11]),
+	PSC_DEV(170, &soc_lpsc_list[12]),
+	PSC_DEV(177, &soc_lpsc_list[13]),
+	PSC_DEV(55, &soc_lpsc_list[14]),
 };
 
 const struct ti_k3_pd_platdata am62px_pd_platdata = {
-- 
2.34.1

[PATCH v4 11/21] board: ti: am62px: evm: Enable cache for AM62p

[Chintan Vankar]

From: Andreas Dannenberg <dannenberg@ti.com>

Enable cache for AM62p to optimize performance of CPU to access data from
memory.

Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

Link to v3:
https://lore.kernel.org/u-boot/20250225114903.2080616-10-c-vankar@ti.com/

Changes from v3 to v4:
- Collected Reviewed-by from Alexander Sverdlin.

 board/ti/am62px/evm.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c
index 2e85363cf5f..c06e3878d67 100644
--- a/board/ti/am62px/evm.c
+++ b/board/ti/am62px/evm.c
@@ -9,6 +9,7 @@
 #include <efi_loader.h>
 #include <asm/arch/hardware.h>
 #include <asm/io.h>
+#include <cpu_func.h>
 #include <dm/uclass.h>
 #include <env.h>
 #include <fdt_support.h>
@@ -41,6 +42,13 @@ struct efi_capsule_update_info update_info = {
 	.images = fw_images,
 };
 
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+void spl_board_init(void)
+{
+	enable_caches();
+}
+#endif
+
 #if defined(CONFIG_XPL_BUILD)
 void spl_perform_fixups(struct spl_image_info *spl_image)
 {
-- 
2.34.1

[PATCH v4 12/21] configs: am62px_evm_r5_ethboot: Add configs to enable Ethernet boot in R5SPL

[Chintan Vankar]

From: Andreas Dannenberg <dannenberg@ti.com>

Add configs for enabling Ethernet boot in R5SPL, also disable not required
configs to avoid memory limitation.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

Link to v3:
https://lore.kernel.org/u-boot/20250225114903.2080616-11-c-vankar@ti.com/

Changes from v3 to v4:
- No changes.

 configs/am62px_evm_r5_ethboot_defconfig | 29 +++++++++++++++++++++++++
 1 file changed, 29 insertions(+)
 create mode 100644 configs/am62px_evm_r5_ethboot_defconfig

diff --git a/configs/am62px_evm_r5_ethboot_defconfig b/configs/am62px_evm_r5_ethboot_defconfig
new file mode 100644
index 00000000000..dfd944ad7c0
--- /dev/null
+++ b/configs/am62px_evm_r5_ethboot_defconfig
@@ -0,0 +1,29 @@
+#include<configs/am62px_evm_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_AM62P5=y
+CONFIG_TARGET_AM62P5_R5_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-r5-sk"
+CONFIG_NET=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM62PX U-Boot R5 SPL"
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_SPL_SPI=n
+CONFIG_SPL_MMC=n
+CONFIG_SPL_MTD_LOAD=n
+CONFIG_SPL_NAND_SPI_SUPPORT=n
+CONFIG_SPL_DM_DEVICE_REMOVE=n
+CONFIG_DM_MTD=n
+CONFIG_MTD_SPI_NAND=n
+CONFIG_DM_SPI_FLASH=n
+CONFIG_SPI=n
+CONFIG_DM_SPI=n
+CONFIG_CADENCE_QSPI=n
-- 
2.34.1

[PATCH v4 13/21] configs: am62px_evm_a53_ethboot: Enable configs required for Ethboot

[Chintan Vankar]

Enable config options needed to support Ethernet boot on SK-AM62P-LP.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

Link to v3:
https://lore.kernel.org/u-boot/20250225114903.2080616-12-c-vankar@ti.com/

Changes from v3 to v4:
- No changes.

 configs/am62px_evm_a53_ethboot_defconfig | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 configs/am62px_evm_a53_ethboot_defconfig

diff --git a/configs/am62px_evm_a53_ethboot_defconfig b/configs/am62px_evm_a53_ethboot_defconfig
new file mode 100644
index 00000000000..57da40d4b2e
--- /dev/null
+++ b/configs/am62px_evm_a53_ethboot_defconfig
@@ -0,0 +1,13 @@
+#include <configs/am62px_evm_a53_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_AM62P5=y
+CONFIG_TARGET_AM62P5_A53_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62p5-sk"
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM62PX U-Boot A53 SPL"
-- 
2.34.1

[PATCH v4 14/21] arm: mach-k3: j722s: Update SoC autogenerated data to enable Ethernet boot

[Chintan Vankar]

Update dev-data and clk-data to include CPSW device which is required to
enable Ethernet boot.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

Link to v3:
https://lore.kernel.org/u-boot/20250225114903.2080616-13-c-vankar@ti.com/

Changes from v3 to v4:
- No changes.

 arch/arm/mach-k3/r5/j722s/clk-data.c | 50 ++++++++++++++++++++++------
 arch/arm/mach-k3/r5/j722s/dev-data.c | 34 +++++++++----------
 2 files changed, 56 insertions(+), 28 deletions(-)

diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c b/arch/arm/mach-k3/r5/j722s/clk-data.c
index b4f27af333d..238d57d0aa0 100644
--- a/arch/arm/mach-k3/r5/j722s/clk-data.c
+++ b/arch/arm/mach-k3/r5/j722s/clk-data.c
@@ -5,7 +5,7 @@
  * This file is auto generated. Please do not hand edit and report any issues
  * to Bryan Brattlof <bb@ti.com>.
  *
- * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <linux/clk-provider.h>
@@ -57,9 +57,15 @@ static const char * const clkout0_ctrl_out0_parents[] = {
 	"hsdiv4_16fft_main_2_hsdivout1_clk",
 };
 
-static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
-	"postdiv4_16ff_main_0_hsdivout5_clk",
-	"hsdiv4_16fft_main_2_hsdivout2_clk",
+static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
+	"postdiv4_16ff_main_2_hsdivout5_clk",
+	"postdiv4_16ff_main_0_hsdivout6_clk",
+	"board_0_cp_gemac_cpts0_rft_clk_out",
+	NULL,
+	"board_0_mcu_ext_refclk0_out",
+	"board_0_ext_refclk1_out",
+	NULL,
+	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
 };
 
 static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
@@ -94,8 +100,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = {
 	"board_0_cp_gemac_cpts0_rft_clk_out",
 	"hsdiv4_16fft_main_1_hsdivout3_clk",
 	"postdiv4_16ff_main_2_hsdivout6_clk",
-	NULL,
-	NULL,
+	"cpsw_3guss_am67_main_0_cpts_genf0",
+	"cpsw_3guss_am67_main_0_cpts_genf1",
 	NULL,
 	NULL,
 	NULL,
@@ -143,7 +149,12 @@ static const struct clk_data clk_list[] = {
 	CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
 	CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
+	CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
+	CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_tck_out", 0, 0),
+	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0),
+	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0),
+	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0),
 	CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
 	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
 	CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -194,7 +205,7 @@ static const struct clk_data clk_list[] = {
 	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
 	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
 	CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
-	CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
+	CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
 	CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
 	CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
 	CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
@@ -209,6 +220,24 @@ static const struct clk_data clk_list[] = {
 };
 
 static const struct dev_clk soc_dev_clk_data[] = {
+	DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
+	DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
+	DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
+	DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
+	DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
+	DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
+	DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+	DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"),
+	DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"),
 	DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
 	DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
 	DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -233,10 +262,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
 	DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
 	DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
-	DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
-	DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
-	DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
-	DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+	DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"),
+	DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"),
 	DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
 	DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
 	DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
@@ -279,6 +306,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(157, 74, "mshsi2c_main_0_porscl"),
 	DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
+	DEV_CLK(157, 140, "cpsw_3guss_am67_main_0_mdio_mdclk_o"),
 	DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 	DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 	DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
diff --git a/arch/arm/mach-k3/r5/j722s/dev-data.c b/arch/arm/mach-k3/r5/j722s/dev-data.c
index 59176c98999..d6832266884 100644
--- a/arch/arm/mach-k3/r5/j722s/dev-data.c
+++ b/arch/arm/mach-k3/r5/j722s/dev-data.c
@@ -5,7 +5,7 @@
  * This file is auto generated. Please do not hand edit and report any issues
  * to Bryan Brattlof <bb@ti.com>.
  *
- * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "k3-dev.h"
@@ -23,16 +23,16 @@ static struct ti_pd soc_pd_list[] = {
 
 static struct ti_lpsc soc_lpsc_list[] = {
 	[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
-	[1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
-	[2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
-	[3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
-	[4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
-	[5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
-	[6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
-	[7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
-	[8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[7]),
+	[1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
+	[2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
+	[3] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+	[4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+	[5] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+	[6] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+	[7] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
+	[8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[6]),
 	[9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]),
-	[10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]),
+	[10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]),
 	[11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]),
 	[12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
 };
@@ -43,13 +43,13 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(61, &soc_lpsc_list[0]),
 	PSC_DEV(178, &soc_lpsc_list[1]),
 	PSC_DEV(179, &soc_lpsc_list[2]),
-	PSC_DEV(57, &soc_lpsc_list[3]),
-	PSC_DEV(58, &soc_lpsc_list[4]),
-	PSC_DEV(161, &soc_lpsc_list[5]),
-	PSC_DEV(75, &soc_lpsc_list[6]),
-	PSC_DEV(36, &soc_lpsc_list[7]),
-	PSC_DEV(102, &soc_lpsc_list[7]),
-	PSC_DEV(146, &soc_lpsc_list[7]),
+	PSC_DEV(58, &soc_lpsc_list[3]),
+	PSC_DEV(161, &soc_lpsc_list[4]),
+	PSC_DEV(75, &soc_lpsc_list[5]),
+	PSC_DEV(36, &soc_lpsc_list[6]),
+	PSC_DEV(102, &soc_lpsc_list[6]),
+	PSC_DEV(146, &soc_lpsc_list[6]),
+	PSC_DEV(13, &soc_lpsc_list[7]),
 	PSC_DEV(166, &soc_lpsc_list[8]),
 	PSC_DEV(135, &soc_lpsc_list[9]),
 	PSC_DEV(170, &soc_lpsc_list[10]),
-- 
2.34.1

[PATCH v4 15/21] board: ti: j722s: evm: Enable cache for J722s

[Chintan Vankar]

Enable cache for J722s to optimize performance of CPU to access data from
memory.

Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

Link to v3:
https://lore.kernel.org/u-boot/20250225114903.2080616-14-c-vankar@ti.com/

Changes from v3 to v4:
- Collected Reviewed-by from Alexander Sverdlin.

 board/ti/j722s/evm.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/board/ti/j722s/evm.c b/board/ti/j722s/evm.c
index d2b94913c12..32d767cb7d2 100644
--- a/board/ti/j722s/evm.c
+++ b/board/ti/j722s/evm.c
@@ -8,6 +8,7 @@
 
 #include <asm/arch/hardware.h>
 #include <asm/io.h>
+#include <cpu_func.h>
 #include <dm/uclass.h>
 #include <env.h>
 #include <fdt_support.h>
@@ -15,6 +16,13 @@
 #include <asm/arch/k3-ddr.h>
 #include "../common/fdt_ops.h"
 
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+void spl_board_init(void)
+{
+	enable_caches();
+}
+#endif
+
 #if defined(CONFIG_XPL_BUILD)
 void spl_perform_fixups(struct spl_image_info *spl_image)
 {
-- 
2.34.1

[PATCH v4 16/21] configs: j722s_evm_r5_ethboot: Add configs to enable Ethernet boot in R5SPL

[Chintan Vankar]

Add configs to enable Ethernet boot in R5SPL, also disable not required
configs to avoid memory limitation.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

Link to v3:
https://lore.kernel.org/u-boot/20250225114903.2080616-15-c-vankar@ti.com/

Changes from v3 to v4:
- No changes.

 configs/j722s_evm_r5_ethboot_defconfig | 30 ++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 configs/j722s_evm_r5_ethboot_defconfig

diff --git a/configs/j722s_evm_r5_ethboot_defconfig b/configs/j722s_evm_r5_ethboot_defconfig
new file mode 100644
index 00000000000..fd58485bff2
--- /dev/null
+++ b/configs/j722s_evm_r5_ethboot_defconfig
@@ -0,0 +1,30 @@
+#include<configs/j722s_evm_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J722S=y
+CONFIG_TARGET_J722S_R5_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-j722s-r5-evm"
+CONFIG_NET=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200000
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="J722S U-Boot R5 SPL"
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_SPL_MMC=n
+CONFIG_SPL_SPI=n
+CONFIG_SPL_MTD_LOAD=n
+CONFIG_SPL_NAND_SPI_SUPPORT=n
+CONFIG_SPL_DM_DEVICE_REMOVE=n
+CONFIG_DM_MTD=n
+CONFIG_MTD_SPI_NAND=n
+CONFIG_DM_SPI_FLASH=n
+CONFIG_SPI=n
+CONFIG_DM_SPI=n
+CONFIG_CADENCE_QSPI=n
-- 
2.34.1

[PATCH v4 17/21] configs: j722s_evm_a53_ethboot: Enable configs required for Ethernet boot

[Chintan Vankar]

Enable configs required to support Ethernet boot for J722S.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

Link to v3:
https://lore.kernel.org/u-boot/20250225114903.2080616-16-c-vankar@ti.com/

Changes from v3 to v4:
- No changes.

 configs/j722s_evm_a53_ethboot_defconfig | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 configs/j722s_evm_a53_ethboot_defconfig

diff --git a/configs/j722s_evm_a53_ethboot_defconfig b/configs/j722s_evm_a53_ethboot_defconfig
new file mode 100644
index 00000000000..a5a2a15849c
--- /dev/null
+++ b/configs/j722s_evm_a53_ethboot_defconfig
@@ -0,0 +1,13 @@
+#include <configs/j722s_evm_a53_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J722S=y
+CONFIG_TARGET_J722S_A53_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-j722s-evm"
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ETH=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="J722S U-Boot A53 SPL"
-- 
2.34.1

[PATCH v4 18/21] arm: mach-k3: j784s4: Update SoC auto-gen data to enable Ethernet boot

[Chintan Vankar]

Update dev-data and clk-data to include CPSW device which is required to
enable Ethernet boot for SK-AM69.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

This patch is newly introduced in this series.

 arch/arm/mach-k3/r5/j784s4/clk-data.c | 54 ++++++++++++++++++++++++---
 arch/arm/mach-k3/r5/j784s4/dev-data.c |  1 +
 2 files changed, 50 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c
index 97d969271ec..24780eb6562 100644
--- a/arch/arm/mach-k3/r5/j784s4/clk-data.c
+++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c
@@ -57,6 +57,25 @@ static const char * const wkup_gpio0_clksel_out0_parents[] = {
 	"j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
 };
 
+static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = {
+	"hsdiv4_16fft_main_3_hsdivout1_clk",
+	"postdiv3_16fft_main_0_hsdivout6_clk",
+	"board_0_mcu_cpts0_rft_clk_out",
+	"board_0_cpts0_rft_clk_out",
+	"board_0_mcu_ext_refclk0_out",
+	"board_0_ext_refclk1_out",
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+	"hsdiv4_16fft_mcu_2_hsdivout1_clk",
+	"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+};
+
 static const char * const mcu_usart_clksel_out0_parents[] = {
 	"hsdiv4_16fft_mcu_1_hsdivout3_clk",
 	"postdiv3_16fft_main_1_hsdivout5_clk",
@@ -132,6 +151,11 @@ static const char * const main_pll_hfosc_sel_out8_parents[] = {
 	"board_0_hfosc1_clk_out",
 };
 
+static const char * const mcu_clkout_mux_out0_parents[] = {
+	"hsdiv4_16fft_mcu_2_hsdivout0_clk",
+	"hsdiv4_16fft_mcu_2_hsdivout1_clk",
+};
+
 static const char * const usb0_refclk_sel_out0_parents[] = {
 	"gluelogic_hfosc0_clkout",
 	"board_0_hfosc1_clk_out",
@@ -142,11 +166,6 @@ static const char * const emmcsd1_lb_clksel_out0_parents[] = {
 	"board_0_mmc1_clk_out",
 };
 
-static const char * const mcu_clkout_mux_out0_parents[] = {
-	"hsdiv4_16fft_mcu_2_hsdivout0_clk",
-	"hsdiv4_16fft_mcu_2_hsdivout1_clk",
-};
-
 static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
 	"main_pll_hfosc_sel_out0",
 	"hsdiv4_16fft_main_0_hsdivout0_clk",
@@ -201,7 +220,11 @@ static const struct clk_data clk_list[] = {
 	CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
 	CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0),
+	CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0),
 	CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
+	CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0),
+	CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0),
 	CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
 	CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
 	CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
@@ -224,6 +247,7 @@ static const struct clk_data clk_list[] = {
 	CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
 	CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
 	CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
+	CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0),
 	CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
 	CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
 	CLK_MUX("wkup_usart_clksel_out0", wkup_usart_clksel_out0_parents, 2, 0x43008064, 0, 1, 0),
@@ -317,6 +341,24 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(61, 15, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
 	DEV_CLK(61, 16, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 	DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(63, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(63, 3, "cpsw2g_cpts_rclk_sel_out0"),
+	DEV_CLK(63, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"),
+	DEV_CLK(63, 5, "postdiv3_16fft_main_0_hsdivout6_clk"),
+	DEV_CLK(63, 6, "board_0_mcu_cpts0_rft_clk_out"),
+	DEV_CLK(63, 7, "board_0_cpts0_rft_clk_out"),
+	DEV_CLK(63, 8, "board_0_mcu_ext_refclk0_out"),
+	DEV_CLK(63, 9, "board_0_ext_refclk1_out"),
+	DEV_CLK(63, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
+	DEV_CLK(63, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+	DEV_CLK(63, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(63, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(63, 22, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(63, 24, "board_0_mcu_rgmii1_rxc_out"),
+	DEV_CLK(63, 27, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(63, 28, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(63, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+	DEV_CLK(63, 30, "board_0_mcu_rmii1_ref_clk_out"),
 	DEV_CLK(78, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
 	DEV_CLK(78, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
 	DEV_CLK(78, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -353,10 +395,12 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
 	DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
 	DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
+	DEV_CLK(157, 190, "cpsw_2guss_mcu_0_mdio_mdclk_o"),
 	DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
 	DEV_CLK(157, 226, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
 	DEV_CLK(157, 228, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
 	DEV_CLK(157, 230, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
+	DEV_CLK(157, 233, "cpsw_2guss_mcu_0_rgmii1_txc_o"),
 	DEV_CLK(157, 239, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
 	DEV_CLK(157, 243, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
 	DEV_CLK(157, 245, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
diff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c
index b32b4ba9588..19901821225 100644
--- a/arch/arm/mach-k3/r5/j784s4/dev-data.c
+++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c
@@ -54,6 +54,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
 };
 
 static struct ti_dev soc_dev_list[] = {
+	PSC_DEV(63, &soc_lpsc_list[0]),
 	PSC_DEV(35, &soc_lpsc_list[0]),
 	PSC_DEV(160, &soc_lpsc_list[0]),
 	PSC_DEV(161, &soc_lpsc_list[0]),
-- 
2.34.1

[PATCH v4 19/21] arm: mach-k3: j784s4_spl: Alias Ethernet boot to CPGMAC

[Chintan Vankar]

This is required to enable spl_net boot on SK-AM69.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

This patch is newly introduced in this series.

 arch/arm/mach-k3/include/mach/j784s4_spl.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-k3/include/mach/j784s4_spl.h b/arch/arm/mach-k3/include/mach/j784s4_spl.h
index d481a46c675..3814dc95d01 100644
--- a/arch/arm/mach-k3/include/mach/j784s4_spl.h
+++ b/arch/arm/mach-k3/include/mach/j784s4_spl.h
@@ -44,4 +44,6 @@
 #define K3_PRIMARY_BOOTMODE		0x0
 #define K3_BACKUP_BOOTMODE		0x1
 
+#define BOOT_DEVICE_CPGMAC              0x04
+
 #endif
-- 
2.34.1

[PATCH v4 20/21] configs: am69_sk_r5_ethboot: Add configs to enable Ethernet boot in R5SPL

[Chintan Vankar]

Add configs required to enable Ethernet boot for SK-AM69.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

This patch is newly introduced in this series.

 configs/am69_sk_r5_ethboot_defconfig | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 configs/am69_sk_r5_ethboot_defconfig

diff --git a/configs/am69_sk_r5_ethboot_defconfig b/configs/am69_sk_r5_ethboot_defconfig
new file mode 100644
index 00000000000..c85aa72cf04
--- /dev/null
+++ b/configs/am69_sk_r5_ethboot_defconfig
@@ -0,0 +1,15 @@
+#include <configs/am69_sk_r5_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J784S4=y
+CONFIG_TARGET_J784S4_R5_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am69-r5-sk"
+CONFIG_SPL_ETH=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM69 U-Boot R5 SPL"
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_TI_I2C_BOARD_DETECT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
-- 
2.34.1

[PATCH v4 21/21] configs: am69_sk_a72_ethboot: Add configs to enable Ethernet boot

[Chintan Vankar]

Add configs required to enable Ethernet boot for SK-AM69.

Signed-off-by: Chintan Vankar <c-vankar@ti.com>
---

This patch is newly introduced in this series.

 configs/am69_sk_a72_ethboot_defconfig | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 configs/am69_sk_a72_ethboot_defconfig

diff --git a/configs/am69_sk_a72_ethboot_defconfig b/configs/am69_sk_a72_ethboot_defconfig
new file mode 100644
index 00000000000..676db01b2e2
--- /dev/null
+++ b/configs/am69_sk_a72_ethboot_defconfig
@@ -0,0 +1,11 @@
+#include <configs/am69_sk_a72_defconfig>
+
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SOC_K3_J784S4=y
+CONFIG_TARGET_J784S4_A72_EVM=y
+CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am69-sk"
+CONFIG_SPL_ETH=y
+CONFIG_SPL_NET=y
+CONFIG_SPL_NET_VCI_STRING="AM69 U-Boot A72 SPL"
+CONFIG_SYS_K3_SPL_ATF=y
-- 
2.34.1

Re: [PATCH v4 00/21] Add support for Ethernet boot

[Tom Rini]

On Thu, 31 Jul 2025 13:29:35 +0530, Chintan Vankar wrote:

> This series adds bind method for CPSW to avoid explicit probing, removes
> explicit probing of CPSW, adds support for Ethernet boot on SK-AM68,
> SK-AM62P-LP, J722S, SK-AM69.
> 
> This series is based on commit 'a8f20bb6650df56d' of origin/master
> branch of U-Boot.
> 
> [...]

Applied to u-boot/next, thanks!

[01/21] net: ti: am65-cpsw-nuss: Define bind method for CPSW driver
        commit: 3943531a54680b76813960655458e88f49f6bfb7
[02/21] arch: mach-k3: common: Remove explicit probing of CPSW driver
        commit: 50ededad3204072a5fe6b8ee49826643e7c8e7aa
[03/21] Revert "mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPL"
        commit: 3967d64740b69cda6b2642036bfb9269b05a7e35
[04/21] Revert "arm: mach-k3: am62x: am625_init: Probe AM65 CPSW NUSS"
        commit: b4a0702c924851906b1c127b3c9884e8a4870bd1
[05/21] arm: mach-k3: j721s2: Update SoC auto-gen data to enable Ethernet boot
        commit: 0b092a2aa81b84eba1ea48f87c04b0be62afd1e9
[06/21] arm: mach-k3: j721s2_spl: Alias Ethernet boot to CPGMAC
        commit: e85b090165ec55ef7e19bdd7fc11e9e6f74ec58e
[07/21] net: ti: Kconfig: Enable SPL_SYSCON config for CPSW
        commit: 333b50d32d76ded3d69e3f65d47ca0de1d32dcc4
[08/21] configs: am68_sk_r5_ethboot: Add configs for enabling Ethernet boot in R5SPL
        commit: 07774020f75b51fc3437d697528cac5978b407ac
[09/21] configs: am68_sk_a72_ethboot: Enable configs required for Ethernet boot
        commit: 3325b13d53f5a8991185936adc981678eb6d1b97
[10/21] arm: mach-k3: am62p: Update SoC auto-gen data to enable Ethernet boot
        commit: 6fc2a6a97171e0d4ecb8cef9385fb1a0a0a14611
[11/21] board: ti: am62px: evm: Enable cache for AM62p
        commit: 3bab8f17fb17c59f83ef409eb14b3aec92cd3f9b
[12/21] configs: am62px_evm_r5_ethboot: Add configs to enable Ethernet boot in R5SPL
        commit: c8c2da2ab817d78efdad88b85ef4449dd5719e01
[13/21] configs: am62px_evm_a53_ethboot: Enable configs required for Ethboot
        commit: c1f1d28c44543dc0fd74653215e25f5153ddd398
[14/21] arm: mach-k3: j722s: Update SoC autogenerated data to enable Ethernet boot
        commit: a02009f3a816e7de42fccff895397906304290ef
[15/21] board: ti: j722s: evm: Enable cache for J722s
        commit: 80b529d8776fe48eb595bc3eaf739751b5bea15c
[16/21] configs: j722s_evm_r5_ethboot: Add configs to enable Ethernet boot in R5SPL
        commit: d449db6cd7c896d69e2dba2b902797d9b329beef
[17/21] configs: j722s_evm_a53_ethboot: Enable configs required for Ethernet boot
        commit: 9def2b0fc17d5ed1162d6a8fbe9a06ec26557512
[18/21] arm: mach-k3: j784s4: Update SoC auto-gen data to enable Ethernet boot
        commit: 8eecd9edb58e57018ce1a9adf9283d88541e974f
[19/21] arm: mach-k3: j784s4_spl: Alias Ethernet boot to CPGMAC
        commit: 721d5c30f5704c78e7e45fa0234c8096a1bcd683
[20/21] configs: am69_sk_r5_ethboot: Add configs to enable Ethernet boot in R5SPL
        commit: 02b2a3277116d80137e62cb931dd365eda54790c
[21/21] configs: am69_sk_a72_ethboot: Add configs to enable Ethernet boot
        commit: 841d3d06ce2c1fb9d7a785bd7df5a1b6b70003bb
-- 
Tom

Re: [PATCH v4 01/21] net: ti: am65-cpsw-nuss: Define bind method for CPSW driver

[Wadim Egorov]

Hi,


On 7/31/25 10:59 AM, Chintan Vankar wrote:
> CPSW driver is defined as UCLASS_MISC driver which needs to be probed
> explicitly. Define bind method for CPSW driver to scan and bind
> ethernet-ports with UCLASS_ETH driver which will eventually probe CPSW
> driver and avoid probing CPSW driver explicitly.


I just noticed a new error message with this patch.

On the phycore-am64x we can see that the 2nd cpsw port is getting probed 
but fails. This is not really an Issue because we are not making use of 
the 2nd port. But the error message does not look nice.

Why is this even probed? The soc-level device tree disables the ports 
per default. And we do not activate it in our device tree.


U-Boot 2025.10-rc1-00085-git (Nov 21 2025 - 14:48:38 +0200)

SoC:   AM64X SR2.0 HS-FS
Model: PHYTEC phyBOARD-Electra-AM64x RDK
DRAM:  2 GiB
I/TC: Reserved shared memory is enabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are disabled
Core:  89 devices, 35 uclasses, devicetree: separate
MMC:   mmc@fa10000: 0, mmc@fa00000: 1
Loading Environment from MMC... Reading from MMC(1)... OK
In:    serial@2800000
Out:   serial@2800000
Err:   serial@2800000
Net:   eth0: ethernet@8000000port@1am65_cpsw_nuss_port 
ethernet@8000000port@2: Invalid PHY mode, port 2

Hit any key to stop autoboot: 0
=>


Regards,
Wadim

> 
> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
> ---
> 
> Link to v3:
> https://lore.kernel.org/u-boot/20250225114903.2080616-2-c-vankar@ti.com/
> 
> Changes from v3 to v4:
> - Moved initialization part from "am65_cpsw_probe_nuss()" to
>    "am65_cpsw_nuss_bind()" method.
> 
>   drivers/net/ti/am65-cpsw-nuss.c | 40 +++++++++++++++++++++++++++------
>   1 file changed, 33 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
> index 9b69f36d04d..754076d807c 100644
> --- a/drivers/net/ti/am65-cpsw-nuss.c
> +++ b/drivers/net/ti/am65-cpsw-nuss.c
> @@ -705,7 +705,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev)
>   	struct am65_cpsw_common *cpsw_common = dev_get_priv(dev);
>   	ofnode ports_np, node;
>   	int ret, i;
> -	struct udevice *port_dev;
>   
>   	cpsw_common->dev = dev;
>   	cpsw_common->ss_base = dev_read_addr(dev);
> @@ -732,6 +731,7 @@ static int am65_cpsw_probe_nuss(struct udevice *dev)
>   	ports_np = dev_read_subnode(dev, "ethernet-ports");
>   	if (!ofnode_valid(ports_np)) {
>   		ret = -ENOENT;
> +		dev_err(dev, "Invalid device tree node %d\n", ret);
>   		goto out;
>   	}
>   
> @@ -763,12 +763,6 @@ static int am65_cpsw_probe_nuss(struct udevice *dev)
>   			continue;
>   
>   		cpsw_common->ports[port_id].disabled = disabled;
> -		if (disabled)
> -			continue;
> -
> -		ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", ofnode_get_name(node), node, &port_dev);
> -		if (ret)
> -			dev_err(dev, "Failed to bind to %s node\n", ofnode_get_name(node));
>   	}
>   
>   	for (i = 0; i < AM65_CPSW_CPSWNU_MAX_PORTS; i++) {
> @@ -798,6 +792,37 @@ out:
>   	return ret;
>   }
>   
> +static int am65_cpsw_nuss_bind(struct udevice *dev)
> +{
> +	struct uclass_driver *drv;
> +	struct udevice *port_dev;
> +	ofnode ports_np, node;
> +	int ret;
> +
> +	drv = lists_uclass_lookup(UCLASS_ETH);
> +	if (!drv) {
> +		puts("Cannot find eth driver");
> +		return -ENOENT;
> +	}
> +
> +	ports_np = dev_read_subnode(dev, "ethernet-ports");
> +	if (!ofnode_valid(ports_np))
> +		return -ENOENT;
> +
> +	ofnode_for_each_subnode(node, ports_np) {
> +		const char *node_name;
> +
> +		node_name = ofnode_get_name(node);
> +
> +		ret = device_bind_driver_to_node(dev, "am65_cpsw_nuss_port", node_name, node,
> +						 &port_dev);
> +		if (ret)
> +			dev_err(dev, "Failed to bind to %s node\n", node_name);
> +	}
> +
> +	return ret;
> +}
> +
>   static const struct udevice_id am65_cpsw_nuss_ids[] = {
>   	{ .compatible = "ti,am654-cpsw-nuss" },
>   	{ .compatible = "ti,j721e-cpsw-nuss" },
> @@ -809,6 +834,7 @@ U_BOOT_DRIVER(am65_cpsw_nuss) = {
>   	.name	= "am65_cpsw_nuss",
>   	.id	= UCLASS_MISC,
>   	.of_match = am65_cpsw_nuss_ids,
> +	.bind	= am65_cpsw_nuss_bind,
>   	.probe	= am65_cpsw_probe_nuss,
>   	.priv_auto = sizeof(struct am65_cpsw_common),
>   };

Re: [PATCH v4 01/21] net: ti: am65-cpsw-nuss: Define bind method for CPSW driver

[Siddharth Vadapalli]

On Fri, 2025-11-21 at 14:55 +0200, Wadim Egorov wrote:
> Hi,

Hello Wadim,
> 
> 
> On 7/31/25 10:59 AM, Chintan Vankar wrote:
> > CPSW driver is defined as UCLASS_MISC driver which needs to be probed
> > explicitly. Define bind method for CPSW driver to scan and bind
> > ethernet-ports with UCLASS_ETH driver which will eventually probe CPSW
> > driver and avoid probing CPSW driver explicitly.
> 
> 
> I just noticed a new error message with this patch.
> 
> On the phycore-am64x we can see that the 2nd cpsw port is getting probed 
> but fails. This is not really an Issue because we are not making use of 
> the 2nd port. But the error message does not look nice.
> 
> Why is this even probed? The soc-level device tree disables the ports 
> per default. And we do not activate it in our device tree.

Thank you for reporting this. I have just posted the fix at:
https://patch.msgid.link/20251121132156.3987128-1-s-vadapalli@ti.com

Regards,
Siddharth.

Re: [PATCH v4 14/21] arm: mach-k3: j722s: Update SoC autogenerated data to enable Ethernet boot

[Michael Walle]

[-- Attachment #1: Type: text/plain, Size: 10691 bytes --]

Hi,

On Thu Jul 31, 2025 at 9:59 AM CEST, Chintan Vankar wrote:
> Update dev-data and clk-data to include CPSW device which is required to
> enable Ethernet boot.
>

This breaks eMMC boot on our board:

U-Boot SPL 2026.01-rc2-00054-g32334645579c (Nov 21 2025 - 15:49:13 +0100)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.3--v11.01.03 (Fancy Rat)')
SPL initial stack usage: 17048 bytes
ti_power_domain_of_xlate: invalid dev-id: 57
ti_power_domain_of_xlate: invalid dev-id: 57
Trying to boot from eMMC (boot0)
ti_power_domain_of_xlate: invalid dev-id: 57
ti_power_domain_of_xlate: invalid dev-id: 57
spl: could not initialize mmc. error: -2
Error: -2
SPL: Unsupported Boot Device!
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

Not sure how this file was autogenerated but it removes ID 57.. see
more below.

Reverting this patch will make (at least) the r5 SPL work again.
There seems to be more issues with the u-boot proper, but I haven't
investigated that yet.

> Signed-off-by: Chintan Vankar <c-vankar@ti.com>
> ---
>
> Link to v3:
> https://lore.kernel.org/u-boot/20250225114903.2080616-13-c-vankar@ti.com/
>
> Changes from v3 to v4:
> - No changes.
>
>  arch/arm/mach-k3/r5/j722s/clk-data.c | 50 ++++++++++++++++++++++------
>  arch/arm/mach-k3/r5/j722s/dev-data.c | 34 +++++++++----------
>  2 files changed, 56 insertions(+), 28 deletions(-)
>
> diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c b/arch/arm/mach-k3/r5/j722s/clk-data.c
> index b4f27af333d..238d57d0aa0 100644
> --- a/arch/arm/mach-k3/r5/j722s/clk-data.c
> +++ b/arch/arm/mach-k3/r5/j722s/clk-data.c
> @@ -5,7 +5,7 @@
>   * This file is auto generated. Please do not hand edit and report any issues
>   * to Bryan Brattlof <bb@ti.com>.
>   *
> - * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
>   */
>  
>  #include <linux/clk-provider.h>
> @@ -57,9 +57,15 @@ static const char * const clkout0_ctrl_out0_parents[] = {
>  	"hsdiv4_16fft_main_2_hsdivout1_clk",
>  };
>  
> -static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
> -	"postdiv4_16ff_main_0_hsdivout5_clk",
> -	"hsdiv4_16fft_main_2_hsdivout2_clk",
> +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
> +	"postdiv4_16ff_main_2_hsdivout5_clk",
> +	"postdiv4_16ff_main_0_hsdivout6_clk",
> +	"board_0_cp_gemac_cpts0_rft_clk_out",
> +	NULL,
> +	"board_0_mcu_ext_refclk0_out",
> +	"board_0_ext_refclk1_out",
> +	NULL,
> +	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
>  };
>  
>  static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
> @@ -94,8 +100,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = {
>  	"board_0_cp_gemac_cpts0_rft_clk_out",
>  	"hsdiv4_16fft_main_1_hsdivout3_clk",
>  	"postdiv4_16ff_main_2_hsdivout6_clk",
> -	NULL,
> -	NULL,
> +	"cpsw_3guss_am67_main_0_cpts_genf0",
> +	"cpsw_3guss_am67_main_0_cpts_genf1",
>  	NULL,
>  	NULL,
>  	NULL,
> @@ -143,7 +149,12 @@ static const struct clk_data clk_list[] = {
>  	CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
>  	CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
>  	CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
> +	CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
> +	CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
>  	CLK_FIXED_RATE("board_0_tck_out", 0, 0),
> +	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0),
> +	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0),
> +	CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0),
>  	CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0),
>  	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
>  	CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
> @@ -194,7 +205,7 @@ static const struct clk_data clk_list[] = {
>  	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
>  	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
>  	CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
> -	CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
> +	CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
>  	CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
>  	CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
>  	CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
> @@ -209,6 +220,24 @@ static const struct clk_data clk_list[] = {
>  };
>  
>  static const struct dev_clk soc_dev_clk_data[] = {
> +	DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> +	DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
> +	DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
> +	DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
> +	DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
> +	DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
> +	DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
> +	DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> +	DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
> +	DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
> +	DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
> +	DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
> +	DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
> +	DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"),
> +	DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"),
> +	DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
> +	DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"),
> +	DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"),
>  	DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
>  	DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
>  	DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
> @@ -233,10 +262,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
>  	DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
>  	DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
>  	DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
> -	DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
> -	DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
> -	DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
> -	DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
> +	DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"),
> +	DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"),
>  	DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
>  	DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
>  	DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
> @@ -279,6 +306,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
>  	DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
>  	DEV_CLK(157, 74, "mshsi2c_main_0_porscl"),
>  	DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
> +	DEV_CLK(157, 140, "cpsw_3guss_am67_main_0_mdio_mdclk_o"),
>  	DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
>  	DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
>  	DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
> diff --git a/arch/arm/mach-k3/r5/j722s/dev-data.c b/arch/arm/mach-k3/r5/j722s/dev-data.c
> index 59176c98999..d6832266884 100644
> --- a/arch/arm/mach-k3/r5/j722s/dev-data.c
> +++ b/arch/arm/mach-k3/r5/j722s/dev-data.c
> @@ -5,7 +5,7 @@
>   * This file is auto generated. Please do not hand edit and report any issues
>   * to Bryan Brattlof <bb@ti.com>.
>   *
> - * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
> + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
>   */
>  
>  #include "k3-dev.h"
> @@ -23,16 +23,16 @@ static struct ti_pd soc_pd_list[] = {
>  
>  static struct ti_lpsc soc_lpsc_list[] = {
>  	[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
> -	[1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
> -	[2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
> -	[3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
> -	[4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
> -	[5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
> -	[6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
> -	[7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
> -	[8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[7]),
> +	[1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
> +	[2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
> +	[3] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
> +	[4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
> +	[5] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
> +	[6] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
> +	[7] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
> +	[8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[6]),
>  	[9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]),
> -	[10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]),
> +	[10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]),
>  	[11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]),
>  	[12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
>  };
> @@ -43,13 +43,13 @@ static struct ti_dev soc_dev_list[] = {
>  	PSC_DEV(61, &soc_lpsc_list[0]),
>  	PSC_DEV(178, &soc_lpsc_list[1]),
>  	PSC_DEV(179, &soc_lpsc_list[2]),
> -	PSC_DEV(57, &soc_lpsc_list[3]),

This seems to be relevant.

-michael

> -	PSC_DEV(58, &soc_lpsc_list[4]),
> -	PSC_DEV(161, &soc_lpsc_list[5]),
> -	PSC_DEV(75, &soc_lpsc_list[6]),
> -	PSC_DEV(36, &soc_lpsc_list[7]),
> -	PSC_DEV(102, &soc_lpsc_list[7]),
> -	PSC_DEV(146, &soc_lpsc_list[7]),
> +	PSC_DEV(58, &soc_lpsc_list[3]),
> +	PSC_DEV(161, &soc_lpsc_list[4]),
> +	PSC_DEV(75, &soc_lpsc_list[5]),
> +	PSC_DEV(36, &soc_lpsc_list[6]),
> +	PSC_DEV(102, &soc_lpsc_list[6]),
> +	PSC_DEV(146, &soc_lpsc_list[6]),
> +	PSC_DEV(13, &soc_lpsc_list[7]),
>  	PSC_DEV(166, &soc_lpsc_list[8]),
>  	PSC_DEV(135, &soc_lpsc_list[9]),
>  	PSC_DEV(170, &soc_lpsc_list[10]),


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 297 bytes --]