* [PATCH v2 00/30] rockchip: Add initial support for RK3528
@ 2025-04-07 22:46 Jonas Karlman
2025-04-07 22:46 ` [PATCH v2 01/30] dt-bindings: clock: Document clock and reset unit of RK3528 Jonas Karlman
` (29 more replies)
0 siblings, 30 replies; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman
This series add initial support for the Rockchip RK3528 SoC.
Clk, pinctrl and rng drivers have been imported from vendor U-Boot with
minor adjustments and fixes.
Upstream DT for RK3528 is now more complete and this series only add a
few missing nodes to -u-boot.dtsi files to have a bootable system.
Changes in v2:
- Pick device tree commits from devicetree-rebasing v6.15-rc1-dts
- Update clk and reset driver to work with mainline Linux dt-bindings
- Add RK3528 support in otp, saradc, inno-usb2 and dwc_eth_qos drivers
Features tested on a ArmSoM Sige1:
- SD-card boot
- eMMC boot
Features tested on a FriendlyElec NanoPi Zero2:
- SD-card boot
- eMMC boot
Features tested on a Radxa E20C v1.104:
- SD-card boot
- eMMC boot
Features tested on a Radxa ROCK 2A v1.202:
- SD-card boot
Boot log on a Radxa ROCK 2A:
DDR 44ec2e0a51 huan.he 24/07/12-14:38:48,fwver: v1.10
[...]
out
U-Boot SPL 2025.04-rc5 (Apr 07 2025 - 21:08:38 +0000)
Trying to boot from MMC2
## Checking hash(es) for config config-1 ... OK
## Checking hash(es) for Image atf-1 ... sha256+ OK
## Checking hash(es) for Image u-boot ... sha256+ OK
## Checking hash(es) for Image fdt-1 ... sha256+ OK
## Checking hash(es) for Image atf-2 ... sha256+ OK
## Checking hash(es) for Image atf-3 ... sha256+ OK
INFO: Preloader serial: 0
NOTICE: BL31: v2.3():v2.3-857-g059b3c586:derrick.huang, fwver: v1.18
NOTICE: BL31: Built : 17:43:24, Nov 18 2024
INFO: rk_otp_init finish!
INFO: ARM GICv2 driver initialized
INFO: nonboot_cpus_off: clst_st=0xc0e, core_st=0xe1e0 boot_cpu=0
INFO: dfs DDR fsp_param[0].freq_mhz= 1056MHz
INFO: dfs DDR fsp_param[1].freq_mhz= 324MHz
INFO: dfs DDR fsp_param[2].freq_mhz= 528MHz
INFO: dfs DDR fsp_param[3].freq_mhz= 780MHz
INFO: idle_st=0x0, pd_st=0x0
INFO: Using opteed sec cpu_context!
INFO: boot cpu mask: 1
INFO: rk_otp_init finish!
INFO: RK3528 SoC (0x101)
INFO: BL31: Initializing runtime services
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
ERROR: Error initializing runtime service opteed_fast
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x800000
INFO: SPSR = 0x3c9
U-Boot 2025.04-rc5 (Apr 07 2025 - 21:08:38 +0000)
Model: Generic RK3528
SoC: RK3528A
DRAM: 4 GiB (effective 3.9 GiB)
Core: 130 devices, 20 uclasses, devicetree: separate
MMC: mmc@ffbf0000: 0, mmc@ffc30000: 1
Loading Environment from nowhere... OK
In: serial@ff9f0000
Out: serial@ff9f0000
Err: serial@ff9f0000
Hit any key to stop autoboot: 0
=>
This series depends on the following series:
- rockchip: ROCKCHIP_COMMON_STACK_ADDR improvements
- rockchip: Update rng compatible for RK356x and RK3588
Chukun Pan (2):
arm64: dts: rockchip: Add rk3528 QoS register node
arm64: dts: rockchip: enable SCMI clk for RK3528 SoC
Jonas Karlman (21):
arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528
arm64: dts: rockchip: Add SARADC node for RK3528
arm64: dts: rockchip: Add SDHCI controller for RK3528
arm64: dts: rockchip: Add uart0 pinctrl to Radxa E20C
arm64: dts: rockchip: Add leds node to Radxa E20C
arm64: dts: rockchip: Add user button to Radxa E20C
arm64: dts: rockchip: Add maskrom button to Radxa E20C
arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C
ram: rockchip: Add basic support for RK3528
arm: dts: rockchip: Add rk3528-u-boot.dtsi
arch: arm: rockchip: Add initial support for RK3528
mmc: rockchip_sdhci: Extend variant configuration
mmc: rockchip_sdhci: Add initial support for RK3528
mmc: rockchip_sdhci: Gate clock for glitch free phase switching
rockchip: otp: Add support for RK3528
adc: rockchip-saradc: Add support for RK3528
phy: rockchip-inno-usb2: Add support for clkout_ctl_phy
phy: rockchip-inno-usb2: Add support for RK3528
net: dwc_eth_qos_rockchip: Add support for RK3528
board: rockchip: Add minimal generic RK3528 board
board: rockchip: Add Radxa E20C
Joseph Chen (1):
clk: rockchip: Add support for RK3528
Lin Jinhan (1):
rng: rockchip: Add support for rkrng variant
Steven Liu (1):
pinctrl: rockchip: Add support for RK3528
Yao Zi (3):
dt-bindings: clock: Document clock and reset unit of RK3528
arm64: dts: rockchip: Add clock generators for RK3528 SoC
arm64: dts: rockchip: Add UART clocks for RK3528 SoC
Yifeng Zhao (1):
rockchip: mkimage: Add support for RK3528
arch/arm/dts/rk3528-generic-u-boot.dtsi | 12 +
arch/arm/dts/rk3528-generic.dts | 31 +
arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi | 12 +
arch/arm/dts/rk3528-u-boot.dtsi | 148 ++
arch/arm/include/asm/arch-rk3528/boot0.h | 9 +
arch/arm/include/asm/arch-rk3528/gpio.h | 9 +
arch/arm/include/asm/arch-rockchip/clock.h | 17 +
.../include/asm/arch-rockchip/cru_rk3528.h | 388 ++++
arch/arm/mach-rockchip/Kconfig | 51 +
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3528/Kconfig | 15 +
arch/arm/mach-rockchip/rk3528/MAINTAINERS | 11 +
arch/arm/mach-rockchip/rk3528/Makefile | 5 +
arch/arm/mach-rockchip/rk3528/clk_rk3528.c | 16 +
arch/arm/mach-rockchip/rk3528/rk3528.c | 137 ++
arch/arm/mach-rockchip/rk3528/syscon_rk3528.c | 19 +
arch/arm/mach-rockchip/sdram.c | 3 +-
configs/generic-rk3528_defconfig | 40 +
configs/radxa-e20c-rk3528_defconfig | 56 +
doc/board/rockchip/rockchip.rst | 13 +
drivers/adc/rockchip-saradc.c | 10 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk_pll.c | 23 +-
drivers/clk/rockchip/clk_rk3528.c | 1754 +++++++++++++++++
drivers/misc/rockchip-otp.c | 4 +
drivers/mmc/rockchip_sdhci.c | 39 +-
drivers/net/dwc_eth_qos.c | 4 +
drivers/net/dwc_eth_qos_rockchip.c | 138 ++
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 63 +-
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3528.c | 273 +++
drivers/ram/rockchip/Makefile | 1 +
drivers/ram/rockchip/sdram_rk3528.c | 33 +
drivers/reset/Makefile | 2 +-
drivers/reset/rst-rk3528.c | 302 +++
drivers/rng/rockchip_rng.c | 73 +
drivers/usb/gadget/Kconfig | 1 +
.../Bindings/clock/rockchip,rk3528-cru.yaml | 64 +
.../dt-bindings/clock/rockchip,rk3528-cru.h | 453 +++++
.../dt-bindings/reset/rockchip,rk3528-cru.h | 241 +++
.../src/arm64/rockchip/rk3528-pinctrl.dtsi | 1397 +++++++++++++
.../src/arm64/rockchip/rk3528-radxa-e20c.dts | 133 ++
dts/upstream/src/arm64/rockchip/rk3528.dtsi | 378 +++-
include/configs/rk3528_common.h | 38 +
tools/rkcommon.c | 1 +
45 files changed, 6398 insertions(+), 22 deletions(-)
create mode 100644 arch/arm/dts/rk3528-generic-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3528-generic.dts
create mode 100644 arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3528-u-boot.dtsi
create mode 100644 arch/arm/include/asm/arch-rk3528/boot0.h
create mode 100644 arch/arm/include/asm/arch-rk3528/gpio.h
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3528.h
create mode 100644 arch/arm/mach-rockchip/rk3528/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3528/MAINTAINERS
create mode 100644 arch/arm/mach-rockchip/rk3528/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3528/clk_rk3528.c
create mode 100644 arch/arm/mach-rockchip/rk3528/rk3528.c
create mode 100644 arch/arm/mach-rockchip/rk3528/syscon_rk3528.c
create mode 100644 configs/generic-rk3528_defconfig
create mode 100644 configs/radxa-e20c-rk3528_defconfig
create mode 100644 drivers/clk/rockchip/clk_rk3528.c
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3528.c
create mode 100644 drivers/ram/rockchip/sdram_rk3528.c
create mode 100644 drivers/reset/rst-rk3528.c
create mode 100644 dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml
create mode 100644 dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h
create mode 100644 dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h
create mode 100644 dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi
create mode 100644 include/configs/rk3528_common.h
--
2.49.0
^ permalink raw reply [flat|nested] 61+ messages in thread
* [PATCH v2 01/30] dt-bindings: clock: Document clock and reset unit of RK3528
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:21 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 02/30] arm64: dts: rockchip: Add clock generators for RK3528 SoC Jonas Karlman
` (28 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg,
Yao Zi
Cc: Chukun Pan, u-boot, Jonas Karlman, Heiko Stuebner
From: Yao Zi <ziyao@disroot.org>
There are two types of clocks in RK3528 SoC, CRU-managed and
SCMI-managed. Independent IDs are assigned to them.
For the reset part, differing from previous Rockchip SoCs and
downstream bindings which embeds register offsets into the IDs, gapless
numbers starting from zero are used.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250217061142.38480-6-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: e0c0a97bc308f71b0934e3637ac545ce65195df0 ]
(cherry picked from commit 8768d063e732e64892e4d1d09aa583d1394c8388)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
.../Bindings/clock/rockchip,rk3528-cru.yaml | 64 +++
.../dt-bindings/clock/rockchip,rk3528-cru.h | 453 ++++++++++++++++++
.../dt-bindings/reset/rockchip,rk3528-cru.h | 241 ++++++++++
3 files changed, 758 insertions(+)
create mode 100644 dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml
create mode 100644 dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h
create mode 100644 dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h
diff --git a/dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml b/dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml
new file mode 100644
index 000000000000..5a3ec902351c
--- /dev/null
+++ b/dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3528 Clock and Reset Controller
+
+maintainers:
+ - Yao Zi <ziyao@disroot.org>
+
+description: |
+ The RK3528 clock controller generates the clock and also implements a reset
+ controller for SoC peripherals. For example, it provides SCLK_UART0 and
+ PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART
+ module.
+ Each clock is assigned an identifier, consumer nodes can use it to specify
+ the clock. All available clock and reset IDs are defined in dt-binding
+ headers.
+
+properties:
+ compatible:
+ const: rockchip,rk3528-cru
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: External 24MHz oscillator clock
+ - description: >
+ 50MHz clock generated by PHY module, for generating GMAC0 clocks only.
+
+ clock-names:
+ items:
+ - const: xin24m
+ - const: gmac0
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@ff4a0000 {
+ compatible = "rockchip,rk3528-cru";
+ reg = <0xff4a0000 0x30000>;
+ clocks = <&xin24m>, <&gmac0_clk>;
+ clock-names = "xin24m", "gmac0";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h b/dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h
new file mode 100644
index 000000000000..55a448f5ed6d
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h
@@ -0,0 +1,453 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
+
+/* cru-clocks indices */
+#define PLL_APLL 0
+#define PLL_CPLL 1
+#define PLL_GPLL 2
+#define PLL_PPLL 3
+#define PLL_DPLL 4
+#define ARMCLK 5
+#define XIN_OSC0_HALF 6
+#define CLK_MATRIX_50M_SRC 7
+#define CLK_MATRIX_100M_SRC 8
+#define CLK_MATRIX_150M_SRC 9
+#define CLK_MATRIX_200M_SRC 10
+#define CLK_MATRIX_250M_SRC 11
+#define CLK_MATRIX_300M_SRC 12
+#define CLK_MATRIX_339M_SRC 13
+#define CLK_MATRIX_400M_SRC 14
+#define CLK_MATRIX_500M_SRC 15
+#define CLK_MATRIX_600M_SRC 16
+#define CLK_UART0_SRC 17
+#define CLK_UART0_FRAC 18
+#define SCLK_UART0 19
+#define CLK_UART1_SRC 20
+#define CLK_UART1_FRAC 21
+#define SCLK_UART1 22
+#define CLK_UART2_SRC 23
+#define CLK_UART2_FRAC 24
+#define SCLK_UART2 25
+#define CLK_UART3_SRC 26
+#define CLK_UART3_FRAC 27
+#define SCLK_UART3 28
+#define CLK_UART4_SRC 29
+#define CLK_UART4_FRAC 30
+#define SCLK_UART4 31
+#define CLK_UART5_SRC 32
+#define CLK_UART5_FRAC 33
+#define SCLK_UART5 34
+#define CLK_UART6_SRC 35
+#define CLK_UART6_FRAC 36
+#define SCLK_UART6 37
+#define CLK_UART7_SRC 38
+#define CLK_UART7_FRAC 39
+#define SCLK_UART7 40
+#define CLK_I2S0_2CH_SRC 41
+#define CLK_I2S0_2CH_FRAC 42
+#define MCLK_I2S0_2CH_SAI_SRC 43
+#define CLK_I2S3_8CH_SRC 44
+#define CLK_I2S3_8CH_FRAC 45
+#define MCLK_I2S3_8CH_SAI_SRC 46
+#define CLK_I2S1_8CH_SRC 47
+#define CLK_I2S1_8CH_FRAC 48
+#define MCLK_I2S1_8CH_SAI_SRC 49
+#define CLK_I2S2_2CH_SRC 50
+#define CLK_I2S2_2CH_FRAC 51
+#define MCLK_I2S2_2CH_SAI_SRC 52
+#define CLK_SPDIF_SRC 53
+#define CLK_SPDIF_FRAC 54
+#define MCLK_SPDIF_SRC 55
+#define DCLK_VOP_SRC0 56
+#define DCLK_VOP_SRC1 57
+#define CLK_HSM 58
+#define CLK_CORE_SRC_ACS 59
+#define CLK_CORE_SRC_PVTMUX 60
+#define CLK_CORE_SRC 61
+#define CLK_CORE 62
+#define ACLK_M_CORE_BIU 63
+#define CLK_CORE_PVTPLL_SRC 64
+#define PCLK_DBG 65
+#define SWCLKTCK 66
+#define CLK_SCANHS_CORE 67
+#define CLK_SCANHS_ACLKM_CORE 68
+#define CLK_SCANHS_PCLK_DBG 69
+#define CLK_SCANHS_PCLK_CPU_BIU 70
+#define PCLK_CPU_ROOT 71
+#define PCLK_CORE_GRF 72
+#define PCLK_DAPLITE_BIU 73
+#define PCLK_CPU_BIU 74
+#define CLK_REF_PVTPLL_CORE 75
+#define ACLK_BUS_VOPGL_ROOT 76
+#define ACLK_BUS_VOPGL_BIU 77
+#define ACLK_BUS_H_ROOT 78
+#define ACLK_BUS_H_BIU 79
+#define ACLK_BUS_ROOT 80
+#define HCLK_BUS_ROOT 81
+#define PCLK_BUS_ROOT 82
+#define ACLK_BUS_M_ROOT 83
+#define ACLK_SYSMEM_BIU 84
+#define CLK_TIMER_ROOT 85
+#define ACLK_BUS_BIU 86
+#define HCLK_BUS_BIU 87
+#define PCLK_BUS_BIU 88
+#define PCLK_DFT2APB 89
+#define PCLK_BUS_GRF 90
+#define ACLK_BUS_M_BIU 91
+#define ACLK_GIC 92
+#define ACLK_SPINLOCK 93
+#define ACLK_DMAC 94
+#define PCLK_TIMER 95
+#define CLK_TIMER0 96
+#define CLK_TIMER1 97
+#define CLK_TIMER2 98
+#define CLK_TIMER3 99
+#define CLK_TIMER4 100
+#define CLK_TIMER5 101
+#define PCLK_JDBCK_DAP 102
+#define CLK_JDBCK_DAP 103
+#define PCLK_WDT_NS 104
+#define TCLK_WDT_NS 105
+#define HCLK_TRNG_NS 106
+#define PCLK_UART0 107
+#define PCLK_DMA2DDR 108
+#define ACLK_DMA2DDR 109
+#define PCLK_PWM0 110
+#define CLK_PWM0 111
+#define CLK_CAPTURE_PWM0 112
+#define PCLK_PWM1 113
+#define CLK_PWM1 114
+#define CLK_CAPTURE_PWM1 115
+#define PCLK_SCR 116
+#define ACLK_DCF 117
+#define PCLK_INTMUX 118
+#define CLK_PPLL_I 119
+#define CLK_PPLL_MUX 120
+#define CLK_PPLL_100M_MATRIX 121
+#define CLK_PPLL_50M_MATRIX 122
+#define CLK_REF_PCIE_INNER_PHY 123
+#define CLK_REF_PCIE_100M_PHY 124
+#define ACLK_VPU_L_ROOT 125
+#define CLK_GMAC1_VPU_25M 126
+#define CLK_PPLL_125M_MATRIX 127
+#define ACLK_VPU_ROOT 128
+#define HCLK_VPU_ROOT 129
+#define PCLK_VPU_ROOT 130
+#define ACLK_VPU_BIU 131
+#define HCLK_VPU_BIU 132
+#define PCLK_VPU_BIU 133
+#define ACLK_VPU 134
+#define HCLK_VPU 135
+#define PCLK_CRU_PCIE 136
+#define PCLK_VPU_GRF 137
+#define HCLK_SFC 138
+#define SCLK_SFC 139
+#define CCLK_SRC_EMMC 140
+#define HCLK_EMMC 141
+#define ACLK_EMMC 142
+#define BCLK_EMMC 143
+#define TCLK_EMMC 144
+#define PCLK_GPIO1 145
+#define DBCLK_GPIO1 146
+#define ACLK_VPU_L_BIU 147
+#define PCLK_VPU_IOC 148
+#define HCLK_SAI_I2S0 149
+#define MCLK_SAI_I2S0 150
+#define HCLK_SAI_I2S2 151
+#define MCLK_SAI_I2S2 152
+#define PCLK_ACODEC 153
+#define MCLK_ACODEC_TX 154
+#define PCLK_GPIO3 155
+#define DBCLK_GPIO3 156
+#define PCLK_SPI1 157
+#define CLK_SPI1 158
+#define SCLK_IN_SPI1 159
+#define PCLK_UART2 160
+#define PCLK_UART5 161
+#define PCLK_UART6 162
+#define PCLK_UART7 163
+#define PCLK_I2C3 164
+#define CLK_I2C3 165
+#define PCLK_I2C5 166
+#define CLK_I2C5 167
+#define PCLK_I2C6 168
+#define CLK_I2C6 169
+#define ACLK_MAC_VPU 170
+#define PCLK_MAC_VPU 171
+#define CLK_GMAC1_RMII_VPU 172
+#define CLK_GMAC1_SRC_VPU 173
+#define PCLK_PCIE 174
+#define CLK_PCIE_AUX 175
+#define ACLK_PCIE 176
+#define HCLK_PCIE_SLV 177
+#define HCLK_PCIE_DBI 178
+#define PCLK_PCIE_PHY 179
+#define PCLK_PIPE_GRF 180
+#define CLK_PIPE_USB3OTG_COMBO 181
+#define CLK_UTMI_USB3OTG 182
+#define CLK_PCIE_PIPE_PHY 183
+#define CCLK_SRC_SDIO0 184
+#define HCLK_SDIO0 185
+#define CCLK_SRC_SDIO1 186
+#define HCLK_SDIO1 187
+#define CLK_TS_0 188
+#define CLK_TS_1 189
+#define PCLK_CAN2 190
+#define CLK_CAN2 191
+#define PCLK_CAN3 192
+#define CLK_CAN3 193
+#define PCLK_SARADC 194
+#define CLK_SARADC 195
+#define PCLK_TSADC 196
+#define CLK_TSADC 197
+#define CLK_TSADC_TSEN 198
+#define ACLK_USB3OTG 199
+#define CLK_REF_USB3OTG 200
+#define CLK_SUSPEND_USB3OTG 201
+#define ACLK_GPU_ROOT 202
+#define PCLK_GPU_ROOT 203
+#define ACLK_GPU_BIU 204
+#define PCLK_GPU_BIU 205
+#define ACLK_GPU 206
+#define CLK_GPU_PVTPLL_SRC 207
+#define ACLK_GPU_MALI 208
+#define HCLK_RKVENC_ROOT 209
+#define ACLK_RKVENC_ROOT 210
+#define PCLK_RKVENC_ROOT 211
+#define HCLK_RKVENC_BIU 212
+#define ACLK_RKVENC_BIU 213
+#define PCLK_RKVENC_BIU 214
+#define HCLK_RKVENC 215
+#define ACLK_RKVENC 216
+#define CLK_CORE_RKVENC 217
+#define HCLK_SAI_I2S1 218
+#define MCLK_SAI_I2S1 219
+#define PCLK_I2C1 220
+#define CLK_I2C1 221
+#define PCLK_I2C0 222
+#define CLK_I2C0 223
+#define CLK_UART_JTAG 224
+#define PCLK_SPI0 225
+#define CLK_SPI0 226
+#define SCLK_IN_SPI0 227
+#define PCLK_GPIO4 228
+#define DBCLK_GPIO4 229
+#define PCLK_RKVENC_IOC 230
+#define HCLK_SPDIF 231
+#define MCLK_SPDIF 232
+#define HCLK_PDM 233
+#define MCLK_PDM 234
+#define PCLK_UART1 235
+#define PCLK_UART3 236
+#define PCLK_RKVENC_GRF 237
+#define PCLK_CAN0 238
+#define CLK_CAN0 239
+#define PCLK_CAN1 240
+#define CLK_CAN1 241
+#define ACLK_VO_ROOT 242
+#define HCLK_VO_ROOT 243
+#define PCLK_VO_ROOT 244
+#define ACLK_VO_BIU 245
+#define HCLK_VO_BIU 246
+#define PCLK_VO_BIU 247
+#define HCLK_RGA2E 248
+#define ACLK_RGA2E 249
+#define CLK_CORE_RGA2E 250
+#define HCLK_VDPP 251
+#define ACLK_VDPP 252
+#define CLK_CORE_VDPP 253
+#define PCLK_VO_GRF 254
+#define PCLK_CRU 255
+#define ACLK_VOP_ROOT 256
+#define ACLK_VOP_BIU 257
+#define HCLK_VOP 258
+#define DCLK_VOP0 259
+#define DCLK_VOP1 260
+#define ACLK_VOP 261
+#define PCLK_HDMI 262
+#define CLK_SFR_HDMI 263
+#define CLK_CEC_HDMI 264
+#define CLK_SPDIF_HDMI 265
+#define CLK_HDMIPHY_TMDSSRC 266
+#define CLK_HDMIPHY_PREP 267
+#define PCLK_HDMIPHY 268
+#define HCLK_HDCP_KEY 269
+#define ACLK_HDCP 270
+#define HCLK_HDCP 271
+#define PCLK_HDCP 272
+#define HCLK_CVBS 273
+#define DCLK_CVBS 274
+#define DCLK_4X_CVBS 275
+#define ACLK_JPEG_DECODER 276
+#define HCLK_JPEG_DECODER 277
+#define ACLK_VO_L_ROOT 278
+#define ACLK_VO_L_BIU 279
+#define ACLK_MAC_VO 280
+#define PCLK_MAC_VO 281
+#define CLK_GMAC0_SRC 282
+#define CLK_GMAC0_RMII_50M 283
+#define CLK_GMAC0_TX 284
+#define CLK_GMAC0_RX 285
+#define ACLK_JPEG_ROOT 286
+#define ACLK_JPEG_BIU 287
+#define HCLK_SAI_I2S3 288
+#define MCLK_SAI_I2S3 289
+#define CLK_MACPHY 290
+#define PCLK_VCDCPHY 291
+#define PCLK_GPIO2 292
+#define DBCLK_GPIO2 293
+#define PCLK_VO_IOC 294
+#define CCLK_SRC_SDMMC0 295
+#define HCLK_SDMMC0 296
+#define PCLK_OTPC_NS 297
+#define CLK_SBPI_OTPC_NS 298
+#define CLK_USER_OTPC_NS 299
+#define CLK_HDMIHDP0 300
+#define HCLK_USBHOST 301
+#define HCLK_USBHOST_ARB 302
+#define CLK_USBHOST_OHCI 303
+#define CLK_USBHOST_UTMI 304
+#define PCLK_UART4 305
+#define PCLK_I2C4 306
+#define CLK_I2C4 307
+#define PCLK_I2C7 308
+#define CLK_I2C7 309
+#define PCLK_USBPHY 310
+#define CLK_REF_USBPHY 311
+#define HCLK_RKVDEC_ROOT 312
+#define ACLK_RKVDEC_ROOT_NDFT 313
+#define PCLK_DDRPHY_CRU 314
+#define HCLK_RKVDEC_BIU 315
+#define ACLK_RKVDEC_BIU 316
+#define ACLK_RKVDEC 317
+#define HCLK_RKVDEC 318
+#define CLK_HEVC_CA_RKVDEC 319
+#define ACLK_RKVDEC_PVTMUX_ROOT 320
+#define CLK_RKVDEC_PVTPLL_SRC 321
+#define PCLK_DDR_ROOT 322
+#define PCLK_DDR_BIU 323
+#define PCLK_DDRC 324
+#define PCLK_DDRMON 325
+#define CLK_TIMER_DDRMON 326
+#define PCLK_MSCH_BIU 327
+#define PCLK_DDR_GRF 328
+#define PCLK_DDR_HWLP 329
+#define PCLK_DDRPHY 330
+#define CLK_MSCH_BIU 331
+#define ACLK_DDR_UPCTL 332
+#define CLK_DDR_UPCTL 333
+#define CLK_DDRMON 334
+#define ACLK_DDR_SCRAMBLE 335
+#define ACLK_SPLIT 336
+#define CLK_DDRC_SRC 337
+#define CLK_DDR_PHY 338
+#define PCLK_OTPC_S 339
+#define CLK_SBPI_OTPC_S 340
+#define CLK_USER_OTPC_S 341
+#define PCLK_KEYREADER 342
+#define PCLK_BUS_SGRF 343
+#define PCLK_STIMER 344
+#define CLK_STIMER0 345
+#define CLK_STIMER1 346
+#define PCLK_WDT_S 347
+#define TCLK_WDT_S 348
+#define HCLK_TRNG_S 349
+#define HCLK_BOOTROM 350
+#define PCLK_DCF 351
+#define ACLK_SYSMEM 352
+#define HCLK_TSP 353
+#define ACLK_TSP 354
+#define CLK_CORE_TSP 355
+#define CLK_OTPC_ARB 356
+#define PCLK_OTP_MASK 357
+#define CLK_PMC_OTP 358
+#define PCLK_PMU_ROOT 359
+#define HCLK_PMU_ROOT 360
+#define PCLK_I2C2 361
+#define CLK_I2C2 362
+#define HCLK_PMU_BIU 363
+#define PCLK_PMU_BIU 364
+#define FCLK_MCU 365
+#define RTC_CLK_MCU 366
+#define PCLK_OSCCHK 367
+#define CLK_PMU_MCU_JTAG 368
+#define PCLK_PMU 369
+#define PCLK_GPIO0 370
+#define DBCLK_GPIO0 371
+#define XIN_OSC0_DIV 372
+#define CLK_DEEPSLOW 373
+#define CLK_DDR_FAIL_SAFE 374
+#define PCLK_PMU_HP_TIMER 375
+#define CLK_PMU_HP_TIMER 376
+#define CLK_PMU_32K_HP_TIMER 377
+#define PCLK_PMU_IOC 378
+#define PCLK_PMU_CRU 379
+#define PCLK_PMU_GRF 380
+#define PCLK_PMU_WDT 381
+#define TCLK_PMU_WDT 382
+#define PCLK_PMU_MAILBOX 383
+#define PCLK_SCRKEYGEN 384
+#define CLK_SCRKEYGEN 385
+#define CLK_PVTM_OSCCHK 386
+#define CLK_REFOUT 387
+#define CLK_PVTM_PMU 388
+#define PCLK_PVTM_PMU 389
+#define PCLK_PMU_SGRF 390
+#define HCLK_PMU_SRAM 391
+#define CLK_UART0 392
+#define CLK_UART1 393
+#define CLK_UART2 394
+#define CLK_UART3 395
+#define CLK_UART4 396
+#define CLK_UART5 397
+#define CLK_UART6 398
+#define CLK_UART7 399
+#define MCLK_I2S0_2CH_SAI_SRC_PRE 400
+#define MCLK_I2S1_8CH_SAI_SRC_PRE 401
+#define MCLK_I2S2_2CH_SAI_SRC_PRE 402
+#define MCLK_I2S3_8CH_SAI_SRC_PRE 403
+#define MCLK_SDPDIF_SRC_PRE 404
+
+/* scmi-clocks indices */
+#define SCMI_PCLK_KEYREADER 0
+#define SCMI_HCLK_KLAD 1
+#define SCMI_PCLK_KLAD 2
+#define SCMI_HCLK_TRNG_S 3
+#define SCMI_HCLK_CRYPTO_S 4
+#define SCMI_PCLK_WDT_S 5
+#define SCMI_TCLK_WDT_S 6
+#define SCMI_PCLK_STIMER 7
+#define SCMI_CLK_STIMER0 8
+#define SCMI_CLK_STIMER1 9
+#define SCMI_PCLK_OTP_MASK 10
+#define SCMI_PCLK_OTPC_S 11
+#define SCMI_CLK_SBPI_OTPC_S 12
+#define SCMI_CLK_USER_OTPC_S 13
+#define SCMI_CLK_PMC_OTP 14
+#define SCMI_CLK_OTPC_ARB 15
+#define SCMI_CLK_CORE_TSP 16
+#define SCMI_ACLK_TSP 17
+#define SCMI_HCLK_TSP 18
+#define SCMI_PCLK_DCF 19
+#define SCMI_CLK_DDR 20
+#define SCMI_CLK_CPU 21
+#define SCMI_CLK_GPU 22
+#define SCMI_CORE_CRYPTO 23
+#define SCMI_ACLK_CRYPTO 24
+#define SCMI_PKA_CRYPTO 25
+#define SCMI_HCLK_CRYPTO 26
+#define SCMI_CORE_CRYPTO_S 27
+#define SCMI_ACLK_CRYPTO_S 28
+#define SCMI_PKA_CRYPTO_S 29
+#define SCMI_CORE_KLAD 30
+#define SCMI_ACLK_KLAD 31
+#define SCMI_HCLK_TRNG 32
+
+#endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
diff --git a/dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h b/dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h
new file mode 100644
index 000000000000..6b024c5f2e1c
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h
@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
+#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
+
+#define SRST_CORE0_PO 0
+#define SRST_CORE1_PO 1
+#define SRST_CORE2_PO 2
+#define SRST_CORE3_PO 3
+#define SRST_CORE0 4
+#define SRST_CORE1 5
+#define SRST_CORE2 6
+#define SRST_CORE3 7
+#define SRST_NL2 8
+#define SRST_CORE_BIU 9
+#define SRST_CORE_CRYPTO 10
+#define SRST_P_DBG 11
+#define SRST_POT_DBG 12
+#define SRST_NT_DBG 13
+#define SRST_P_CORE_GRF 14
+#define SRST_P_DAPLITE_BIU 15
+#define SRST_P_CPU_BIU 16
+#define SRST_REF_PVTPLL_CORE 17
+#define SRST_A_BUS_VOPGL_BIU 18
+#define SRST_A_BUS_H_BIU 19
+#define SRST_A_SYSMEM_BIU 20
+#define SRST_A_BUS_BIU 21
+#define SRST_H_BUS_BIU 22
+#define SRST_P_BUS_BIU 23
+#define SRST_P_DFT2APB 24
+#define SRST_P_BUS_GRF 25
+#define SRST_A_BUS_M_BIU 26
+#define SRST_A_GIC 27
+#define SRST_A_SPINLOCK 28
+#define SRST_A_DMAC 29
+#define SRST_P_TIMER 30
+#define SRST_TIMER0 31
+#define SRST_TIMER1 32
+#define SRST_TIMER2 33
+#define SRST_TIMER3 34
+#define SRST_TIMER4 35
+#define SRST_TIMER5 36
+#define SRST_P_JDBCK_DAP 37
+#define SRST_JDBCK_DAP 38
+#define SRST_P_WDT_NS 39
+#define SRST_T_WDT_NS 40
+#define SRST_H_TRNG_NS 41
+#define SRST_P_UART0 42
+#define SRST_S_UART0 43
+#define SRST_PKA_CRYPTO 44
+#define SRST_A_CRYPTO 45
+#define SRST_H_CRYPTO 46
+#define SRST_P_DMA2DDR 47
+#define SRST_A_DMA2DDR 48
+#define SRST_P_PWM0 49
+#define SRST_PWM0 50
+#define SRST_P_PWM1 51
+#define SRST_PWM1 52
+#define SRST_P_SCR 53
+#define SRST_A_DCF 54
+#define SRST_P_INTMUX 55
+#define SRST_A_VPU_BIU 56
+#define SRST_H_VPU_BIU 57
+#define SRST_P_VPU_BIU 58
+#define SRST_A_VPU 59
+#define SRST_H_VPU 60
+#define SRST_P_CRU_PCIE 61
+#define SRST_P_VPU_GRF 62
+#define SRST_H_SFC 63
+#define SRST_S_SFC 64
+#define SRST_C_EMMC 65
+#define SRST_H_EMMC 66
+#define SRST_A_EMMC 67
+#define SRST_B_EMMC 68
+#define SRST_T_EMMC 69
+#define SRST_P_GPIO1 70
+#define SRST_DB_GPIO1 71
+#define SRST_A_VPU_L_BIU 72
+#define SRST_P_VPU_IOC 73
+#define SRST_H_SAI_I2S0 74
+#define SRST_M_SAI_I2S0 75
+#define SRST_H_SAI_I2S2 76
+#define SRST_M_SAI_I2S2 77
+#define SRST_P_ACODEC 78
+#define SRST_P_GPIO3 79
+#define SRST_DB_GPIO3 80
+#define SRST_P_SPI1 81
+#define SRST_SPI1 82
+#define SRST_P_UART2 83
+#define SRST_S_UART2 84
+#define SRST_P_UART5 85
+#define SRST_S_UART5 86
+#define SRST_P_UART6 87
+#define SRST_S_UART6 88
+#define SRST_P_UART7 89
+#define SRST_S_UART7 90
+#define SRST_P_I2C3 91
+#define SRST_I2C3 92
+#define SRST_P_I2C5 93
+#define SRST_I2C5 94
+#define SRST_P_I2C6 95
+#define SRST_I2C6 96
+#define SRST_A_MAC 97
+#define SRST_P_PCIE 98
+#define SRST_PCIE_PIPE_PHY 99
+#define SRST_PCIE_POWER_UP 100
+#define SRST_P_PCIE_PHY 101
+#define SRST_P_PIPE_GRF 102
+#define SRST_H_SDIO0 103
+#define SRST_H_SDIO1 104
+#define SRST_TS_0 105
+#define SRST_TS_1 106
+#define SRST_P_CAN2 107
+#define SRST_CAN2 108
+#define SRST_P_CAN3 109
+#define SRST_CAN3 110
+#define SRST_P_SARADC 111
+#define SRST_SARADC 112
+#define SRST_SARADC_PHY 113
+#define SRST_P_TSADC 114
+#define SRST_TSADC 115
+#define SRST_A_USB3OTG 116
+#define SRST_A_GPU_BIU 117
+#define SRST_P_GPU_BIU 118
+#define SRST_A_GPU 119
+#define SRST_REF_PVTPLL_GPU 120
+#define SRST_H_RKVENC_BIU 121
+#define SRST_A_RKVENC_BIU 122
+#define SRST_P_RKVENC_BIU 123
+#define SRST_H_RKVENC 124
+#define SRST_A_RKVENC 125
+#define SRST_CORE_RKVENC 126
+#define SRST_H_SAI_I2S1 127
+#define SRST_M_SAI_I2S1 128
+#define SRST_P_I2C1 129
+#define SRST_I2C1 130
+#define SRST_P_I2C0 131
+#define SRST_I2C0 132
+#define SRST_P_SPI0 133
+#define SRST_SPI0 134
+#define SRST_P_GPIO4 135
+#define SRST_DB_GPIO4 136
+#define SRST_P_RKVENC_IOC 137
+#define SRST_H_SPDIF 138
+#define SRST_M_SPDIF 139
+#define SRST_H_PDM 140
+#define SRST_M_PDM 141
+#define SRST_P_UART1 142
+#define SRST_S_UART1 143
+#define SRST_P_UART3 144
+#define SRST_S_UART3 145
+#define SRST_P_RKVENC_GRF 146
+#define SRST_P_CAN0 147
+#define SRST_CAN0 148
+#define SRST_P_CAN1 149
+#define SRST_CAN1 150
+#define SRST_A_VO_BIU 151
+#define SRST_H_VO_BIU 152
+#define SRST_P_VO_BIU 153
+#define SRST_H_RGA2E 154
+#define SRST_A_RGA2E 155
+#define SRST_CORE_RGA2E 156
+#define SRST_H_VDPP 157
+#define SRST_A_VDPP 158
+#define SRST_CORE_VDPP 159
+#define SRST_P_VO_GRF 160
+#define SRST_P_CRU 161
+#define SRST_A_VOP_BIU 162
+#define SRST_H_VOP 163
+#define SRST_D_VOP0 164
+#define SRST_D_VOP1 165
+#define SRST_A_VOP 166
+#define SRST_P_HDMI 167
+#define SRST_HDMI 168
+#define SRST_P_HDMIPHY 169
+#define SRST_H_HDCP_KEY 170
+#define SRST_A_HDCP 171
+#define SRST_H_HDCP 172
+#define SRST_P_HDCP 173
+#define SRST_H_CVBS 174
+#define SRST_D_CVBS_VOP 175
+#define SRST_D_4X_CVBS_VOP 176
+#define SRST_A_JPEG_DECODER 177
+#define SRST_H_JPEG_DECODER 178
+#define SRST_A_VO_L_BIU 179
+#define SRST_A_MAC_VO 180
+#define SRST_A_JPEG_BIU 181
+#define SRST_H_SAI_I2S3 182
+#define SRST_M_SAI_I2S3 183
+#define SRST_MACPHY 184
+#define SRST_P_VCDCPHY 185
+#define SRST_P_GPIO2 186
+#define SRST_DB_GPIO2 187
+#define SRST_P_VO_IOC 188
+#define SRST_H_SDMMC0 189
+#define SRST_P_OTPC_NS 190
+#define SRST_SBPI_OTPC_NS 191
+#define SRST_USER_OTPC_NS 192
+#define SRST_HDMIHDP0 193
+#define SRST_H_USBHOST 194
+#define SRST_H_USBHOST_ARB 195
+#define SRST_HOST_UTMI 196
+#define SRST_P_UART4 197
+#define SRST_S_UART4 198
+#define SRST_P_I2C4 199
+#define SRST_I2C4 200
+#define SRST_P_I2C7 201
+#define SRST_I2C7 202
+#define SRST_P_USBPHY 203
+#define SRST_USBPHY_POR 204
+#define SRST_USBPHY_OTG 205
+#define SRST_USBPHY_HOST 206
+#define SRST_P_DDRPHY_CRU 207
+#define SRST_H_RKVDEC_BIU 208
+#define SRST_A_RKVDEC_BIU 209
+#define SRST_A_RKVDEC 210
+#define SRST_H_RKVDEC 211
+#define SRST_HEVC_CA_RKVDEC 212
+#define SRST_REF_PVTPLL_RKVDEC 213
+#define SRST_P_DDR_BIU 214
+#define SRST_P_DDRC 215
+#define SRST_P_DDRMON 216
+#define SRST_TIMER_DDRMON 217
+#define SRST_P_MSCH_BIU 218
+#define SRST_P_DDR_GRF 219
+#define SRST_P_DDR_HWLP 220
+#define SRST_P_DDRPHY 221
+#define SRST_MSCH_BIU 222
+#define SRST_A_DDR_UPCTL 223
+#define SRST_DDR_UPCTL 224
+#define SRST_DDRMON 225
+#define SRST_A_DDR_SCRAMBLE 226
+#define SRST_A_SPLIT 227
+#define SRST_DDR_PHY 228
+
+#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 02/30] arm64: dts: rockchip: Add clock generators for RK3528 SoC
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
2025-04-07 22:46 ` [PATCH v2 01/30] dt-bindings: clock: Document clock and reset unit of RK3528 Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:21 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 03/30] arm64: dts: rockchip: Add UART clocks " Jonas Karlman
` (27 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman, Heiko Stuebner
From: Yao Zi <ziyao@disroot.org>
Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is
generated by internal Ethernet phy, a fixed clock node is added as a
placeholder to avoid orphans.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250217061142.38480-9-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 858cdcdd11cf9913756297d3869e4de0f01329ea ]
(cherry picked from commit 60741472b42e92d2393327cb70669ab90e3b382f)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
dts/upstream/src/arm64/rockchip/rk3528.dtsi | 51 +++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
index e58faa985aa4..37fd40377076 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/rockchip,rk3528-cru.h>
/ {
compatible = "rockchip,rk3528";
@@ -95,6 +96,13 @@
#clock-cells = <0>;
};
+ gmac0_clk: clock-gmac50m {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "gmac0";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
@@ -114,6 +122,49 @@
#interrupt-cells = <3>;
};
+ cru: clock-controller@ff4a0000 {
+ compatible = "rockchip,rk3528-cru";
+ reg = <0x0 0xff4a0000 0x0 0x30000>;
+ assigned-clocks =
+ <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>,
+ <&cru PLL_PPLL>, <&cru PLL_CPLL>,
+ <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>,
+ <&cru CLK_MATRIX_500M_SRC>,
+ <&cru CLK_MATRIX_50M_SRC>,
+ <&cru CLK_MATRIX_100M_SRC>,
+ <&cru CLK_MATRIX_150M_SRC>,
+ <&cru CLK_MATRIX_200M_SRC>,
+ <&cru CLK_MATRIX_300M_SRC>,
+ <&cru CLK_MATRIX_339M_SRC>,
+ <&cru CLK_MATRIX_400M_SRC>,
+ <&cru CLK_MATRIX_600M_SRC>,
+ <&cru CLK_PPLL_50M_MATRIX>,
+ <&cru CLK_PPLL_100M_MATRIX>,
+ <&cru CLK_PPLL_125M_MATRIX>,
+ <&cru ACLK_BUS_VOPGL_ROOT>;
+ assigned-clock-rates =
+ <32768>, <1188000000>,
+ <1000000000>, <996000000>,
+ <408000000>, <250000000>,
+ <500000000>,
+ <50000000>,
+ <100000000>,
+ <150000000>,
+ <200000000>,
+ <300000000>,
+ <340000000>,
+ <400000000>,
+ <600000000>,
+ <50000000>,
+ <100000000>,
+ <125000000>,
+ <500000000>;
+ clocks = <&xin24m>, <&gmac0_clk>;
+ clock-names = "xin24m", "gmac0";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
uart0: serial@ff9f0000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xff9f0000 0x0 0x100>;
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 03/30] arm64: dts: rockchip: Add UART clocks for RK3528 SoC
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
2025-04-07 22:46 ` [PATCH v2 01/30] dt-bindings: clock: Document clock and reset unit of RK3528 Jonas Karlman
2025-04-07 22:46 ` [PATCH v2 02/30] arm64: dts: rockchip: Add clock generators for RK3528 SoC Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:21 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 04/30] arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528 Jonas Karlman
` (26 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman, Heiko Stuebner
From: Yao Zi <ziyao@disroot.org>
Add missing clocks in UART nodes for RK3528 SoC.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Link: https://lore.kernel.org/r/20250217061142.38480-10-ziyao@disroot.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: b9454434d0349223418f74fbfa7b902104da9bc5 ]
(cherry picked from commit 12f69f638472dc9cf1b62816c7d4407de1846d12)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
dts/upstream/src/arm64/rockchip/rk3528.dtsi | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
index 37fd40377076..5b334690356a 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
@@ -168,7 +168,8 @@
uart0: serial@ff9f0000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xff9f0000 0x0 0x100>;
- clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -178,6 +179,8 @@
uart1: serial@ff9f8000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xff9f8000 0x0 0x100>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -187,6 +190,8 @@
uart2: serial@ffa00000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa00000 0x0 0x100>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -195,6 +200,8 @@
uart3: serial@ffa08000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
reg = <0x0 0xffa08000 0x0 0x100>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -204,6 +211,8 @@
uart4: serial@ffa10000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa10000 0x0 0x100>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -213,6 +222,8 @@
uart5: serial@ffa18000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa18000 0x0 0x100>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -222,6 +233,8 @@
uart6: serial@ffa20000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa20000 0x0 0x100>;
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -231,6 +244,8 @@
uart7: serial@ffa28000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xffa28000 0x0 0x100>;
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 04/30] arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (2 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 03/30] arm64: dts: rockchip: Add UART clocks " Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:21 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 05/30] arm64: dts: rockchip: Add rk3528 QoS register node Jonas Karlman
` (25 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman, Heiko Stuebner
Add pinctrl and gpio nodes for RK3528 and import rk3528-pinctrl.dtsi
from vendor linux-6.1-stan-rkr5 kernel with the hdmi-pins-idle node
removed due to missing label reference to pcfg_output_low_pull_down.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250228064024.3200000-5-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: a31fad19ae39ea27b5068e3b02bcbf30a905339b ]
(cherry picked from commit 89a24fa2e923b68a42ccc8cc9cb2d5bdf291ac40)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
.../src/arm64/rockchip/rk3528-pinctrl.dtsi | 1397 +++++++++++++++++
dts/upstream/src/arm64/rockchip/rk3528.dtsi | 82 +
2 files changed, 1479 insertions(+)
create mode 100644 dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi
diff --git a/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi b/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi
new file mode 100644
index 000000000000..ea051362fb26
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi
@@ -0,0 +1,1397 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ arm {
+ /omit-if-no-ref/
+ arm_pins: arm-pins {
+ rockchip,pins =
+ /* arm_avs */
+ <4 RK_PC4 3 &pcfg_pull_none>;
+ };
+ };
+
+ clk {
+ /omit-if-no-ref/
+ clkm0_32k_out: clkm0-32k-out {
+ rockchip,pins =
+ /* clkm0_32k_out */
+ <3 RK_PC3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ clkm1_32k_out: clkm1-32k-out {
+ rockchip,pins =
+ /* clkm1_32k_out */
+ <1 RK_PC3 1 &pcfg_pull_none>;
+ };
+ };
+
+ emmc {
+ /omit-if-no-ref/
+ emmc_rstnout: emmc-rstnout {
+ rockchip,pins =
+ /* emmc_rstn */
+ <1 RK_PD6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <1 RK_PC7 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d4 */
+ <1 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d5 */
+ <1 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d6 */
+ <1 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d7 */
+ <1 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clk */
+ <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <1 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_strb: emmc-strb {
+ rockchip,pins =
+ /* emmc_strb */
+ <1 RK_PD7 1 &pcfg_pull_none>;
+ };
+ };
+
+ eth {
+ /omit-if-no-ref/
+ eth_pins: eth-pins {
+ rockchip,pins =
+ /* eth_clk_25m_out */
+ <3 RK_PB5 2 &pcfg_pull_none_drv_level_2>;
+ };
+ };
+
+ fephy {
+ /omit-if-no-ref/
+ fephym0_led_dpx: fephym0-led_dpx {
+ rockchip,pins =
+ /* fephy_led_dpx_m0 */
+ <4 RK_PB5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fephym0_led_link: fephym0-led_link {
+ rockchip,pins =
+ /* fephy_led_link_m0 */
+ <4 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fephym0_led_spd: fephym0-led_spd {
+ rockchip,pins =
+ /* fephy_led_spd_m0 */
+ <4 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fephym1_led_dpx: fephym1-led_dpx {
+ rockchip,pins =
+ /* fephy_led_dpx_m1 */
+ <2 RK_PA4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fephym1_led_link: fephym1-led_link {
+ rockchip,pins =
+ /* fephy_led_link_m1 */
+ <2 RK_PA6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fephym1_led_spd: fephym1-led_spd {
+ rockchip,pins =
+ /* fephy_led_spd_m1 */
+ <2 RK_PA5 5 &pcfg_pull_none>;
+ };
+ };
+
+ fspi {
+ /omit-if-no-ref/
+ fspi_pins: fspi-pins {
+ rockchip,pins =
+ /* fspi_clk */
+ <1 RK_PD5 2 &pcfg_pull_none>,
+ /* fspi_d0 */
+ <1 RK_PC4 2 &pcfg_pull_none>,
+ /* fspi_d1 */
+ <1 RK_PC5 2 &pcfg_pull_none>,
+ /* fspi_d2 */
+ <1 RK_PC6 2 &pcfg_pull_none>,
+ /* fspi_d3 */
+ <1 RK_PC7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi_csn0: fspi-csn0 {
+ rockchip,pins =
+ /* fspi_csn0 */
+ <1 RK_PD0 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ fspi_csn1: fspi-csn1 {
+ rockchip,pins =
+ /* fspi_csn1 */
+ <1 RK_PD1 2 &pcfg_pull_none>;
+ };
+ };
+
+ gpu {
+ /omit-if-no-ref/
+ gpu_pins: gpu-pins {
+ rockchip,pins =
+ /* gpu_avs */
+ <4 RK_PC3 3 &pcfg_pull_none>;
+ };
+ };
+
+ hdmi {
+ /omit-if-no-ref/
+ hdmi_pins: hdmi-pins {
+ rockchip,pins =
+ /* hdmi_tx_cec */
+ <0 RK_PA3 1 &pcfg_pull_none>,
+ /* hdmi_tx_hpd */
+ <0 RK_PA2 1 &pcfg_pull_none>,
+ /* hdmi_tx_scl */
+ <0 RK_PA4 1 &pcfg_pull_none>,
+ /* hdmi_tx_sda */
+ <0 RK_PA5 1 &pcfg_pull_none>;
+ };
+ };
+
+ hsm {
+ /omit-if-no-ref/
+ hsmm0_pins: hsmm0-pins {
+ rockchip,pins =
+ /* hsm_clk_out_m0 */
+ <2 RK_PA2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hsmm1_pins: hsmm1-pins {
+ rockchip,pins =
+ /* hsm_clk_out_m1 */
+ <1 RK_PA4 3 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0m0_xfer: i2c0m0-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m0 */
+ <4 RK_PC4 2 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m0 */
+ <4 RK_PC3 2 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c0m1_xfer: i2c0m1-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m1 */
+ <4 RK_PA1 2 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m1 */
+ <4 RK_PA0 2 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c1 {
+ /omit-if-no-ref/
+ i2c1m0_xfer: i2c1m0-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m0 */
+ <4 RK_PA3 2 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m0 */
+ <4 RK_PA2 2 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c1m1_xfer: i2c1m1-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m1 */
+ <4 RK_PC5 4 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m1 */
+ <4 RK_PC6 4 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2m0_xfer: i2c2m0-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m0 */
+ <0 RK_PA4 2 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m0 */
+ <0 RK_PA5 2 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m1_xfer: i2c2m1-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m1 */
+ <1 RK_PA5 3 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m1 */
+ <1 RK_PA6 3 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3 {
+ /omit-if-no-ref/
+ i2c3m0_xfer: i2c3m0-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m0 */
+ <1 RK_PA0 2 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m0 */
+ <1 RK_PA1 2 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m1_xfer: i2c3m1-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m1 */
+ <3 RK_PC1 5 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m1 */
+ <3 RK_PC3 5 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c4 {
+ /omit-if-no-ref/
+ i2c4_xfer: i2c4-xfer {
+ rockchip,pins =
+ /* i2c4_scl */
+ <2 RK_PA0 4 &pcfg_pull_none_smt>,
+ /* i2c4_sda */
+ <2 RK_PA1 4 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c5 {
+ /omit-if-no-ref/
+ i2c5m0_xfer: i2c5m0-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m0 */
+ <1 RK_PB2 3 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m0 */
+ <1 RK_PB3 3 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m1_xfer: i2c5m1-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m1 */
+ <1 RK_PD2 3 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m1 */
+ <1 RK_PD3 3 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c6 {
+ /omit-if-no-ref/
+ i2c6m0_xfer: i2c6m0-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m0 */
+ <3 RK_PB2 5 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m0 */
+ <3 RK_PB3 5 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c6m1_xfer: i2c6m1-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m1 */
+ <1 RK_PD4 3 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m1 */
+ <1 RK_PD7 3 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c7 {
+ /omit-if-no-ref/
+ i2c7_xfer: i2c7-xfer {
+ rockchip,pins =
+ /* i2c7_scl */
+ <2 RK_PA5 4 &pcfg_pull_none_smt>,
+ /* i2c7_sda */
+ <2 RK_PA6 4 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2s0 {
+ /omit-if-no-ref/
+ i2s0m0_lrck: i2s0m0-lrck {
+ rockchip,pins =
+ /* i2s0_lrck_m0 */
+ <3 RK_PB6 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m0_mclk: i2s0m0-mclk {
+ rockchip,pins =
+ /* i2s0_mclk_m0 */
+ <3 RK_PB4 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m0_sclk: i2s0m0-sclk {
+ rockchip,pins =
+ /* i2s0_sclk_m0 */
+ <3 RK_PB5 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m0_sdi: i2s0m0-sdi {
+ rockchip,pins =
+ /* i2s0m0_sdi */
+ <3 RK_PB7 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ i2s0m0_sdo: i2s0m0-sdo {
+ rockchip,pins =
+ /* i2s0m0_sdo */
+ <3 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_lrck: i2s0m1-lrck {
+ rockchip,pins =
+ /* i2s0_lrck_m1 */
+ <1 RK_PB6 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_mclk: i2s0m1-mclk {
+ rockchip,pins =
+ /* i2s0_mclk_m1 */
+ <1 RK_PB4 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_sclk: i2s0m1-sclk {
+ rockchip,pins =
+ /* i2s0_sclk_m1 */
+ <1 RK_PB5 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s0m1_sdi: i2s0m1-sdi {
+ rockchip,pins =
+ /* i2s0m1_sdi */
+ <1 RK_PB7 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ i2s0m1_sdo: i2s0m1-sdo {
+ rockchip,pins =
+ /* i2s0m1_sdo */
+ <1 RK_PC0 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2s1 {
+ /omit-if-no-ref/
+ i2s1_lrck: i2s1-lrck {
+ rockchip,pins =
+ /* i2s1_lrck */
+ <4 RK_PA6 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_mclk: i2s1-mclk {
+ rockchip,pins =
+ /* i2s1_mclk */
+ <4 RK_PA4 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sclk: i2s1-sclk {
+ rockchip,pins =
+ /* i2s1_sclk */
+ <4 RK_PA5 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sdi0: i2s1-sdi0 {
+ rockchip,pins =
+ /* i2s1_sdi0 */
+ <4 RK_PB4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sdi1: i2s1-sdi1 {
+ rockchip,pins =
+ /* i2s1_sdi1 */
+ <4 RK_PB3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sdi2: i2s1-sdi2 {
+ rockchip,pins =
+ /* i2s1_sdi2 */
+ <4 RK_PA3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sdi3: i2s1-sdi3 {
+ rockchip,pins =
+ /* i2s1_sdi3 */
+ <4 RK_PA2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sdo0: i2s1-sdo0 {
+ rockchip,pins =
+ /* i2s1_sdo0 */
+ <4 RK_PA7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sdo1: i2s1-sdo1 {
+ rockchip,pins =
+ /* i2s1_sdo1 */
+ <4 RK_PB0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sdo2: i2s1-sdo2 {
+ rockchip,pins =
+ /* i2s1_sdo2 */
+ <4 RK_PB1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1_sdo3: i2s1-sdo3 {
+ rockchip,pins =
+ /* i2s1_sdo3 */
+ <4 RK_PB2 1 &pcfg_pull_none>;
+ };
+ };
+
+ jtag {
+ /omit-if-no-ref/
+ jtagm0_pins: jtagm0-pins {
+ rockchip,pins =
+ /* jtag_cpu_tck_m0 */
+ <2 RK_PA2 2 &pcfg_pull_none>,
+ /* jtag_cpu_tms_m0 */
+ <2 RK_PA3 2 &pcfg_pull_none>,
+ /* jtag_mcu_tck_m0 */
+ <2 RK_PA4 2 &pcfg_pull_none>,
+ /* jtag_mcu_tms_m0 */
+ <2 RK_PA5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ jtagm1_pins: jtagm1-pins {
+ rockchip,pins =
+ /* jtag_cpu_tck_m1 */
+ <4 RK_PD0 2 &pcfg_pull_none>,
+ /* jtag_cpu_tms_m1 */
+ <4 RK_PC7 2 &pcfg_pull_none>,
+ /* jtag_mcu_tck_m1 */
+ <4 RK_PD0 3 &pcfg_pull_none>,
+ /* jtag_mcu_tms_m1 */
+ <4 RK_PC7 3 &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ /omit-if-no-ref/
+ pciem0_pins: pciem0-pins {
+ rockchip,pins =
+ /* pcie_clkreqn_m0 */
+ <3 RK_PA6 5 &pcfg_pull_none>,
+ /* pcie_perstn_m0 */
+ <3 RK_PB0 5 &pcfg_pull_none>,
+ /* pcie_waken_m0 */
+ <3 RK_PA7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pciem1_pins: pciem1-pins {
+ rockchip,pins =
+ /* pcie_clkreqn_m1 */
+ <1 RK_PA0 4 &pcfg_pull_none>,
+ /* pcie_perstn_m1 */
+ <1 RK_PA2 4 &pcfg_pull_none>,
+ /* pcie_waken_m1 */
+ <1 RK_PA1 4 &pcfg_pull_none>;
+ };
+ };
+
+ pdm {
+ /omit-if-no-ref/
+ pdm_clk0: pdm-clk0 {
+ rockchip,pins =
+ /* pdm_clk0 */
+ <4 RK_PB5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm_clk1: pdm-clk1 {
+ rockchip,pins =
+ /* pdm_clk1 */
+ <4 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm_sdi0: pdm-sdi0 {
+ rockchip,pins =
+ /* pdm_sdi0 */
+ <4 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm_sdi1: pdm-sdi1 {
+ rockchip,pins =
+ /* pdm_sdi1 */
+ <4 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm_sdi2: pdm-sdi2 {
+ rockchip,pins =
+ /* pdm_sdi2 */
+ <4 RK_PB3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm_sdi3: pdm-sdi3 {
+ rockchip,pins =
+ /* pdm_sdi3 */
+ <4 RK_PC1 3 &pcfg_pull_none>;
+ };
+ };
+
+ pmu {
+ /omit-if-no-ref/
+ pmu_pins: pmu-pins {
+ rockchip,pins =
+ /* pmu_debug */
+ <4 RK_PA0 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm0 {
+ /omit-if-no-ref/
+ pwm0m0_pins: pwm0m0-pins {
+ rockchip,pins =
+ /* pwm0_m0 */
+ <4 RK_PC3 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m1_pins: pwm0m1-pins {
+ rockchip,pins =
+ /* pwm0_m1 */
+ <1 RK_PA2 5 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwm1 {
+ /omit-if-no-ref/
+ pwm1m0_pins: pwm1m0-pins {
+ rockchip,pins =
+ /* pwm1_m0 */
+ <4 RK_PC4 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_pins: pwm1m1-pins {
+ rockchip,pins =
+ /* pwm1_m1 */
+ <1 RK_PA3 4 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwm2 {
+ /omit-if-no-ref/
+ pwm2m0_pins: pwm2m0-pins {
+ rockchip,pins =
+ /* pwm2_m0 */
+ <4 RK_PC5 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_pins: pwm2m1-pins {
+ rockchip,pins =
+ /* pwm2_m1 */
+ <1 RK_PA7 2 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwm3 {
+ /omit-if-no-ref/
+ pwm3m0_pins: pwm3m0-pins {
+ rockchip,pins =
+ /* pwm3_m0 */
+ <4 RK_PC6 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm3m1_pins: pwm3m1-pins {
+ rockchip,pins =
+ /* pwm3_m1 */
+ <2 RK_PA4 3 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwm4 {
+ /omit-if-no-ref/
+ pwm4m0_pins: pwm4m0-pins {
+ rockchip,pins =
+ /* pwm4_m0 */
+ <4 RK_PB7 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm4m1_pins: pwm4m1-pins {
+ rockchip,pins =
+ /* pwm4_m1 */
+ <1 RK_PA4 2 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwm5 {
+ /omit-if-no-ref/
+ pwm5m0_pins: pwm5m0-pins {
+ rockchip,pins =
+ /* pwm5_m0 */
+ <4 RK_PC0 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm5m1_pins: pwm5m1-pins {
+ rockchip,pins =
+ /* pwm5_m1 */
+ <3 RK_PC3 1 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwm6 {
+ /omit-if-no-ref/
+ pwm6m0_pins: pwm6m0-pins {
+ rockchip,pins =
+ /* pwm6_m0 */
+ <4 RK_PC1 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm6m1_pins: pwm6m1-pins {
+ rockchip,pins =
+ /* pwm6_m1 */
+ <1 RK_PC3 3 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm6m2_pins: pwm6m2-pins {
+ rockchip,pins =
+ /* pwm6_m2 */
+ <3 RK_PC1 1 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwm7 {
+ /omit-if-no-ref/
+ pwm7m0_pins: pwm7m0-pins {
+ rockchip,pins =
+ /* pwm7_m0 */
+ <4 RK_PC2 1 &pcfg_pull_none_drv_level_0>;
+ };
+
+ /omit-if-no-ref/
+ pwm7m1_pins: pwm7m1-pins {
+ rockchip,pins =
+ /* pwm7_m1 */
+ <1 RK_PC2 2 &pcfg_pull_none_drv_level_0>;
+ };
+ };
+
+ pwr {
+ /omit-if-no-ref/
+ pwr_pins: pwr-pins {
+ rockchip,pins =
+ /* pwr_ctrl0 */
+ <4 RK_PC2 2 &pcfg_pull_none>,
+ /* pwr_ctrl1 */
+ <4 RK_PB6 1 &pcfg_pull_none>;
+ };
+ };
+
+ ref {
+ /omit-if-no-ref/
+ refm0_pins: refm0-pins {
+ rockchip,pins =
+ /* ref_clk_out_m0 */
+ <0 RK_PA1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ refm1_pins: refm1-pins {
+ rockchip,pins =
+ /* ref_clk_out_m1 */
+ <3 RK_PC3 6 &pcfg_pull_none>;
+ };
+ };
+
+ rgmii {
+ /omit-if-no-ref/
+ rgmii_miim: rgmii-miim {
+ rockchip,pins =
+ /* rgmii_mdc */
+ <3 RK_PB6 2 &pcfg_pull_none_drv_level_2>,
+ /* rgmii_mdio */
+ <3 RK_PB7 2 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ rgmii_rx_bus2: rgmii-rx_bus2 {
+ rockchip,pins =
+ /* rgmii_rxd0 */
+ <3 RK_PA3 2 &pcfg_pull_none>,
+ /* rgmii_rxd1 */
+ <3 RK_PA2 2 &pcfg_pull_none>,
+ /* rgmii_rxdv_crs */
+ <3 RK_PC2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmii_tx_bus2: rgmii-tx_bus2 {
+ rockchip,pins =
+ /* rgmii_txd0 */
+ <3 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
+ /* rgmii_txd1 */
+ <3 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
+ /* rgmii_txen */
+ <3 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgmii_rgmii_clk: rgmii-rgmii_clk {
+ rockchip,pins =
+ /* rgmii_rxclk */
+ <3 RK_PA5 2 &pcfg_pull_none>,
+ /* rgmii_txclk */
+ <3 RK_PA4 2 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ rgmii_rgmii_bus: rgmii-rgmii_bus {
+ rockchip,pins =
+ /* rgmii_rxd2 */
+ <3 RK_PA7 2 &pcfg_pull_none>,
+ /* rgmii_rxd3 */
+ <3 RK_PA6 2 &pcfg_pull_none>,
+ /* rgmii_txd2 */
+ <3 RK_PB1 2 &pcfg_pull_none_drv_level_2>,
+ /* rgmii_txd3 */
+ <3 RK_PB0 2 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ rgmii_clk: rgmii-clk {
+ rockchip,pins =
+ /* rgmii_clk */
+ <3 RK_PB4 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ rgmii_txer: rgmii-txer {
+ rockchip,pins =
+ /* rgmii_txer */
+ <3 RK_PC1 2 &pcfg_pull_none>;
+ };
+ };
+
+ scr {
+ /omit-if-no-ref/
+ scrm0_pins: scrm0-pins {
+ rockchip,pins =
+ /* scr_clk_m0 */
+ <1 RK_PA2 3 &pcfg_pull_none>,
+ /* scr_data_m0 */
+ <1 RK_PA1 3 &pcfg_pull_none>,
+ /* scr_detn_m0 */
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ /* scr_rstn_m0 */
+ <1 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ scrm1_pins: scrm1-pins {
+ rockchip,pins =
+ /* scr_clk_m1 */
+ <2 RK_PA5 3 &pcfg_pull_none>,
+ /* scr_data_m1 */
+ <2 RK_PA3 4 &pcfg_pull_none>,
+ /* scr_detn_m1 */
+ <2 RK_PA6 3 &pcfg_pull_none>,
+ /* scr_rstn_m1 */
+ <2 RK_PA4 4 &pcfg_pull_none>;
+ };
+ };
+
+ sdio0 {
+ /omit-if-no-ref/
+ sdio0_bus4: sdio0-bus4 {
+ rockchip,pins =
+ /* sdio0_d0 */
+ <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio0_d1 */
+ <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio0_d2 */
+ <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio0_d3 */
+ <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdio0_clk: sdio0-clk {
+ rockchip,pins =
+ /* sdio0_clk */
+ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdio0_cmd: sdio0-cmd {
+ rockchip,pins =
+ /* sdio0_cmd */
+ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdio0_det: sdio0-det {
+ rockchip,pins =
+ /* sdio0_det */
+ <1 RK_PA6 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdio0_pwren: sdio0-pwren {
+ rockchip,pins =
+ /* sdio0_pwren */
+ <1 RK_PA7 1 &pcfg_pull_none>;
+ };
+ };
+
+ sdio1 {
+ /omit-if-no-ref/
+ sdio1_bus4: sdio1-bus4 {
+ rockchip,pins =
+ /* sdio1_d0 */
+ <3 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio1_d1 */
+ <3 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio1_d2 */
+ <3 RK_PB0 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio1_d3 */
+ <3 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdio1_clk: sdio1-clk {
+ rockchip,pins =
+ /* sdio1_clk */
+ <3 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdio1_cmd: sdio1-cmd {
+ rockchip,pins =
+ /* sdio1_cmd */
+ <3 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdio1_det: sdio1-det {
+ rockchip,pins =
+ /* sdio1_det */
+ <3 RK_PB3 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdio1_pwren: sdio1-pwren {
+ rockchip,pins =
+ /* sdio1_pwren */
+ <3 RK_PB2 1 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc {
+ /omit-if-no-ref/
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins =
+ /* sdmmc_d0 */
+ <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc_d1 */
+ <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc_d2 */
+ <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc_d3 */
+ <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins =
+ /* sdmmc_clk */
+ <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins =
+ /* sdmmc_cmd */
+ <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc_det: sdmmc-det {
+ rockchip,pins =
+ /* sdmmc_detn */
+ <2 RK_PA6 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc_pwren: sdmmc-pwren {
+ rockchip,pins =
+ /* sdmmc_pwren */
+ <4 RK_PA1 1 &pcfg_pull_none>;
+ };
+ };
+
+ spdif {
+ /omit-if-no-ref/
+ spdifm0_pins: spdifm0-pins {
+ rockchip,pins =
+ /* spdif_tx_m0 */
+ <4 RK_PA0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm1_pins: spdifm1-pins {
+ rockchip,pins =
+ /* spdif_tx_m1 */
+ <1 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm2_pins: spdifm2-pins {
+ rockchip,pins =
+ /* spdif_tx_m2 */
+ <3 RK_PC3 2 &pcfg_pull_none>;
+ };
+ };
+
+ spi0 {
+ /omit-if-no-ref/
+ spi0_pins: spi0-pins {
+ rockchip,pins =
+ /* spi0_clk */
+ <4 RK_PB4 2 &pcfg_pull_none_drv_level_2>,
+ /* spi0_miso */
+ <4 RK_PB3 2 &pcfg_pull_none_drv_level_2>,
+ /* spi0_mosi */
+ <4 RK_PB2 2 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ spi0_csn0: spi0-csn0 {
+ rockchip,pins =
+ /* spi0_csn0 */
+ <4 RK_PB6 2 &pcfg_pull_none_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ spi0_csn1: spi0-csn1 {
+ rockchip,pins =
+ /* spi0_csn1 */
+ <4 RK_PC1 2 &pcfg_pull_none_drv_level_2>;
+ };
+ };
+
+ spi1 {
+ /omit-if-no-ref/
+ spi1_pins: spi1-pins {
+ rockchip,pins =
+ /* spi1_clk */
+ <1 RK_PB6 2 &pcfg_pull_none_drv_level_2>,
+ /* spi1_miso */
+ <1 RK_PC0 2 &pcfg_pull_none_drv_level_2>,
+ /* spi1_mosi */
+ <1 RK_PB7 2 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ spi1_csn0: spi1-csn0 {
+ rockchip,pins =
+ /* spi1_csn0 */
+ <1 RK_PC1 1 &pcfg_pull_none_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ spi1_csn1: spi1-csn1 {
+ rockchip,pins =
+ /* spi1_csn1 */
+ <1 RK_PC2 1 &pcfg_pull_none_drv_level_2>;
+ };
+ };
+
+ tsi0 {
+ /omit-if-no-ref/
+ tsi0_pins: tsi0-pins {
+ rockchip,pins =
+ /* tsi0_clkin */
+ <3 RK_PB2 3 &pcfg_pull_none>,
+ /* tsi0_d0 */
+ <3 RK_PB1 3 &pcfg_pull_none>,
+ /* tsi0_d1 */
+ <3 RK_PB5 3 &pcfg_pull_none>,
+ /* tsi0_d2 */
+ <3 RK_PB6 3 &pcfg_pull_none>,
+ /* tsi0_d3 */
+ <3 RK_PB7 3 &pcfg_pull_none>,
+ /* tsi0_d4 */
+ <3 RK_PA3 3 &pcfg_pull_none>,
+ /* tsi0_d5 */
+ <3 RK_PA2 3 &pcfg_pull_none>,
+ /* tsi0_d6 */
+ <3 RK_PA1 3 &pcfg_pull_none>,
+ /* tsi0_d7 */
+ <3 RK_PA0 3 &pcfg_pull_none>,
+ /* tsi0_fail */
+ <3 RK_PC0 3 &pcfg_pull_none>,
+ /* tsi0_sync */
+ <3 RK_PB4 3 &pcfg_pull_none>,
+ /* tsi0_valid */
+ <3 RK_PB3 3 &pcfg_pull_none>;
+ };
+ };
+
+ tsi1 {
+ /omit-if-no-ref/
+ tsi1_pins: tsi1-pins {
+ rockchip,pins =
+ /* tsi1_clkin */
+ <3 RK_PA5 3 &pcfg_pull_none>,
+ /* tsi1_d0 */
+ <3 RK_PA4 3 &pcfg_pull_none>,
+ /* tsi1_sync */
+ <3 RK_PA7 3 &pcfg_pull_none>,
+ /* tsi1_valid */
+ <3 RK_PA6 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ /omit-if-no-ref/
+ uart0m0_xfer: uart0m0-xfer {
+ rockchip,pins =
+ /* uart0_rx_m0 */
+ <4 RK_PC7 1 &pcfg_pull_up>,
+ /* uart0_tx_m0 */
+ <4 RK_PD0 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart0m1_xfer: uart0m1-xfer {
+ rockchip,pins =
+ /* uart0_rx_m1 */
+ <2 RK_PA0 2 &pcfg_pull_up>,
+ /* uart0_tx_m1 */
+ <2 RK_PA1 2 &pcfg_pull_up>;
+ };
+ };
+
+ uart1 {
+ /omit-if-no-ref/
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <4 RK_PA7 2 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <4 RK_PA6 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_xfer: uart1m1-xfer {
+ rockchip,pins =
+ /* uart1_rx_m1 */
+ <4 RK_PC6 2 &pcfg_pull_up>,
+ /* uart1_tx_m1 */
+ <4 RK_PC5 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1_ctsn: uart1-ctsn {
+ rockchip,pins =
+ /* uart1_ctsn */
+ <4 RK_PA4 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart1_rtsn: uart1-rtsn {
+ rockchip,pins =
+ /* uart1_rtsn */
+ <4 RK_PA5 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ /omit-if-no-ref/
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins =
+ /* uart2_rx_m0 */
+ <3 RK_PA0 1 &pcfg_pull_up>,
+ /* uart2_tx_m0 */
+ <3 RK_PA1 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m0_ctsn: uart2m0-ctsn {
+ rockchip,pins =
+ /* uart2m0_ctsn */
+ <3 RK_PA3 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart2m0_rtsn: uart2m0-rtsn {
+ rockchip,pins =
+ /* uart2m0_rtsn */
+ <3 RK_PA2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rx_m1 */
+ <1 RK_PB0 1 &pcfg_pull_up>,
+ /* uart2_tx_m1 */
+ <1 RK_PB1 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_ctsn: uart2m1-ctsn {
+ rockchip,pins =
+ /* uart2m1_ctsn */
+ <1 RK_PB3 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart2m1_rtsn: uart2m1-rtsn {
+ rockchip,pins =
+ /* uart2m1_rtsn */
+ <1 RK_PB2 1 &pcfg_pull_none>;
+ };
+ };
+
+ uart3 {
+ /omit-if-no-ref/
+ uart3m0_xfer: uart3m0-xfer {
+ rockchip,pins =
+ /* uart3_rx_m0 */
+ <4 RK_PB0 2 &pcfg_pull_up>,
+ /* uart3_tx_m0 */
+ <4 RK_PB1 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3m1_xfer: uart3m1-xfer {
+ rockchip,pins =
+ /* uart3_rx_m1 */
+ <4 RK_PB7 3 &pcfg_pull_up>,
+ /* uart3_tx_m1 */
+ <4 RK_PC0 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3_ctsn: uart3-ctsn {
+ rockchip,pins =
+ /* uart3_ctsn */
+ <4 RK_PA3 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart3_rtsn: uart3-rtsn {
+ rockchip,pins =
+ /* uart3_rtsn */
+ <4 RK_PA2 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart4 {
+ /omit-if-no-ref/
+ uart4_xfer: uart4-xfer {
+ rockchip,pins =
+ /* uart4_rx */
+ <2 RK_PA2 3 &pcfg_pull_up>,
+ /* uart4_tx */
+ <2 RK_PA3 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart4_ctsn: uart4-ctsn {
+ rockchip,pins =
+ /* uart4_ctsn */
+ <2 RK_PA1 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart4_rtsn: uart4-rtsn {
+ rockchip,pins =
+ /* uart4_rtsn */
+ <2 RK_PA0 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart5 {
+ /omit-if-no-ref/
+ uart5m0_xfer: uart5m0-xfer {
+ rockchip,pins =
+ /* uart5_rx_m0 */
+ <1 RK_PA2 2 &pcfg_pull_up>,
+ /* uart5_tx_m0 */
+ <1 RK_PA3 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m0_ctsn: uart5m0-ctsn {
+ rockchip,pins =
+ /* uart5m0_ctsn */
+ <1 RK_PA6 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart5m0_rtsn: uart5m0-rtsn {
+ rockchip,pins =
+ /* uart5m0_rtsn */
+ <1 RK_PA5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_xfer: uart5m1-xfer {
+ rockchip,pins =
+ /* uart5_rx_m1 */
+ <1 RK_PD4 2 &pcfg_pull_up>,
+ /* uart5_tx_m1 */
+ <1 RK_PD7 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_ctsn: uart5m1-ctsn {
+ rockchip,pins =
+ /* uart5m1_ctsn */
+ <1 RK_PD3 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart5m1_rtsn: uart5m1-rtsn {
+ rockchip,pins =
+ /* uart5m1_rtsn */
+ <1 RK_PD2 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart6 {
+ /omit-if-no-ref/
+ uart6m0_xfer: uart6m0-xfer {
+ rockchip,pins =
+ /* uart6_rx_m0 */
+ <3 RK_PA7 4 &pcfg_pull_up>,
+ /* uart6_tx_m0 */
+ <3 RK_PA6 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6m1_xfer: uart6m1-xfer {
+ rockchip,pins =
+ /* uart6_rx_m1 */
+ <3 RK_PC3 4 &pcfg_pull_up>,
+ /* uart6_tx_m1 */
+ <3 RK_PC1 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6_ctsn: uart6-ctsn {
+ rockchip,pins =
+ /* uart6_ctsn */
+ <3 RK_PA4 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart6_rtsn: uart6-rtsn {
+ rockchip,pins =
+ /* uart6_rtsn */
+ <3 RK_PA5 4 &pcfg_pull_none>;
+ };
+ };
+
+ uart7 {
+ /omit-if-no-ref/
+ uart7m0_xfer: uart7m0-xfer {
+ rockchip,pins =
+ /* uart7_rx_m0 */
+ <3 RK_PB3 4 &pcfg_pull_up>,
+ /* uart7_tx_m0 */
+ <3 RK_PB2 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m0_ctsn: uart7m0-ctsn {
+ rockchip,pins =
+ /* uart7m0_ctsn */
+ <3 RK_PB0 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart7m0_rtsn: uart7m0-rtsn {
+ rockchip,pins =
+ /* uart7m0_rtsn */
+ <3 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m1_xfer: uart7m1-xfer {
+ rockchip,pins =
+ /* uart7_rx_m1 */
+ <1 RK_PB3 4 &pcfg_pull_up>,
+ /* uart7_tx_m1 */
+ <1 RK_PB2 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m1_ctsn: uart7m1-ctsn {
+ rockchip,pins =
+ /* uart7m1_ctsn */
+ <1 RK_PB0 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart7m1_rtsn: uart7m1-rtsn {
+ rockchip,pins =
+ /* uart7m1_rtsn */
+ <1 RK_PB1 4 &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
index 5b334690356a..b1713ed4d7e2 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
@@ -4,8 +4,10 @@
* Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
*/
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rockchip,rk3528-cru.h>
/ {
@@ -16,6 +18,11 @@
#size-cells = <2>;
aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -165,6 +172,11 @@
#reset-cells = <1>;
};
+ ioc_grf: syscon@ff540000 {
+ compatible = "rockchip,rk3528-ioc-grf", "syscon";
+ reg = <0x0 0xff540000 0x0 0x40000>;
+ };
+
uart0: serial@ff9f0000 {
compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
reg = <0x0 0xff9f0000 0x0 0x100>;
@@ -251,5 +263,75 @@
reg-shift = <2>;
status = "disabled";
};
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3528-pinctrl";
+ rockchip,grf = <&ioc_grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@ff610000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff610000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@ffaf0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffaf0000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@ffb00000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb00000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@ffb10000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb10000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@ffb20000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb20000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
};
};
+
+#include "rk3528-pinctrl.dtsi"
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 05/30] arm64: dts: rockchip: Add rk3528 QoS register node
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (3 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 04/30] arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528 Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:21 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 06/30] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC Jonas Karlman
` (24 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman, Heiko Stuebner
From: Chukun Pan <amadeus@jmu.edu.cn>
The Quality-of-Service (QsS) node stores/restores specific
register contents when the power domains is turned off/on.
Add QoS node so that they can connect to the power domain.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250306123809.273655-3-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 61a05d8ca3030a544175671f5fab7a8f29c24085 ]
(cherry picked from commit 9ee90dfd6957fcc42ea94c43d195b01d1b286713)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
dts/upstream/src/arm64/rockchip/rk3528.dtsi | 160 ++++++++++++++++++++
1 file changed, 160 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
index b1713ed4d7e2..0c0e7f151462 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
@@ -129,6 +129,166 @@
#interrupt-cells = <3>;
};
+ qos_crypto_a: qos@ff200000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200000 0x0 0x20>;
+ };
+
+ qos_crypto_p: qos@ff200080 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200080 0x0 0x20>;
+ };
+
+ qos_dcf: qos@ff200100 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200100 0x0 0x20>;
+ };
+
+ qos_dft2apb: qos@ff200200 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200200 0x0 0x20>;
+ };
+
+ qos_dma2ddr: qos@ff200280 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200280 0x0 0x20>;
+ };
+
+ qos_dmac: qos@ff200300 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200300 0x0 0x20>;
+ };
+
+ qos_keyreader: qos@ff200380 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200380 0x0 0x20>;
+ };
+
+ qos_cpu: qos@ff210000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff210000 0x0 0x20>;
+ };
+
+ qos_debug: qos@ff210080 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff210080 0x0 0x20>;
+ };
+
+ qos_gpu_m0: qos@ff220000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff220000 0x0 0x20>;
+ };
+
+ qos_gpu_m1: qos@ff220080 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff220080 0x0 0x20>;
+ };
+
+ qos_pmu_mcu: qos@ff240000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff240000 0x0 0x20>;
+ };
+
+ qos_rkvdec: qos@ff250000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff250000 0x0 0x20>;
+ };
+
+ qos_rkvenc: qos@ff260000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff260000 0x0 0x20>;
+ };
+
+ qos_gmac0: qos@ff270000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270000 0x0 0x20>;
+ };
+
+ qos_hdcp: qos@ff270080 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270080 0x0 0x20>;
+ };
+
+ qos_jpegdec: qos@ff270100 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270100 0x0 0x20>;
+ };
+
+ qos_rga2_m0ro: qos@ff270200 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270200 0x0 0x20>;
+ };
+
+ qos_rga2_m0wo: qos@ff270280 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270280 0x0 0x20>;
+ };
+
+ qos_sdmmc0: qos@ff270300 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270300 0x0 0x20>;
+ };
+
+ qos_usb2host: qos@ff270380 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270380 0x0 0x20>;
+ };
+
+ qos_vdpp: qos@ff270480 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270480 0x0 0x20>;
+ };
+
+ qos_vop: qos@ff270500 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff270500 0x0 0x20>;
+ };
+
+ qos_emmc: qos@ff280000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280000 0x0 0x20>;
+ };
+
+ qos_fspi: qos@ff280080 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280080 0x0 0x20>;
+ };
+
+ qos_gmac1: qos@ff280100 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280100 0x0 0x20>;
+ };
+
+ qos_pcie: qos@ff280180 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280180 0x0 0x20>;
+ };
+
+ qos_sdio0: qos@ff280200 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280200 0x0 0x20>;
+ };
+
+ qos_sdio1: qos@ff280280 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280280 0x0 0x20>;
+ };
+
+ qos_tsp: qos@ff280300 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280300 0x0 0x20>;
+ };
+
+ qos_usb3otg: qos@ff280380 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280380 0x0 0x20>;
+ };
+
+ qos_vpu: qos@ff280400 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff280400 0x0 0x20>;
+ };
+
cru: clock-controller@ff4a0000 {
compatible = "rockchip,rk3528-cru";
reg = <0x0 0xff4a0000 0x0 0x30000>;
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 06/30] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (4 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 05/30] arm64: dts: rockchip: Add rk3528 QoS register node Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:21 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 07/30] arm64: dts: rockchip: Add SARADC node for RK3528 Jonas Karlman
` (23 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman, Heiko Stuebner
From: Chukun Pan <amadeus@jmu.edu.cn>
Same as RK3568, RK3528 uses SCMI clk instead of ARMCLK.
Add SCMI clk for CPU, GPU and RNG will also use it.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Link: https://lore.kernel.org/r/20250307100008.789129-2-amadeus@jmu.edu.cn
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: fbcbc1fb93e14729bd87ab386b7f62694dcc8b51 ]
(cherry picked from commit 6e03c7e28e2d929a420809a24b0379305a9fb86a)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
dts/upstream/src/arm64/rockchip/rk3528.dtsi | 31 +++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
index 0c0e7f151462..4be53868f324 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
@@ -59,6 +59,7 @@
reg = <0x0>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
};
cpu1: cpu@1 {
@@ -66,6 +67,7 @@
reg = <0x1>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
};
cpu2: cpu@2 {
@@ -73,6 +75,7 @@
reg = <0x2>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
};
cpu3: cpu@3 {
@@ -80,6 +83,22 @@
reg = <0x3>;
device_type = "cpu";
enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
+ };
+ };
+
+ firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ arm,smc-id = <0x82000010>;
+ shmem = <&scmi_shmem>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
};
};
@@ -88,6 +107,18 @@
method = "smc";
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scmi_shmem: shmem@10f000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x0010f000 0x0 0x100>;
+ no-map;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 07/30] arm64: dts: rockchip: Add SARADC node for RK3528
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (5 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 06/30] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:21 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 08/30] arm64: dts: rockchip: Add SDHCI controller " Jonas Karlman
` (22 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman, Heiko Stuebner
Add a device tree node for the SARADC controller used by RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250304201642.831218-4-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 6e58302c84ce90aadbecd41efe1f69098a6f91e5 ]
(cherry picked from commit 8ba64ba5cb301bca777ba7f0d2a2a72f49af5ff2)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
dts/upstream/src/arm64/rockchip/rk3528.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
index 4be53868f324..c2eaa0c6ea90 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rockchip,rk3528-cru.h>
+#include <dt-bindings/reset/rockchip,rk3528-cru.h>
/ {
compatible = "rockchip,rk3528";
@@ -455,6 +456,18 @@
status = "disabled";
};
+ saradc: adc@ffae0000 {
+ compatible = "rockchip,rk3528-saradc";
+ reg = <0x0 0xffae0000 0x0 0x10000>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_P_SARADC>;
+ reset-names = "saradc-apb";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3528-pinctrl";
rockchip,grf = <&ioc_grf>;
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 08/30] arm64: dts: rockchip: Add SDHCI controller for RK3528
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (6 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 07/30] arm64: dts: rockchip: Add SARADC node for RK3528 Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:21 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 09/30] arm64: dts: rockchip: Add uart0 pinctrl to Radxa E20C Jonas Karlman
` (21 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman, Heiko Stuebner
The SDHCI controller in Rockchip RK3528 is similar to the one included
in RK3588.
Add device tree node for the SDHCI controller in RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250305214108.1327208-3-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: a98cc47f79ab5b8059b748bf0bd59335edfff7d9 ]
(cherry picked from commit db7a99c423dea0ead19d6a18053d898a762a3b48)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
dts/upstream/src/arm64/rockchip/rk3528.dtsi | 24 +++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
index c2eaa0c6ea90..26c3559d6a6d 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
@@ -468,6 +468,30 @@
status = "disabled";
};
+ sdhci: mmc@ffbf0000 {
+ compatible = "rockchip,rk3528-dwcmshc",
+ "rockchip,rk3588-dwcmshc";
+ reg = <0x0 0xffbf0000 0x0 0x10000>;
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
+ <&cru CCLK_SRC_EMMC>;
+ assigned-clock-rates = <200000000>, <24000000>,
+ <200000000>;
+ clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+ <&cru TCLK_EMMC>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
+ <&emmc_strb>;
+ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
+ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
+ <&cru SRST_T_EMMC>;
+ reset-names = "core", "bus", "axi", "block", "timer";
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3528-pinctrl";
rockchip,grf = <&ioc_grf>;
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 09/30] arm64: dts: rockchip: Add uart0 pinctrl to Radxa E20C
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (7 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 08/30] arm64: dts: rockchip: Add SDHCI controller " Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:22 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 10/30] arm64: dts: rockchip: Add leds node " Jonas Karlman
` (20 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman, Heiko Stuebner
Radxa E20C route UART0 M0 pins (GPIO4_C7 and GPIO4_D0) to the onboard
CH340B for debug console use.
Add pinctrl for UART0 M0 pins used for serial console.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250228064024.3200000-6-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 0d2312f0d3e4ce74af0977c1519a07dfc71a82ac ]
(cherry picked from commit 9bcf6ccdd87c3be48fe7d75150c6e403c5c0a42d)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
index d2cdb63d4a9d..5161d22330ab 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
@@ -18,5 +18,7 @@
};
&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m0_xfer>;
status = "okay";
};
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 10/30] arm64: dts: rockchip: Add leds node to Radxa E20C
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (8 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 09/30] arm64: dts: rockchip: Add uart0 pinctrl to Radxa E20C Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:22 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 11/30] arm64: dts: rockchip: Add user button " Jonas Karlman
` (19 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman, Heiko Stuebner
Radxa E20C has three gpio controlled leds (sys, wan and lan).
Add led nodes and set default trigger to heartbeat for the sys led and
netdev for the lan and wan leds.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250304201642.831218-2-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 6a709e003492e9878d5f1357be0b2e1162e1e6a6 ]
(cherry picked from commit a3556ede6b48c7760ac3608ad77601fca26d2ce0)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
.../src/arm64/rockchip/rk3528-radxa-e20c.dts | 48 +++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
index 5161d22330ab..7f0237206405 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
@@ -6,6 +6,8 @@
*/
/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
#include "rk3528.dtsi"
/ {
@@ -15,6 +17,52 @@
chosen {
stdout-path = "serial0:1500000n8";
};
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lan_led_g>, <&sys_led_g>, <&wan_led_g>;
+
+ led-lan {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "netdev";
+ };
+
+ led-sys {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-wan {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_WAN;
+ gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "netdev";
+ };
+ };
+};
+
+&pinctrl {
+ leds {
+ lan_led_g: lan-led-g {
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ sys_led_g: sys-led-g {
+ rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wan_led_g: wan-led-g {
+ rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
};
&uart0 {
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 11/30] arm64: dts: rockchip: Add user button to Radxa E20C
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (9 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 10/30] arm64: dts: rockchip: Add leds node " Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:22 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 12/30] arm64: dts: rockchip: Add maskrom " Jonas Karlman
` (18 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman, Heiko Stuebner
Radxa E20C has two buttons, one SARADC maskrom button and one GPIO user
button.
Add support for the user button using a gpio-keys node.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250304201642.831218-3-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: ad8afc8813567994164f2720189c819da8c22b99 ]
(cherry picked from commit 6793b56b79df26ab3323e5293b97577d0786ddb3)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
.../src/arm64/rockchip/rk3528-radxa-e20c.dts | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
index 7f0237206405..b378774d2a4e 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
@@ -7,6 +7,7 @@
/dts-v1/;
+#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "rk3528.dtsi"
@@ -18,6 +19,19 @@
stdout-path = "serial0:1500000n8";
};
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_key>;
+
+ button-user {
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+ label = "USER";
+ linux,code = <BTN_1>;
+ wakeup-source;
+ };
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -50,6 +64,12 @@
};
&pinctrl {
+ gpio-keys {
+ user_key: user-key {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
leds {
lan_led_g: lan-led-g {
rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 12/30] arm64: dts: rockchip: Add maskrom button to Radxa E20C
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (10 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 11/30] arm64: dts: rockchip: Add user button " Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:22 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 13/30] arm64: dts: rockchip: Enable onboard eMMC on " Jonas Karlman
` (17 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman, Heiko Stuebner
Radxa E20C has two buttons, one SARADC maskrom button and one GPIO user
button.
Add support for the maskrom button using a adc-keys node, also add the
regulators used by SARADC controller.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250304201642.831218-5-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 3a2819ee9c71d1c6388e456cc4eb042914d15d7e ]
(cherry picked from commit 460ef5b623e5fa69843305faf50f6b1a8e81e1cd)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
.../src/arm64/rockchip/rk3528-radxa-e20c.dts | 48 +++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
index b378774d2a4e..5346ef457c2a 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
@@ -19,6 +19,20 @@
stdout-path = "serial0:1500000n8";
};
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-maskrom {
+ label = "MASKROM";
+ linux,code = <KEY_SETUP>;
+ press-threshold-microvolt = <0>;
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -61,6 +75,35 @@
linux,default-trigger = "netdev";
};
};
+
+ vcc_1v8: regulator-1v8-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ };
+
+ vcc_3v3: regulator-3v3-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: regulator-5v0-vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
};
&pinctrl {
@@ -85,6 +128,11 @@
};
};
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0m0_xfer>;
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 13/30] arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (11 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 12/30] arm64: dts: rockchip: Add maskrom " Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:22 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 14/30] rockchip: mkimage: Add support for RK3528 Jonas Karlman
` (16 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman, Heiko Stuebner
The Radxa E20C may come with an onboard eMMC (8GB / 16GB / 32GB / 64GB).
Enable support for the onboard eMMC on Radxa E20C.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250305214108.1327208-4-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 3a01b5f14a8ae2d45aea5aeed30001ac1655de86 ]
(cherry picked from commit bd4c8a1c08f92d863d89c0ddff59e5f5bc6a1e34)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
.../src/arm64/rockchip/rk3528-radxa-e20c.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
index 5346ef457c2a..57a446b5cbd6 100644
--- a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
+++ b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
@@ -15,6 +15,10 @@
model = "Radxa E20C";
compatible = "radxa,e20c", "rockchip,rk3528";
+ aliases {
+ mmc0 = &sdhci;
+ };
+
chosen {
stdout-path = "serial0:1500000n8";
};
@@ -133,6 +137,17 @@
status = "okay";
};
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ no-sd;
+ no-sdio;
+ non-removable;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0m0_xfer>;
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 14/30] rockchip: mkimage: Add support for RK3528
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (12 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 13/30] arm64: dts: rockchip: Enable onboard eMMC on " Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:22 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 15/30] ram: rockchip: Add basic " Jonas Karlman
` (15 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman, Yifeng Zhao
From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Add support for generating Rockchip Boot Image for RK3528.
Similar to RK3568, the RK3528 has 64 KiB SRAM and 4 KiB of it is
reserved for BootROM.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v2: No change
---
tools/rkcommon.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 3e52236b15a8..f158d1562284 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -134,6 +134,7 @@ static struct spl_info spl_infos[] = {
{ "rk3399", "RK33", 0x30000 - 0x2000, false, RK_HEADER_V1 },
{ "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
{ "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
+ { "rk3528", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
{ "rk3568", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
{ "rk3588", "RK35", 0x100000 - 0x1000, false, RK_HEADER_V2 },
};
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 15/30] ram: rockchip: Add basic support for RK3528
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (13 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 14/30] rockchip: mkimage: Add support for RK3528 Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:22 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 16/30] clk: rockchip: Add " Jonas Karlman
` (14 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman
Add support for reading DRAM size information from PMUGRF os_reg18 reg.
Compared to most Rockchip SoCs the RK3528 use os_reg18 for DRAM info,
instead of os_reg2.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v2: No change
---
arch/arm/mach-rockchip/sdram.c | 3 ++-
drivers/ram/rockchip/Makefile | 1 +
drivers/ram/rockchip/sdram_rk3528.c | 33 +++++++++++++++++++++++++++++
3 files changed, 36 insertions(+), 1 deletion(-)
create mode 100644 drivers/ram/rockchip/sdram_rk3528.c
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 0bdda77a7926..91a6606d461f 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -110,7 +110,8 @@ static int rockchip_dram_init_banksize(void)
u8 i, j;
if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
- !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+ !IS_ENABLED(CONFIG_ROCKCHIP_RK3568) &&
+ !IS_ENABLED(CONFIG_ROCKCHIP_RK3528))
return -ENOTSUPP;
if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index 36dc0500dab5..f222cc99f1e4 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3528) += sdram_rk3528.o
obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o
obj-$(CONFIG_ROCKCHIP_RK3588) += sdram_rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1126) += sdram_rv1126.o sdram_pctl_px30.o
diff --git a/drivers/ram/rockchip/sdram_rk3528.c b/drivers/ram/rockchip/sdram_rk3528.c
new file mode 100644
index 000000000000..89d325bea667
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3528.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+#include <dm.h>
+#include <ram.h>
+#include <asm/arch-rockchip/sdram.h>
+
+#define PMUGRF_BASE 0xff370000
+#define OS_REG18_REG 0x248
+
+static int rk3528_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ info->base = CFG_SYS_SDRAM_BASE;
+ info->size = rockchip_sdram_size(PMUGRF_BASE + OS_REG18_REG);
+
+ return 0;
+}
+
+static struct ram_ops rk3528_dmc_ops = {
+ .get_info = rk3528_dmc_get_info,
+};
+
+static const struct udevice_id rk3528_dmc_ids[] = {
+ { .compatible = "rockchip,rk3528-dmc" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3528_dmc) = {
+ .name = "rockchip_rk3528_dmc",
+ .id = UCLASS_RAM,
+ .of_match = rk3528_dmc_ids,
+ .ops = &rk3528_dmc_ops,
+};
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 16/30] clk: rockchip: Add support for RK3528
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (14 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 15/30] ram: rockchip: Add basic " Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:23 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 17/30] pinctrl: " Jonas Karlman
` (13 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini,
Lukasz Majewski, Sean Anderson
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman, Joseph Chen,
Finley Xiao
From: Joseph Chen <chenjh@rock-chips.com>
Add clock driver for RK3528.
Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with minor
adjustments and fixes for mainline.
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
Changes in v2:
- Use mainline Linux dt-bindings headers and rst-rk3528
- Add TCLK_EMMC, BCLK_EMMC, ACLK_BUS_VOPGL_ROOT and XIN_OSC0_DIV
- Add missing break for CLK_I2C5
---
arch/arm/include/asm/arch-rockchip/clock.h | 17 +
.../include/asm/arch-rockchip/cru_rk3528.h | 388 ++++
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk_pll.c | 23 +-
drivers/clk/rockchip/clk_rk3528.c | 1754 +++++++++++++++++
drivers/reset/Makefile | 2 +-
drivers/reset/rst-rk3528.c | 302 +++
7 files changed, 2480 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3528.h
create mode 100644 drivers/clk/rockchip/clk_rk3528.c
create mode 100644 drivers/reset/rst-rk3528.c
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 73e5283108b1..a9921fbb6e42 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -15,6 +15,13 @@ struct udevice;
#define RKCLK_PLL_MODE_NORMAL 1
#define RKCLK_PLL_MODE_DEEP 2
+/*
+ * PLL flags
+ */
+#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
+/* normal mode only. now only for pll_rk3036, pll_rk3328 type */
+#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
+
enum {
ROCKCHIP_SYSCON_NOC,
ROCKCHIP_SYSCON_GRF,
@@ -207,6 +214,16 @@ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
*/
int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table,
u32 reg_offset, u32 reg_number);
+/*
+ * rk3528_reset_bind_lut() - Bind soft reset device as child of clock device
+ * using dedicated RK3528 lookup table
+ *
+ * @pdev: clock udevice
+ * @reg_offset: the first offset in cru for softreset registers
+ * @reg_number: the reg numbers of softreset registers
+ * Return: 0 success, or error value
+ */
+int rk3528_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number);
/*
* rk3588_reset_bind_lut() - Bind soft reset device as child of clock device
* using dedicated RK3588 lookup table
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3528.h b/arch/arm/include/asm/arch-rockchip/cru_rk3528.h
new file mode 100644
index 000000000000..b4020958a046
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3528.h
@@ -0,0 +1,388 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3528_H
+#define _ASM_ARCH_CRU_RK3528_H
+
+#define MHz 1000000
+#define KHz 1000
+#define OSC_HZ (24 * MHz)
+
+#define CPU_PVTPLL_HZ (1200 * MHz)
+#define APLL_HZ (600 * MHz)
+#define GPLL_HZ (1188 * MHz)
+#define CPLL_HZ (996 * MHz)
+#define PPLL_HZ (1000 * MHz)
+
+/* RK3528 pll id */
+enum rk3528_pll_id {
+ APLL,
+ CPLL,
+ GPLL,
+ PPLL,
+ DPLL,
+ PLL_COUNT,
+};
+
+struct rk3528_clk_priv {
+ struct rk3528_cru *cru;
+ unsigned long ppll_hz;
+ unsigned long gpll_hz;
+ unsigned long cpll_hz;
+ unsigned long armclk_hz;
+ unsigned long armclk_enter_hz;
+ unsigned long armclk_init_hz;
+ bool sync_kernel;
+};
+
+struct rk3528_pll {
+ unsigned int con0;
+ unsigned int con1;
+ unsigned int con2;
+ unsigned int con3;
+ unsigned int con4;
+ unsigned int reserved0[3];
+};
+
+#define RK3528_CRU_BASE ((struct rk3528_cru *)0xff4a0000)
+
+struct rk3528_cru {
+ unsigned int apll_con[5];
+ unsigned int reserved0014[3];
+ unsigned int cpll_con[5];
+ unsigned int reserved0034[11];
+ unsigned int gpll_con[5];
+ unsigned int reserved0074[51 + 32];
+ unsigned int reserved01c0[48];
+ unsigned int mode_con[1];
+ unsigned int reserved0284[31];
+ unsigned int clksel_con[91];
+ unsigned int reserved046c[229];
+ unsigned int gate_con[46];
+ unsigned int reserved08b8[82];
+ unsigned int softrst_con[47];
+ unsigned int reserved0abc[81];
+ unsigned int glb_cnt_th;
+ unsigned int glb_rst_st;
+ unsigned int glb_srst_fst;
+ unsigned int glb_srst_snd;
+ unsigned int glb_rst_con;
+ unsigned int reserved0c14[6];
+ unsigned int corewfi_con;
+ unsigned int reserved0c30[15604];
+
+ /* pmucru */
+ unsigned int reserved10000[192];
+ unsigned int pmuclksel_con[3];
+ unsigned int reserved1030c[317];
+ unsigned int pmugate_con[3];
+ unsigned int reserved1080c[125];
+ unsigned int pmusoftrst_con[3];
+ unsigned int reserved10a08[7550 + 8191];
+
+ /* pciecru */
+ unsigned int reserved20000[32];
+ unsigned int ppll_con[5];
+ unsigned int reserved20094[155];
+ unsigned int pcieclksel_con[2];
+ unsigned int reserved20308[318];
+ unsigned int pciegate_con;
+};
+
+check_member(rk3528_cru, pciegate_con, 0x20800);
+
+struct pll_rate_table {
+ unsigned long rate;
+ unsigned int fbdiv;
+ unsigned int postdiv1;
+ unsigned int refdiv;
+ unsigned int postdiv2;
+ unsigned int dsmpd;
+ unsigned int frac;
+};
+
+#define RK3528_PMU_CRU_BASE 0x10000
+#define RK3528_PCIE_CRU_BASE 0x20000
+#define RK3528_DDRPHY_CRU_BASE 0x28000
+#define RK3528_PLL_CON(x) ((x) * 0x4)
+#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
+#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
+#define RK3528_MODE_CON 0x280
+#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
+#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
+#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
+#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
+
+#define RK3528_DIV_ACLK_M_CORE_SHIFT 11
+#define RK3528_DIV_ACLK_M_CORE_MASK (0x1f << RK3528_DIV_ACLK_M_CORE_SHIFT)
+#define RK3528_DIV_PCLK_DBG_SHIFT 1
+#define RK3528_DIV_PCLK_DBG_MASK (0x1f << RK3528_DIV_PCLK_DBG_SHIFT)
+
+enum {
+ /* CRU_CLKSEL_CON00 */
+ CLK_MATRIX_50M_SRC_DIV_SHIFT = 2,
+ CLK_MATRIX_50M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_50M_SRC_DIV_SHIFT,
+ CLK_MATRIX_100M_SRC_DIV_SHIFT = 7,
+ CLK_MATRIX_100M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_100M_SRC_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON01 */
+ CLK_MATRIX_150M_SRC_DIV_SHIFT = 0,
+ CLK_MATRIX_150M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_150M_SRC_DIV_SHIFT,
+ CLK_MATRIX_200M_SRC_DIV_SHIFT = 5,
+ CLK_MATRIX_200M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_200M_SRC_DIV_SHIFT,
+ CLK_MATRIX_250M_SRC_DIV_SHIFT = 10,
+ CLK_MATRIX_250M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_250M_SRC_DIV_SHIFT,
+ CLK_MATRIX_250M_SRC_SEL_SHIFT = 15,
+ CLK_MATRIX_250M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_250M_SRC_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON02 */
+ CLK_MATRIX_300M_SRC_DIV_SHIFT = 0,
+ CLK_MATRIX_300M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_300M_SRC_DIV_SHIFT,
+ CLK_MATRIX_339M_SRC_DIV_SHIFT = 5,
+ CLK_MATRIX_339M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_339M_SRC_DIV_SHIFT,
+ CLK_MATRIX_400M_SRC_DIV_SHIFT = 10,
+ CLK_MATRIX_400M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_400M_SRC_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON03 */
+ CLK_MATRIX_500M_SRC_DIV_SHIFT = 6,
+ CLK_MATRIX_500M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_500M_SRC_DIV_SHIFT,
+ CLK_MATRIX_500M_SRC_SEL_SHIFT = 11,
+ CLK_MATRIX_500M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_500M_SRC_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON04 */
+ CLK_MATRIX_600M_SRC_DIV_SHIFT = 0,
+ CLK_MATRIX_600M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_600M_SRC_DIV_SHIFT,
+ CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX = 0U,
+ CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX = 1U,
+ CLK_MATRIX_500M_SRC_SEL_CLK_GPLL_MUX = 0U,
+ CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX = 1U,
+
+ /* PMUCRU_CLKSEL_CON00 */
+ CLK_I2C2_SEL_SHIFT = 0,
+ CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT,
+
+ /* PCIE_CRU_CLKSEL_CON01 */
+ PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT = 7,
+ PCIE_CLK_MATRIX_50M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT,
+ PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT = 11,
+ PCIE_CLK_MATRIX_100M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON32 */
+ DCLK_VOP_SRC0_SEL_SHIFT = 10,
+ DCLK_VOP_SRC0_SEL_MASK = 0x1 << DCLK_VOP_SRC0_SEL_SHIFT,
+ DCLK_VOP_SRC0_DIV_SHIFT = 2,
+ DCLK_VOP_SRC0_DIV_MASK = 0xFF << DCLK_VOP_SRC0_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON33 */
+ DCLK_VOP_SRC1_SEL_SHIFT = 8,
+ DCLK_VOP_SRC1_SEL_MASK = 0x1 << DCLK_VOP_SRC1_SEL_SHIFT,
+ DCLK_VOP_SRC1_DIV_SHIFT = 0,
+ DCLK_VOP_SRC1_DIV_MASK = 0xFF << DCLK_VOP_SRC1_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON43 */
+ CLK_CORE_CRYPTO_SEL_SHIFT = 14,
+ CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT,
+ ACLK_BUS_VOPGL_ROOT_DIV_SHIFT = 0U,
+ ACLK_BUS_VOPGL_ROOT_DIV_MASK = 0x7U << ACLK_BUS_VOPGL_ROOT_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON44 */
+ CLK_PWM0_SEL_SHIFT = 6,
+ CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT,
+ CLK_PWM1_SEL_SHIFT = 8,
+ CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
+ CLK_PWM0_SEL_CLK_MATRIX_100M_SRC = 0U,
+ CLK_PWM0_SEL_CLK_MATRIX_50M_SRC = 1U,
+ CLK_PWM0_SEL_XIN_OSC0_FUNC = 2U,
+ CLK_PWM1_SEL_CLK_MATRIX_100M_SRC = 0U,
+ CLK_PWM1_SEL_CLK_MATRIX_50M_SRC = 1U,
+ CLK_PWM1_SEL_XIN_OSC0_FUNC = 2U,
+ CLK_PKA_CRYPTO_SEL_SHIFT = 0,
+ CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT,
+ CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U,
+ CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U,
+ CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U,
+ CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC = 3U,
+ CLK_PKA_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U,
+ CLK_PKA_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U,
+ CLK_PKA_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U,
+ CLK_PKA_CRYPTO_SEL_XIN_OSC0_FUNC = 3U,
+
+ /* CRU_CLKSEL_CON60 */
+ CLK_MATRIX_25M_SRC_DIV_SHIFT = 2,
+ CLK_MATRIX_25M_SRC_DIV_MASK = 0xff << CLK_MATRIX_25M_SRC_DIV_SHIFT,
+ CLK_MATRIX_125M_SRC_DIV_SHIFT = 10,
+ CLK_MATRIX_125M_SRC_DIV_MASK = 0x1f << CLK_MATRIX_125M_SRC_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON61 */
+ SCLK_SFC_DIV_SHIFT = 6,
+ SCLK_SFC_DIV_MASK = 0x3F << SCLK_SFC_DIV_SHIFT,
+ SCLK_SFC_SEL_SHIFT = 12,
+ SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT,
+ SCLK_SFC_SEL_CLK_GPLL_MUX = 0U,
+ SCLK_SFC_SEL_CLK_CPLL_MUX = 1U,
+ SCLK_SFC_SEL_XIN_OSC0_FUNC = 2U,
+
+ /* CRU_CLKSEL_CON62 */
+ CCLK_SRC_EMMC_DIV_SHIFT = 0,
+ CCLK_SRC_EMMC_DIV_MASK = 0x3F << CCLK_SRC_EMMC_DIV_SHIFT,
+ CCLK_SRC_EMMC_SEL_SHIFT = 6,
+ CCLK_SRC_EMMC_SEL_MASK = 0x3 << CCLK_SRC_EMMC_SEL_SHIFT,
+ BCLK_EMMC_SEL_SHIFT = 8,
+ BCLK_EMMC_SEL_MASK = 0x3 << BCLK_EMMC_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON63 */
+ CLK_I2C3_SEL_SHIFT = 12,
+ CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT,
+ CLK_I2C5_SEL_SHIFT = 14,
+ CLK_I2C5_SEL_MASK = 0x3 << CLK_I2C5_SEL_SHIFT,
+ CLK_SPI1_SEL_SHIFT = 10,
+ CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON64 */
+ CLK_I2C6_SEL_SHIFT = 0,
+ CLK_I2C6_SEL_MASK = 0x3 << CLK_I2C6_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON74 */
+ CLK_SARADC_DIV_SHIFT = 0,
+ CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT,
+ CLK_TSADC_DIV_SHIFT = 3,
+ CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT,
+ CLK_TSADC_TSEN_DIV_SHIFT = 8,
+ CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON79 */
+ CLK_I2C1_SEL_SHIFT = 9,
+ CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT,
+ CLK_I2C0_SEL_SHIFT = 11,
+ CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT,
+ CLK_SPI0_SEL_SHIFT = 13,
+ CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON83 */
+ ACLK_VOP_ROOT_DIV_SHIFT = 12,
+ ACLK_VOP_ROOT_DIV_MASK = 0x7 << ACLK_VOP_ROOT_DIV_SHIFT,
+ ACLK_VOP_ROOT_SEL_SHIFT = 15,
+ ACLK_VOP_ROOT_SEL_MASK = 0x1 << ACLK_VOP_ROOT_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON84 */
+ DCLK_VOP0_SEL_SHIFT = 0,
+ DCLK_VOP0_SEL_MASK = 0x1 << DCLK_VOP0_SEL_SHIFT,
+ DCLK_VOP_SRC_SEL_CLK_GPLL_MUX = 0U,
+ DCLK_VOP_SRC_SEL_CLK_CPLL_MUX = 1U,
+ ACLK_VOP_ROOT_SEL_CLK_GPLL_MUX = 0U,
+ ACLK_VOP_ROOT_SEL_CLK_CPLL_MUX = 1U,
+ DCLK_VOP0_SEL_DCLK_VOP_SRC0 = 0U,
+ DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL_IO = 1U,
+
+ /* CRU_CLKSEL_CON85 */
+ CLK_I2C4_SEL_SHIFT = 13,
+ CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT,
+ CLK_I2C7_SEL_SHIFT = 0,
+ CLK_I2C7_SEL_MASK = 0x3 << CLK_I2C7_SEL_SHIFT,
+ CLK_I2C3_SEL_CLK_MATRIX_200M_SRC = 0U,
+ CLK_I2C3_SEL_CLK_MATRIX_100M_SRC = 1U,
+ CLK_I2C3_SEL_CLK_MATRIX_50M_SRC = 2U,
+ CLK_I2C3_SEL_XIN_OSC0_FUNC = 3U,
+ CLK_SPI1_SEL_CLK_MATRIX_200M_SRC = 0U,
+ CLK_SPI1_SEL_CLK_MATRIX_100M_SRC = 1U,
+ CLK_SPI1_SEL_CLK_MATRIX_50M_SRC = 2U,
+ CLK_SPI1_SEL_XIN_OSC0_FUNC = 3U,
+ CCLK_SRC_SDMMC0_DIV_SHIFT = 0,
+ CCLK_SRC_SDMMC0_DIV_MASK = 0x3F << CCLK_SRC_SDMMC0_DIV_SHIFT,
+ CCLK_SRC_SDMMC0_SEL_SHIFT = 6,
+ CCLK_SRC_SDMMC0_SEL_MASK = 0x3 << CCLK_SRC_SDMMC0_SEL_SHIFT,
+ CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX = 0U,
+ CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX = 1U,
+ CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC = 2U,
+ BCLK_EMMC_SEL_CLK_MATRIX_200M_SRC = 0U,
+ BCLK_EMMC_SEL_CLK_MATRIX_100M_SRC = 1U,
+ BCLK_EMMC_SEL_CLK_MATRIX_50M_SRC = 2U,
+ BCLK_EMMC_SEL_XIN_OSC0_FUNC = 3U,
+ CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX = 0U,
+ CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX = 1U,
+ CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC = 2U,
+
+ /* CRU_CLKSEL_CON04 */
+ CLK_UART0_SRC_DIV_SHIFT = 5,
+ CLK_UART0_SRC_DIV_MASK = 0x1F << CLK_UART0_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON05 */
+ CLK_UART0_FRAC_DIV_SHIFT = 0,
+ CLK_UART0_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART0_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON06 */
+ SCLK_UART0_SRC_SEL_SHIFT = 0,
+ SCLK_UART0_SRC_SEL_MASK = 0x3 << SCLK_UART0_SRC_SEL_SHIFT,
+ CLK_UART1_SRC_DIV_SHIFT = 2,
+ CLK_UART1_SRC_DIV_MASK = 0x1F << CLK_UART1_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON07 */
+ CLK_UART1_FRAC_DIV_SHIFT = 0,
+ CLK_UART1_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART1_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON08 */
+ SCLK_UART1_SRC_SEL_SHIFT = 0,
+ SCLK_UART1_SRC_SEL_MASK = 0x3 << SCLK_UART1_SRC_SEL_SHIFT,
+ CLK_UART2_SRC_DIV_SHIFT = 2,
+ CLK_UART2_SRC_DIV_MASK = 0x1F << CLK_UART2_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON09 */
+ CLK_UART2_FRAC_DIV_SHIFT = 0,
+ CLK_UART2_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART2_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON10 */
+ SCLK_UART2_SRC_SEL_SHIFT = 0,
+ SCLK_UART2_SRC_SEL_MASK = 0x3 << SCLK_UART2_SRC_SEL_SHIFT,
+ CLK_UART3_SRC_DIV_SHIFT = 2,
+ CLK_UART3_SRC_DIV_MASK = 0x1F << CLK_UART3_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON11 */
+ CLK_UART3_FRAC_DIV_SHIFT = 0,
+ CLK_UART3_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART3_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON12 */
+ SCLK_UART3_SRC_SEL_SHIFT = 0,
+ SCLK_UART3_SRC_SEL_MASK = 0x3 << SCLK_UART3_SRC_SEL_SHIFT,
+ CLK_UART4_SRC_DIV_SHIFT = 2,
+ CLK_UART4_SRC_DIV_MASK = 0x1F << CLK_UART4_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON13 */
+ CLK_UART4_FRAC_DIV_SHIFT = 0,
+ CLK_UART4_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART4_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON14 */
+ SCLK_UART4_SRC_SEL_SHIFT = 0,
+ SCLK_UART4_SRC_SEL_MASK = 0x3 << SCLK_UART4_SRC_SEL_SHIFT,
+ CLK_UART5_SRC_DIV_SHIFT = 2,
+ CLK_UART5_SRC_DIV_MASK = 0x1F << CLK_UART5_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON15 */
+ CLK_UART5_FRAC_DIV_SHIFT = 0,
+ CLK_UART5_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART5_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON16 */
+ SCLK_UART5_SRC_SEL_SHIFT = 0,
+ SCLK_UART5_SRC_SEL_MASK = 0x3 << SCLK_UART5_SRC_SEL_SHIFT,
+ CLK_UART6_SRC_DIV_SHIFT = 2,
+ CLK_UART6_SRC_DIV_MASK = 0x1F << CLK_UART6_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON17 */
+ CLK_UART6_FRAC_DIV_SHIFT = 0,
+ CLK_UART6_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART6_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON18 */
+ SCLK_UART6_SRC_SEL_SHIFT = 0,
+ SCLK_UART6_SRC_SEL_MASK = 0x3 << SCLK_UART6_SRC_SEL_SHIFT,
+ CLK_UART7_SRC_DIV_SHIFT = 2,
+ CLK_UART7_SRC_DIV_MASK = 0x1F << CLK_UART7_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON19 */
+ CLK_UART7_FRAC_DIV_SHIFT = 0,
+ CLK_UART7_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART7_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON20 */
+ SCLK_UART7_SRC_SEL_SHIFT = 0,
+ SCLK_UART7_SRC_SEL_MASK = 0x3 << SCLK_UART7_SRC_SEL_SHIFT,
+ SCLK_UART0_SRC_SEL_CLK_UART0_SRC = 0U,
+ SCLK_UART0_SRC_SEL_CLK_UART0_FRAC = 1U,
+ SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC = 2U,
+
+ /* CRU_CLKSEL_CON60 */
+ CLK_GMAC1_VPU_25M_DIV_SHIFT = 2,
+ CLK_GMAC1_VPU_25M_DIV_MASK = 0xFF << CLK_GMAC1_VPU_25M_DIV_SHIFT,
+ /* CRU_CLKSEL_CON66 */
+ CLK_GMAC1_SRC_VPU_DIV_SHIFT = 0,
+ CLK_GMAC1_SRC_VPU_DIV_MASK = 0x3F << CLK_GMAC1_SRC_VPU_DIV_SHIFT,
+ /* CRU_CLKSEL_CON84 */
+ CLK_GMAC0_SRC_DIV_SHIFT = 3,
+ CLK_GMAC0_SRC_DIV_MASK = 0x3F << CLK_GMAC0_SRC_DIV_SHIFT,
+};
+
+#endif /* _ASM_ARCH_CRU_RK3528_H */
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 9e379cc2e3b6..70be03164e8f 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o
obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3528) += clk_rk3528.o
obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o
diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c
index 44c6f14618d2..9dec40b1fe83 100644
--- a/drivers/clk/rockchip/clk_pll.c
+++ b/drivers/clk/rockchip/clk_pll.c
@@ -309,9 +309,11 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
* When power on or changing PLL setting,
* we must force PLL into slow mode to ensure output stable clock.
*/
- rk_clrsetreg(base + pll->mode_offset,
- pll->mode_mask << pll->mode_shift,
- RKCLK_PLL_MODE_SLOW << pll->mode_shift);
+ if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
+ rk_clrsetreg(base + pll->mode_offset,
+ pll->mode_mask << pll->mode_shift,
+ RKCLK_PLL_MODE_SLOW << pll->mode_shift);
+ }
/* Power down */
rk_setreg(base + pll->con_offset + 0x4,
@@ -345,8 +347,11 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift)))
udelay(1);
- rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
- RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
+ if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
+ rk_clrsetreg(base + pll->mode_offset,
+ pll->mode_mask << pll->mode_shift,
+ RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
+ }
debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",
pll, readl(base + pll->con_offset),
readl(base + pll->con_offset + 0x4),
@@ -362,12 +367,18 @@ static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll,
u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac;
u32 con = 0, shift, mask;
ulong rate;
+ int mode;
con = readl(base + pll->mode_offset);
shift = pll->mode_shift;
mask = pll->mode_mask << shift;
- switch ((con & mask) >> shift) {
+ if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE))
+ mode = (con & mask) >> shift;
+ else
+ mode = RKCLK_PLL_MODE_NORMAL;
+
+ switch (mode) {
case RKCLK_PLL_MODE_SLOW:
return OSC_HZ;
case RKCLK_PLL_MODE_NORMAL:
diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c
new file mode 100644
index 000000000000..06f20895accf
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3528.c
@@ -0,0 +1,1754 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#include <bitfield.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3528.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rockchip,rk3528-cru.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+
+/*
+ * PLL attention.
+ *
+ * [FRAC PLL]: GPLL, PPLL, DPLL
+ * - frac mode: refdiv can be 1 or 2 only
+ * - int mode: refdiv has no special limit
+ * - VCO range: [950, 3800] MHZ
+ *
+ * [INT PLL]: CPLL, APLL
+ * - int mode: refdiv can be 1 or 2 only
+ * - VCO range: [475, 1900] MHZ
+ *
+ * [PPLL]: normal mode only.
+ *
+ */
+static struct rockchip_pll_rate_table rk3528_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */
+ RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */
+ RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */
+ RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0),
+ RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
+ RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
+ RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0),
+ { /* sentinel */ },
+};
+
+static struct rockchip_pll_clock rk3528_pll_clks[] = {
+ [APLL] = PLL(pll_rk3328, PLL_APLL, RK3528_PLL_CON(0),
+ RK3528_MODE_CON, 0, 10, 0, rk3528_pll_rates),
+
+ [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3528_PLL_CON(8),
+ RK3528_MODE_CON, 2, 10, 0, rk3528_pll_rates),
+
+ [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3528_PLL_CON(24),
+ RK3528_MODE_CON, 4, 10, 0, rk3528_pll_rates),
+
+ [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3528_PCIE_PLL_CON(32),
+ RK3528_MODE_CON, 6, 10, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates),
+
+ [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3528_DDRPHY_PLL_CON(16),
+ RK3528_DDRPHY_MODE_CON, 0, 10, 0, rk3528_pll_rates),
+};
+
+#define RK3528_CPUCLK_RATE(_rate, _aclk_m_core, _pclk_dbg) \
+{ \
+ .rate = _rate##U, \
+ .aclk_div = (_aclk_m_core), \
+ .pclk_div = (_pclk_dbg), \
+}
+
+/* sign-off: _aclk_m_core: 550M, _pclk_dbg: 137.5M, */
+static struct rockchip_cpu_rate_table rk3528_cpu_rates[] = {
+ RK3528_CPUCLK_RATE(1896000000, 1, 13),
+ RK3528_CPUCLK_RATE(1800000000, 1, 12),
+ RK3528_CPUCLK_RATE(1704000000, 1, 11),
+ RK3528_CPUCLK_RATE(1608000000, 1, 11),
+ RK3528_CPUCLK_RATE(1512000000, 1, 11),
+ RK3528_CPUCLK_RATE(1416000000, 1, 9),
+ RK3528_CPUCLK_RATE(1296000000, 1, 8),
+ RK3528_CPUCLK_RATE(1200000000, 1, 8),
+ RK3528_CPUCLK_RATE(1188000000, 1, 8),
+ RK3528_CPUCLK_RATE(1092000000, 1, 7),
+ RK3528_CPUCLK_RATE(1008000000, 1, 6),
+ RK3528_CPUCLK_RATE(1000000000, 1, 6),
+ RK3528_CPUCLK_RATE(996000000, 1, 6),
+ RK3528_CPUCLK_RATE(960000000, 1, 6),
+ RK3528_CPUCLK_RATE(912000000, 1, 6),
+ RK3528_CPUCLK_RATE(816000000, 1, 5),
+ RK3528_CPUCLK_RATE(600000000, 1, 3),
+ RK3528_CPUCLK_RATE(594000000, 1, 3),
+ RK3528_CPUCLK_RATE(408000000, 1, 2),
+ RK3528_CPUCLK_RATE(312000000, 1, 2),
+ RK3528_CPUCLK_RATE(216000000, 1, 1),
+ RK3528_CPUCLK_RATE(96000000, 1, 0),
+};
+
+/*
+ *
+ * rational_best_approximation(31415, 10000,
+ * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+static void rational_best_approximation(unsigned long given_numerator,
+ unsigned long given_denominator,
+ unsigned long max_numerator,
+ unsigned long max_denominator,
+ unsigned long *best_numerator,
+ unsigned long *best_denominator)
+{
+ unsigned long n, d, n0, d0, n1, d1;
+
+ n = given_numerator;
+ d = given_denominator;
+ n0 = 0;
+ d1 = 0;
+ n1 = 1;
+ d0 = 1;
+ for (;;) {
+ unsigned long t, a;
+
+ if (n1 > max_numerator || d1 > max_denominator) {
+ n1 = n0;
+ d1 = d0;
+ break;
+ }
+ if (d == 0)
+ break;
+ t = d;
+ a = n / d;
+ d = n % d;
+ n = t;
+ t = n0 + a * n1;
+ n0 = n1;
+ n1 = t;
+ t = d0 + a * d1;
+ d0 = d1;
+ d1 = t;
+ }
+ *best_numerator = n1;
+ *best_denominator = d1;
+}
+
+static int rk3528_armclk_set_clk(struct rk3528_clk_priv *priv, ulong new_rate)
+{
+ const struct rockchip_cpu_rate_table *rate;
+ struct rk3528_cru *cru = priv->cru;
+ ulong old_rate;
+
+ rate = rockchip_get_cpu_settings(rk3528_cpu_rates, new_rate);
+ if (!rate) {
+ printf("%s unsupported rate\n", __func__);
+ return -EINVAL;
+ }
+
+ /*
+ * set up dependent divisors for DBG and ACLK clocks.
+ */
+ old_rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, APLL);
+ if (old_rate > new_rate) {
+ if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL],
+ priv->cru, APLL, new_rate))
+ return -EINVAL;
+
+ rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
+ rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT);
+
+ rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
+ rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT);
+ } else if (old_rate < new_rate) {
+ rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
+ rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT);
+
+ rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
+ rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT);
+
+ if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL],
+ priv->cru, APLL, new_rate))
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static ulong rk3528_ppll_matrix_get_rate(struct rk3528_clk_priv *priv,
+ ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, mask, shift;
+ void *reg;
+
+ switch (clk_id) {
+ case CLK_PPLL_50M_MATRIX:
+ case CLK_GMAC1_RMII_VPU:
+ mask = PCIE_CLK_MATRIX_50M_SRC_DIV_MASK;
+ shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT;
+ reg = &cru->pcieclksel_con[1];
+ break;
+
+ case CLK_PPLL_100M_MATRIX:
+ mask = PCIE_CLK_MATRIX_100M_SRC_DIV_MASK;
+ shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT;
+ reg = &cru->pcieclksel_con[1];
+ break;
+
+ case CLK_PPLL_125M_MATRIX:
+ case CLK_GMAC1_SRC_VPU:
+ mask = CLK_MATRIX_125M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_125M_SRC_DIV_SHIFT;
+ reg = &cru->clksel_con[60];
+ break;
+
+ case CLK_GMAC1_VPU_25M:
+ mask = CLK_MATRIX_25M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_25M_SRC_DIV_SHIFT;
+ reg = &cru->clksel_con[60];
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ div = (readl(reg) & mask) >> shift;
+
+ return DIV_TO_RATE(priv->ppll_hz, div);
+}
+
+static ulong rk3528_ppll_matrix_set_rate(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, div, mask, shift;
+ u8 is_pciecru = 0;
+
+ switch (clk_id) {
+ case CLK_PPLL_50M_MATRIX:
+ id = 1;
+ mask = PCIE_CLK_MATRIX_50M_SRC_DIV_MASK;
+ shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT;
+ is_pciecru = 1;
+ break;
+
+ case CLK_PPLL_100M_MATRIX:
+ id = 1;
+ mask = PCIE_CLK_MATRIX_100M_SRC_DIV_MASK;
+ shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT;
+ is_pciecru = 1;
+ break;
+
+ case CLK_PPLL_125M_MATRIX:
+ id = 60;
+ mask = CLK_MATRIX_125M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_125M_SRC_DIV_SHIFT;
+ break;
+ case CLK_GMAC1_VPU_25M:
+ id = 60;
+ mask = CLK_MATRIX_25M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_25M_SRC_DIV_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ div = DIV_ROUND_UP(priv->ppll_hz, rate);
+ if (is_pciecru)
+ rk_clrsetreg(&cru->pcieclksel_con[id], mask, (div - 1) << shift);
+ else
+ rk_clrsetreg(&cru->clksel_con[id], mask, (div - 1) << shift);
+
+ return rk3528_ppll_matrix_get_rate(priv, clk_id);
+}
+
+static ulong rk3528_cgpll_matrix_get_rate(struct rk3528_clk_priv *priv,
+ ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 sel, div, mask, shift, con;
+ u32 sel_mask = 0, sel_shift;
+ u8 is_gpll_parent = 1;
+ u8 is_halfdiv = 0;
+ ulong prate;
+
+ switch (clk_id) {
+ case CLK_MATRIX_50M_SRC:
+ con = 0;
+ mask = CLK_MATRIX_50M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_50M_SRC_DIV_SHIFT;
+ is_gpll_parent = 0;
+ break;
+
+ case CLK_MATRIX_100M_SRC:
+ con = 0;
+ mask = CLK_MATRIX_100M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_100M_SRC_DIV_SHIFT;
+ is_gpll_parent = 0;
+ break;
+
+ case CLK_MATRIX_150M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_150M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_150M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_200M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_200M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_200M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_250M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_250M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_250M_SRC_DIV_SHIFT;
+ sel_mask = CLK_MATRIX_250M_SRC_SEL_MASK;
+ sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT;
+ break;
+
+ case CLK_MATRIX_300M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_300M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_300M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_339M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_339M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_339M_SRC_DIV_SHIFT;
+ is_halfdiv = 1;
+ break;
+
+ case CLK_MATRIX_400M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_400M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_400M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_500M_SRC:
+ con = 3;
+ mask = CLK_MATRIX_500M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_500M_SRC_DIV_SHIFT;
+ sel_mask = CLK_MATRIX_500M_SRC_SEL_MASK;
+ sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT;
+ break;
+
+ case CLK_MATRIX_600M_SRC:
+ con = 4;
+ mask = CLK_MATRIX_600M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_600M_SRC_DIV_SHIFT;
+ break;
+
+ case ACLK_BUS_VOPGL_ROOT:
+ case ACLK_BUS_VOPGL_BIU:
+ con = 43;
+ mask = ACLK_BUS_VOPGL_ROOT_DIV_MASK;
+ shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ if (sel_mask) {
+ sel = (readl(&cru->clksel_con[con]) & sel_mask) >> sel_shift;
+ if (sel == CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX) // TODO
+ prate = priv->gpll_hz;
+ else
+ prate = priv->cpll_hz;
+ } else {
+ if (is_gpll_parent)
+ prate = priv->gpll_hz;
+ else
+ prate = priv->cpll_hz;
+ }
+
+ div = (readl(&cru->clksel_con[con]) & mask) >> shift;
+
+ /* NOTE: '-1' to balance the DIV_TO_RATE() 'div+1' */
+ return is_halfdiv ? DIV_TO_RATE(prate * 2, (3 + 2 * div) - 1) : DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3528_cgpll_matrix_set_rate(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 sel, div, mask, shift, con;
+ u32 sel_mask = 0, sel_shift;
+ u8 is_gpll_parent = 1;
+ u8 is_halfdiv = 0;
+ ulong prate = 0;
+
+ switch (clk_id) {
+ case CLK_MATRIX_50M_SRC:
+ con = 0;
+ mask = CLK_MATRIX_50M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_50M_SRC_DIV_SHIFT;
+ is_gpll_parent = 0;
+ break;
+
+ case CLK_MATRIX_100M_SRC:
+ con = 0;
+ mask = CLK_MATRIX_100M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_100M_SRC_DIV_SHIFT;
+ is_gpll_parent = 0;
+ break;
+
+ case CLK_MATRIX_150M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_150M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_150M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_200M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_200M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_200M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_250M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_250M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_250M_SRC_DIV_SHIFT;
+ sel_mask = CLK_MATRIX_250M_SRC_SEL_MASK;
+ sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT;
+ break;
+
+ case CLK_MATRIX_300M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_300M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_300M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_339M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_339M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_339M_SRC_DIV_SHIFT;
+ is_halfdiv = 1;
+ break;
+
+ case CLK_MATRIX_400M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_400M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_400M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_500M_SRC:
+ con = 3;
+ mask = CLK_MATRIX_500M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_500M_SRC_DIV_SHIFT;
+ sel_mask = CLK_MATRIX_500M_SRC_SEL_MASK;
+ sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT;
+ break;
+
+ case CLK_MATRIX_600M_SRC:
+ con = 4;
+ mask = CLK_MATRIX_600M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_600M_SRC_DIV_SHIFT;
+ break;
+
+ case ACLK_BUS_VOPGL_ROOT:
+ case ACLK_BUS_VOPGL_BIU:
+ con = 43;
+ mask = ACLK_BUS_VOPGL_ROOT_DIV_MASK;
+ shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ if (sel_mask) {
+ if (priv->gpll_hz % rate == 0) {
+ sel = CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX; // TODO
+ prate = priv->gpll_hz;
+ } else {
+ sel = CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX;
+ prate = priv->cpll_hz;
+ }
+ } else {
+ if (is_gpll_parent)
+ prate = priv->gpll_hz;
+ else
+ prate = priv->cpll_hz;
+ }
+
+ if (is_halfdiv)
+ /* NOTE: '+1' to balance the following rk_clrsetreg() 'div-1' */
+ div = DIV_ROUND_UP((prate * 2) - (3 * rate), 2 * rate) + 1;
+ else
+ div = DIV_ROUND_UP(prate, rate);
+
+ rk_clrsetreg(&cru->clksel_con[con], mask, (div - 1) << shift);
+ if (sel_mask)
+ rk_clrsetreg(&cru->clksel_con[con], sel_mask, sel << sel_shift);
+
+ return rk3528_cgpll_matrix_get_rate(priv, clk_id);
+}
+
+static ulong rk3528_i2c_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, con, mask, shift;
+ u8 is_pmucru = 0;
+ ulong rate;
+
+ switch (clk_id) {
+ case CLK_I2C0:
+ id = 79;
+ mask = CLK_I2C0_SEL_MASK;
+ shift = CLK_I2C0_SEL_SHIFT;
+ break;
+
+ case CLK_I2C1:
+ id = 79;
+ mask = CLK_I2C1_SEL_MASK;
+ shift = CLK_I2C1_SEL_SHIFT;
+ break;
+
+ case CLK_I2C2:
+ id = 0;
+ mask = CLK_I2C2_SEL_MASK;
+ shift = CLK_I2C2_SEL_SHIFT;
+ is_pmucru = 1;
+ break;
+
+ case CLK_I2C3:
+ id = 63;
+ mask = CLK_I2C3_SEL_MASK;
+ shift = CLK_I2C3_SEL_SHIFT;
+ break;
+
+ case CLK_I2C4:
+ id = 85;
+ mask = CLK_I2C4_SEL_MASK;
+ shift = CLK_I2C4_SEL_SHIFT;
+ break;
+
+ case CLK_I2C5:
+ id = 63;
+ mask = CLK_I2C5_SEL_MASK;
+ shift = CLK_I2C5_SEL_SHIFT;
+ break;
+
+ case CLK_I2C6:
+ id = 64;
+ mask = CLK_I2C6_SEL_MASK;
+ shift = CLK_I2C6_SEL_SHIFT;
+ break;
+
+ case CLK_I2C7:
+ id = 86;
+ mask = CLK_I2C7_SEL_MASK;
+ shift = CLK_I2C7_SEL_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ if (is_pmucru)
+ con = readl(&cru->pmuclksel_con[id]);
+ else
+ con = readl(&cru->clksel_con[id]);
+ sel = (con & mask) >> shift;
+ if (sel == CLK_I2C3_SEL_CLK_MATRIX_200M_SRC)
+ rate = 200 * MHz;
+ else if (sel == CLK_I2C3_SEL_CLK_MATRIX_100M_SRC)
+ rate = 100 * MHz;
+ else if (sel == CLK_I2C3_SEL_CLK_MATRIX_50M_SRC)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+
+ return rate;
+}
+
+static ulong rk3528_i2c_set_clk(struct rk3528_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, mask, shift;
+ u8 is_pmucru = 0;
+
+ if (rate >= 198 * MHz)
+ sel = CLK_I2C3_SEL_CLK_MATRIX_200M_SRC;
+ else if (rate >= 99 * MHz)
+ sel = CLK_I2C3_SEL_CLK_MATRIX_100M_SRC;
+ else if (rate >= 50 * MHz)
+ sel = CLK_I2C3_SEL_CLK_MATRIX_50M_SRC;
+ else
+ sel = CLK_I2C3_SEL_XIN_OSC0_FUNC;
+
+ switch (clk_id) {
+ case CLK_I2C0:
+ id = 79;
+ mask = CLK_I2C0_SEL_MASK;
+ shift = CLK_I2C0_SEL_SHIFT;
+ break;
+
+ case CLK_I2C1:
+ id = 79;
+ mask = CLK_I2C1_SEL_MASK;
+ shift = CLK_I2C1_SEL_SHIFT;
+ break;
+
+ case CLK_I2C2:
+ id = 0;
+ mask = CLK_I2C2_SEL_MASK;
+ shift = CLK_I2C2_SEL_SHIFT;
+ is_pmucru = 1;
+ break;
+
+ case CLK_I2C3:
+ id = 63;
+ mask = CLK_I2C3_SEL_MASK;
+ shift = CLK_I2C3_SEL_SHIFT;
+ break;
+
+ case CLK_I2C4:
+ id = 85;
+ mask = CLK_I2C4_SEL_MASK;
+ shift = CLK_I2C4_SEL_SHIFT;
+ break;
+
+ case CLK_I2C5:
+ id = 63;
+ mask = CLK_I2C5_SEL_MASK;
+ shift = CLK_I2C5_SEL_SHIFT;
+ break;
+
+ case CLK_I2C6:
+ id = 64;
+ mask = CLK_I2C6_SEL_MASK;
+ shift = CLK_I2C6_SEL_SHIFT;
+ break;
+
+ case CLK_I2C7:
+ id = 86;
+ mask = CLK_I2C7_SEL_MASK;
+ shift = CLK_I2C7_SEL_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ if (is_pmucru)
+ rk_clrsetreg(&cru->pmuclksel_con[id], mask, sel << shift);
+ else
+ rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
+
+ return rk3528_i2c_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_spi_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, con, mask, shift;
+ ulong rate;
+
+ switch (clk_id) {
+ case CLK_SPI0:
+ id = 79;
+ mask = CLK_SPI0_SEL_MASK;
+ shift = CLK_SPI0_SEL_SHIFT;
+ break;
+
+ case CLK_SPI1:
+ id = 63;
+ mask = CLK_SPI1_SEL_MASK;
+ shift = CLK_SPI1_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ con = readl(&cru->clksel_con[id]);
+ sel = (con & mask) >> shift;
+ if (sel == CLK_SPI1_SEL_CLK_MATRIX_200M_SRC)
+ rate = 200 * MHz;
+ else if (sel == CLK_SPI1_SEL_CLK_MATRIX_100M_SRC)
+ rate = 100 * MHz;
+ else if (sel == CLK_SPI1_SEL_CLK_MATRIX_50M_SRC)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+
+ return rate;
+}
+
+static ulong rk3528_spi_set_clk(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, mask, shift;
+
+ if (rate >= 198 * MHz)
+ sel = CLK_SPI1_SEL_CLK_MATRIX_200M_SRC;
+ else if (rate >= 99 * MHz)
+ sel = CLK_SPI1_SEL_CLK_MATRIX_100M_SRC;
+ else if (rate >= 50 * MHz)
+ sel = CLK_SPI1_SEL_CLK_MATRIX_50M_SRC;
+ else
+ sel = CLK_SPI1_SEL_XIN_OSC0_FUNC;
+
+ switch (clk_id) {
+ case CLK_SPI0:
+ id = 79;
+ mask = CLK_SPI0_SEL_MASK;
+ shift = CLK_SPI0_SEL_SHIFT;
+ break;
+
+ case CLK_SPI1:
+ id = 63;
+ mask = CLK_SPI1_SEL_MASK;
+ shift = CLK_SPI1_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
+
+ return rk3528_spi_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_pwm_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, con, mask, shift;
+ ulong rate;
+
+ switch (clk_id) {
+ case CLK_PWM0:
+ id = 44;
+ mask = CLK_PWM0_SEL_MASK;
+ shift = CLK_PWM0_SEL_SHIFT;
+ break;
+
+ case CLK_PWM1:
+ id = 44;
+ mask = CLK_PWM1_SEL_MASK;
+ shift = CLK_PWM1_SEL_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ con = readl(&cru->clksel_con[id]);
+ sel = (con & mask) >> shift;
+ if (sel == CLK_PWM0_SEL_CLK_MATRIX_100M_SRC)
+ rate = 100 * MHz;
+ if (sel == CLK_PWM0_SEL_CLK_MATRIX_50M_SRC)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+
+ return rate;
+}
+
+static ulong rk3528_pwm_set_clk(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, mask, shift;
+
+ if (rate >= 99 * MHz)
+ sel = CLK_PWM0_SEL_CLK_MATRIX_100M_SRC;
+ else if (rate >= 50 * MHz)
+ sel = CLK_PWM0_SEL_CLK_MATRIX_50M_SRC;
+ else
+ sel = CLK_PWM0_SEL_XIN_OSC0_FUNC;
+
+ switch (clk_id) {
+ case CLK_PWM0:
+ id = 44;
+ mask = CLK_PWM0_SEL_MASK;
+ shift = CLK_PWM0_SEL_SHIFT;
+ break;
+
+ case CLK_PWM1:
+ id = 44;
+ mask = CLK_PWM1_SEL_MASK;
+ shift = CLK_PWM1_SEL_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
+
+ return rk3528_pwm_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_adc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, con;
+
+ con = readl(&cru->clksel_con[74]);
+ switch (clk_id) {
+ case CLK_SARADC:
+ div = (con & CLK_SARADC_DIV_MASK) >>
+ CLK_SARADC_DIV_SHIFT;
+ break;
+
+ case CLK_TSADC_TSEN:
+ div = (con & CLK_TSADC_TSEN_DIV_MASK) >>
+ CLK_TSADC_TSEN_DIV_SHIFT;
+ break;
+
+ case CLK_TSADC:
+ div = (con & CLK_TSADC_DIV_MASK) >>
+ CLK_TSADC_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3528_adc_set_clk(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, mask, shift;
+
+ switch (clk_id) {
+ case CLK_SARADC:
+ mask = CLK_SARADC_DIV_MASK;
+ shift = CLK_SARADC_DIV_SHIFT;
+ break;
+
+ case CLK_TSADC_TSEN:
+ mask = CLK_TSADC_TSEN_DIV_MASK;
+ shift = CLK_TSADC_TSEN_DIV_SHIFT;
+ break;
+
+ case CLK_TSADC:
+ mask = CLK_TSADC_DIV_MASK;
+ shift = CLK_TSADC_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ rk_clrsetreg(&cru->clksel_con[74], mask, (div - 1) << shift);
+
+ return rk3528_adc_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_sdmmc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, sel, con;
+ ulong prate;
+
+ con = readl(&cru->clksel_con[85]);
+ div = (con & CCLK_SRC_SDMMC0_DIV_MASK) >>
+ CCLK_SRC_SDMMC0_DIV_SHIFT;
+ sel = (con & CCLK_SRC_SDMMC0_SEL_MASK) >>
+ CCLK_SRC_SDMMC0_SEL_SHIFT;
+
+ if (sel == CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX)
+ prate = priv->gpll_hz;
+ else if (sel == CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX)
+ prate = priv->cpll_hz;
+ else
+ prate = OSC_HZ;
+
+ return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3528_sdmmc_set_clk(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, sel;
+
+ if (OSC_HZ % rate == 0) {
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ sel = CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC;
+ } else if ((priv->cpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ sel = CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX;
+ } else {
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ sel = CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX;
+ }
+
+ assert(div - 1 <= 63);
+ rk_clrsetreg(&cru->clksel_con[85],
+ CCLK_SRC_SDMMC0_SEL_MASK |
+ CCLK_SRC_SDMMC0_DIV_MASK,
+ sel << CCLK_SRC_SDMMC0_SEL_SHIFT |
+ (div - 1) << CCLK_SRC_SDMMC0_DIV_SHIFT);
+
+ return rk3528_sdmmc_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_sfc_get_clk(struct rk3528_clk_priv *priv)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, sel, con, parent;
+
+ con = readl(&cru->clksel_con[61]);
+ div = (con & SCLK_SFC_DIV_MASK) >>
+ SCLK_SFC_DIV_SHIFT;
+ sel = (con & SCLK_SFC_SEL_MASK) >>
+ SCLK_SFC_SEL_SHIFT;
+ if (sel == SCLK_SFC_SEL_CLK_GPLL_MUX)
+ parent = priv->gpll_hz;
+ else if (sel == SCLK_SFC_SEL_CLK_CPLL_MUX)
+ parent = priv->cpll_hz;
+ else
+ parent = OSC_HZ;
+
+ return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3528_sfc_set_clk(struct rk3528_clk_priv *priv, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ int div, sel;
+
+ if (OSC_HZ % rate == 0) {
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ sel = SCLK_SFC_SEL_XIN_OSC0_FUNC;
+ } else if ((priv->cpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ sel = SCLK_SFC_SEL_CLK_CPLL_MUX;
+ } else {
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ sel = SCLK_SFC_SEL_CLK_GPLL_MUX;
+ }
+
+ assert(div - 1 <= 63);
+ rk_clrsetreg(&cru->clksel_con[61],
+ SCLK_SFC_SEL_MASK |
+ SCLK_SFC_DIV_MASK,
+ sel << SCLK_SFC_SEL_SHIFT |
+ (div - 1) << SCLK_SFC_DIV_SHIFT);
+
+ return rk3528_sfc_get_clk(priv);
+}
+
+static ulong rk3528_emmc_get_clk(struct rk3528_clk_priv *priv)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, sel, con, parent;
+
+ con = readl(&cru->clksel_con[62]);
+ div = (con & CCLK_SRC_EMMC_DIV_MASK) >>
+ CCLK_SRC_EMMC_DIV_SHIFT;
+ sel = (con & CCLK_SRC_EMMC_SEL_MASK) >>
+ CCLK_SRC_EMMC_SEL_SHIFT;
+
+ if (sel == CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX)
+ parent = priv->gpll_hz;
+ else if (sel == CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX)
+ parent = priv->cpll_hz;
+ else
+ parent = OSC_HZ;
+
+ return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3528_emmc_set_clk(struct rk3528_clk_priv *priv, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, sel;
+
+ if (OSC_HZ % rate == 0) {
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ sel = CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC;
+ } else if ((priv->cpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ sel = CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX;
+ } else {
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ sel = CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX;
+ }
+
+ assert(div - 1 <= 63);
+ rk_clrsetreg(&cru->clksel_con[62],
+ CCLK_SRC_EMMC_SEL_MASK |
+ CCLK_SRC_EMMC_DIV_MASK,
+ sel << CCLK_SRC_EMMC_SEL_SHIFT |
+ (div - 1) << CCLK_SRC_EMMC_DIV_SHIFT);
+
+ return rk3528_emmc_get_clk(priv);
+}
+
+static ulong rk3528_dclk_vop_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div_mask, div_shift;
+ u32 sel_mask, sel_shift;
+ u32 id, con, sel, div;
+ ulong prate;
+
+ switch (clk_id) {
+ case DCLK_VOP0:
+ id = 32;
+ sel_mask = DCLK_VOP_SRC0_SEL_MASK;
+ sel_shift = DCLK_VOP_SRC0_SEL_SHIFT;
+ /* FIXME if need src: clk_hdmiphy_pixel_io */
+ div_mask = DCLK_VOP_SRC0_DIV_MASK;
+ div_shift = DCLK_VOP_SRC0_DIV_SHIFT;
+ break;
+
+ case DCLK_VOP1:
+ id = 33;
+ sel_mask = DCLK_VOP_SRC1_SEL_MASK;
+ sel_shift = DCLK_VOP_SRC1_SEL_SHIFT;
+ div_mask = DCLK_VOP_SRC1_DIV_MASK;
+ div_shift = DCLK_VOP_SRC1_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ con = readl(&cru->clksel_con[id]);
+ div = (con & div_mask) >> div_shift;
+ sel = (con & sel_mask) >> sel_shift;
+ if (sel == DCLK_VOP_SRC_SEL_CLK_GPLL_MUX)
+ prate = priv->gpll_hz;
+ else
+ prate = priv->cpll_hz;
+
+ return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3528_dclk_vop_set_clk(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div_mask, div_shift;
+ u32 sel_mask, sel_shift;
+ u32 id, sel, div;
+ ulong prate;
+
+ switch (clk_id) {
+ case DCLK_VOP0:
+ id = 32;
+ sel_mask = DCLK_VOP_SRC0_SEL_MASK;
+ sel_shift = DCLK_VOP_SRC0_SEL_SHIFT;
+ /* FIXME if need src: clk_hdmiphy_pixel_io */
+ div_mask = DCLK_VOP_SRC0_DIV_MASK;
+ div_shift = DCLK_VOP_SRC0_DIV_SHIFT;
+ break;
+
+ case DCLK_VOP1:
+ id = 33;
+ sel_mask = DCLK_VOP_SRC1_SEL_MASK;
+ sel_shift = DCLK_VOP_SRC1_SEL_SHIFT;
+ div_mask = DCLK_VOP_SRC1_DIV_MASK;
+ div_shift = DCLK_VOP_SRC1_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ if ((priv->gpll_hz % rate) == 0) {
+ prate = priv->gpll_hz;
+ sel = (DCLK_VOP_SRC_SEL_CLK_GPLL_MUX << sel_shift) & sel_mask;
+ } else {
+ prate = priv->cpll_hz;
+ sel = (DCLK_VOP_SRC_SEL_CLK_CPLL_MUX << sel_shift) & sel_mask;
+ }
+
+ div = ((DIV_ROUND_UP(prate, rate) - 1) << div_shift) & div_mask;
+ rk_clrsetreg(&cru->clksel_con[id], sel, div);
+
+ return rk3528_dclk_vop_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_uart_get_rate(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 sel_shift, sel_mask, div_shift, div_mask;
+ u32 sel, id, con, frac_div, div;
+ ulong m, n, rate;
+
+ switch (clk_id) {
+ case SCLK_UART0:
+ id = 6;
+ sel_shift = SCLK_UART0_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART0_SRC_SEL_MASK;
+ div_shift = CLK_UART0_SRC_DIV_SHIFT;
+ div_mask = CLK_UART0_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART1:
+ id = 8;
+ sel_shift = SCLK_UART1_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART1_SRC_SEL_MASK;
+ div_shift = CLK_UART1_SRC_DIV_SHIFT;
+ div_mask = CLK_UART1_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART2:
+ id = 10;
+ sel_shift = SCLK_UART2_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART2_SRC_SEL_MASK;
+ div_shift = CLK_UART2_SRC_DIV_SHIFT;
+ div_mask = CLK_UART2_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART3:
+ id = 12;
+ sel_shift = SCLK_UART3_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART3_SRC_SEL_MASK;
+ div_shift = CLK_UART3_SRC_DIV_SHIFT;
+ div_mask = CLK_UART3_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART4:
+ id = 14;
+ sel_shift = SCLK_UART4_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART4_SRC_SEL_MASK;
+ div_shift = CLK_UART4_SRC_DIV_SHIFT;
+ div_mask = CLK_UART4_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART5:
+ id = 16;
+ sel_shift = SCLK_UART5_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART5_SRC_SEL_MASK;
+ div_shift = CLK_UART5_SRC_DIV_SHIFT;
+ div_mask = CLK_UART5_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART6:
+ id = 18;
+ sel_shift = SCLK_UART6_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART6_SRC_SEL_MASK;
+ div_shift = CLK_UART6_SRC_DIV_SHIFT;
+ div_mask = CLK_UART6_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART7:
+ id = 20;
+ sel_shift = SCLK_UART7_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART7_SRC_SEL_MASK;
+ div_shift = CLK_UART7_SRC_DIV_SHIFT;
+ div_mask = CLK_UART7_SRC_DIV_MASK;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ con = readl(&cru->clksel_con[id - 2]);
+ div = (con & div_mask) >> div_shift;
+
+ con = readl(&cru->clksel_con[id]);
+ sel = (con & sel_mask) >> sel_shift;
+
+ if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_SRC) {
+ rate = DIV_TO_RATE(priv->gpll_hz, div);
+ } else if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_FRAC) {
+ frac_div = readl(&cru->clksel_con[id - 1]);
+ n = (frac_div & 0xffff0000) >> 16;
+ m = frac_div & 0x0000ffff;
+ rate = DIV_TO_RATE(priv->gpll_hz, div) * n / m;
+ } else {
+ rate = OSC_HZ;
+ }
+
+ return rate;
+}
+
+static ulong rk3528_uart_set_rate(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 sel_shift, sel_mask, div_shift, div_mask;
+ u32 sel, id, div;
+ ulong m = 0, n = 0, val;
+
+ if (rate == OSC_HZ) {
+ sel = SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC;
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ } else if (priv->gpll_hz % rate == 0) {
+ sel = SCLK_UART0_SRC_SEL_CLK_UART0_SRC;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ } else {
+ sel = SCLK_UART0_SRC_SEL_CLK_UART0_FRAC;
+ div = 2;
+ rational_best_approximation(rate, priv->gpll_hz / div,
+ GENMASK(16 - 1, 0),
+ GENMASK(16 - 1, 0),
+ &n, &m);
+ }
+
+ switch (clk_id) {
+ case SCLK_UART0:
+ id = 6;
+ sel_shift = SCLK_UART0_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART0_SRC_SEL_MASK;
+ div_shift = CLK_UART0_SRC_DIV_SHIFT;
+ div_mask = CLK_UART0_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART1:
+ id = 8;
+ sel_shift = SCLK_UART1_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART1_SRC_SEL_MASK;
+ div_shift = CLK_UART1_SRC_DIV_SHIFT;
+ div_mask = CLK_UART1_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART2:
+ id = 10;
+ sel_shift = SCLK_UART2_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART2_SRC_SEL_MASK;
+ div_shift = CLK_UART2_SRC_DIV_SHIFT;
+ div_mask = CLK_UART2_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART3:
+ id = 12;
+ sel_shift = SCLK_UART3_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART3_SRC_SEL_MASK;
+ div_shift = CLK_UART3_SRC_DIV_SHIFT;
+ div_mask = CLK_UART3_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART4:
+ id = 14;
+ sel_shift = SCLK_UART4_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART4_SRC_SEL_MASK;
+ div_shift = CLK_UART4_SRC_DIV_SHIFT;
+ div_mask = CLK_UART4_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART5:
+ id = 16;
+ sel_shift = SCLK_UART5_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART5_SRC_SEL_MASK;
+ div_shift = CLK_UART5_SRC_DIV_SHIFT;
+ div_mask = CLK_UART5_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART6:
+ id = 18;
+ sel_shift = SCLK_UART6_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART6_SRC_SEL_MASK;
+ div_shift = CLK_UART6_SRC_DIV_SHIFT;
+ div_mask = CLK_UART6_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART7:
+ id = 20;
+ sel_shift = SCLK_UART7_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART7_SRC_SEL_MASK;
+ div_shift = CLK_UART7_SRC_DIV_SHIFT;
+ div_mask = CLK_UART7_SRC_DIV_MASK;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[id - 2], div_mask, (div - 1) << div_shift);
+ rk_clrsetreg(&cru->clksel_con[id], sel_mask, sel << sel_shift);
+ if (m && n) {
+ val = n << 16 | m;
+ writel(val, &cru->clksel_con[id - 1]);
+ }
+
+ return rk3528_uart_get_rate(priv, clk_id);
+}
+
+static ulong rk3528_clk_get_rate(struct clk *clk)
+{
+ struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong rate = 0;
+
+ if (!priv->gpll_hz || !priv->cpll_hz) {
+ printf("%s: gpll=%lu, cpll=%ld\n",
+ __func__, priv->gpll_hz, priv->cpll_hz);
+ return -ENOENT;
+ }
+
+ switch (clk->id) {
+ case PLL_APLL:
+ case ARMCLK:
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru,
+ APLL);
+ break;
+ case PLL_CPLL:
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], priv->cru,
+ CPLL);
+ break;
+ case PLL_GPLL:
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], priv->cru,
+ GPLL);
+ break;
+
+ case PLL_PPLL:
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], priv->cru,
+ PPLL);
+ break;
+ case PLL_DPLL:
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[DPLL], priv->cru,
+ DPLL);
+ break;
+
+ case TCLK_EMMC:
+ case TCLK_WDT_NS:
+ rate = OSC_HZ;
+ break;
+ case CLK_I2C0:
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C5:
+ case CLK_I2C6:
+ case CLK_I2C7:
+ rate = rk3528_i2c_get_clk(priv, clk->id);
+ break;
+ case CLK_SPI0:
+ case CLK_SPI1:
+ rate = rk3528_spi_get_clk(priv, clk->id);
+ break;
+ case CLK_PWM0:
+ case CLK_PWM1:
+ rate = rk3528_pwm_get_clk(priv, clk->id);
+ break;
+ case CLK_SARADC:
+ case CLK_TSADC:
+ case CLK_TSADC_TSEN:
+ rate = rk3528_adc_get_clk(priv, clk->id);
+ break;
+ case CCLK_SRC_EMMC:
+ rate = rk3528_emmc_get_clk(priv);
+ break;
+ case HCLK_SDMMC0:
+ case CCLK_SRC_SDMMC0:
+ rate = rk3528_sdmmc_get_clk(priv, clk->id);
+ break;
+ case SCLK_SFC:
+ rate = rk3528_sfc_get_clk(priv);
+ break;
+ case DCLK_VOP0:
+ case DCLK_VOP1:
+ rate = rk3528_dclk_vop_get_clk(priv, clk->id);
+ break;
+ case DCLK_CVBS:
+ rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1) / 4;
+ break;
+ case DCLK_4X_CVBS:
+ rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1);
+ break;
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_UART3:
+ case SCLK_UART4:
+ case SCLK_UART5:
+ case SCLK_UART6:
+ case SCLK_UART7:
+ rate = rk3528_uart_get_rate(priv, clk->id);
+ break;
+ case CLK_MATRIX_50M_SRC:
+ case CLK_MATRIX_100M_SRC:
+ case CLK_MATRIX_150M_SRC:
+ case CLK_MATRIX_200M_SRC:
+ case CLK_MATRIX_250M_SRC:
+ case CLK_MATRIX_300M_SRC:
+ case CLK_MATRIX_339M_SRC:
+ case CLK_MATRIX_400M_SRC:
+ case CLK_MATRIX_500M_SRC:
+ case CLK_MATRIX_600M_SRC:
+ case ACLK_BUS_VOPGL_BIU:
+ rate = rk3528_cgpll_matrix_get_rate(priv, clk->id);
+ break;
+ case CLK_PPLL_50M_MATRIX:
+ case CLK_PPLL_100M_MATRIX:
+ case CLK_PPLL_125M_MATRIX:
+ case CLK_GMAC1_VPU_25M:
+ case CLK_GMAC1_RMII_VPU:
+ case CLK_GMAC1_SRC_VPU:
+ rate = rk3528_ppll_matrix_get_rate(priv, clk->id);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+};
+
+static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong ret = 0;
+
+ if (!priv->gpll_hz) {
+ printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
+ return -ENOENT;
+ }
+
+ switch (clk->id) {
+ case PLL_APLL:
+ case ARMCLK:
+ if (priv->armclk_hz)
+ rk3528_armclk_set_clk(priv, rate);
+ priv->armclk_hz = rate;
+ break;
+ case PLL_CPLL:
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru,
+ CPLL, rate);
+ priv->cpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL],
+ priv->cru, CPLL);
+ break;
+ case PLL_GPLL:
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru,
+ GPLL, rate);
+ priv->gpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL],
+ priv->cru, GPLL);
+ break;
+ case PLL_PPLL:
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru,
+ PPLL, rate);
+ priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL],
+ priv->cru, PPLL);
+ break;
+ case TCLK_EMMC:
+ case TCLK_WDT_NS:
+ return (rate == OSC_HZ) ? 0 : -EINVAL;
+ case CLK_I2C0:
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C5:
+ case CLK_I2C6:
+ case CLK_I2C7:
+ ret = rk3528_i2c_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_SPI0:
+ case CLK_SPI1:
+ ret = rk3528_spi_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_PWM0:
+ case CLK_PWM1:
+ ret = rk3528_pwm_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_SARADC:
+ case CLK_TSADC:
+ case CLK_TSADC_TSEN:
+ ret = rk3528_adc_set_clk(priv, clk->id, rate);
+ break;
+ case HCLK_SDMMC0:
+ case CCLK_SRC_SDMMC0:
+ ret = rk3528_sdmmc_set_clk(priv, clk->id, rate);
+ break;
+ case SCLK_SFC:
+ ret = rk3528_sfc_set_clk(priv, rate);
+ break;
+ case CCLK_SRC_EMMC:
+ ret = rk3528_emmc_set_clk(priv, rate);
+ break;
+ case DCLK_VOP0:
+ case DCLK_VOP1:
+ ret = rk3528_dclk_vop_set_clk(priv, clk->id, rate);
+ break;
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_UART3:
+ case SCLK_UART4:
+ case SCLK_UART5:
+ case SCLK_UART6:
+ case SCLK_UART7:
+ ret = rk3528_uart_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_MATRIX_50M_SRC:
+ case CLK_MATRIX_100M_SRC:
+ case CLK_MATRIX_150M_SRC:
+ case CLK_MATRIX_200M_SRC:
+ case CLK_MATRIX_250M_SRC:
+ case CLK_MATRIX_300M_SRC:
+ case CLK_MATRIX_339M_SRC:
+ case CLK_MATRIX_400M_SRC:
+ case CLK_MATRIX_500M_SRC:
+ case CLK_MATRIX_600M_SRC:
+ case ACLK_BUS_VOPGL_BIU:
+ ret = rk3528_cgpll_matrix_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_PPLL_50M_MATRIX:
+ case CLK_PPLL_100M_MATRIX:
+ case CLK_PPLL_125M_MATRIX:
+ case CLK_GMAC1_VPU_25M:
+ ret = rk3528_ppll_matrix_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_GMAC1_RMII_VPU:
+ case CLK_GMAC1_SRC_VPU:
+ /* dummy set */
+ ret = rk3528_ppll_matrix_get_rate(priv, clk->id);
+ break;
+
+ /* Might occur in cru assigned-clocks, can be ignored here */
+ case ACLK_BUS_VOPGL_ROOT:
+ case BCLK_EMMC:
+ case XIN_OSC0_DIV:
+ ret = 0;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return ret;
+};
+
+static struct clk_ops rk3528_clk_ops = {
+ .get_rate = rk3528_clk_get_rate,
+ .set_rate = rk3528_clk_set_rate,
+};
+
+#ifdef CONFIG_XPL_BUILD
+
+#define COREGRF_BASE 0xff300000
+#define PVTPLL_CON0_L 0x0
+#define PVTPLL_CON0_H 0x4
+
+static int rk3528_cpu_pvtpll_set_rate(struct rk3528_clk_priv *priv, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 length;
+
+ if (rate >= 1200000000)
+ length = 8;
+ else if (rate >= 1008000000)
+ length = 11;
+ else
+ length = 17;
+
+ /* set pclk dbg div to 9 */
+ rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
+ 9 << RK3528_DIV_PCLK_DBG_SHIFT);
+ /* set aclk_m_core div to 1 */
+ rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
+ 1 << RK3528_DIV_ACLK_M_CORE_SHIFT);
+
+ /* set ring sel = 1 */
+ writel(0x07000000 | (1 << 8), COREGRF_BASE + PVTPLL_CON0_L);
+ /* set length */
+ writel(0x007f0000 | length, COREGRF_BASE + PVTPLL_CON0_H);
+ /* enable pvtpll */
+ writel(0x00020002, COREGRF_BASE + PVTPLL_CON0_L);
+ /* start monitor */
+ writel(0x00010001, COREGRF_BASE + PVTPLL_CON0_L);
+
+ /* set core mux pvtpll */
+ writel(0x00010001, &cru->clksel_con[40]);
+ writel(0x00100010, &cru->clksel_con[39]);
+
+ /* set pclk dbg div to 8 */
+ rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
+ 8 << RK3528_DIV_PCLK_DBG_SHIFT);
+
+ return 0;
+}
+#endif
+
+static int rk3528_clk_init(struct rk3528_clk_priv *priv)
+{
+ int ret;
+
+ priv->sync_kernel = false;
+
+#ifdef CONFIG_XPL_BUILD
+ /*
+ * BOOTROM:
+ * CPU 1902/2(postdiv1)=546M
+ * CPLL 996/2(postdiv1)=498M
+ * GPLL 1188/2(postdiv1)=594M
+ * |-- clk_matrix_200m_src_div=1 => rate: 300M
+ * |-- clk_matrix_300m_src_div=2 => rate: 200M
+ *
+ * Avoid overclocking when change GPLL rate:
+ * Change clk_matrix_200m_src_div to 5.
+ * Change clk_matrix_300m_src_div to 3.
+ */
+ writel(0x01200120, &priv->cru->clksel_con[1]);
+ writel(0x00030003, &priv->cru->clksel_con[2]);
+
+ if (!priv->armclk_enter_hz) {
+ priv->armclk_enter_hz =
+ rockchip_pll_get_rate(&rk3528_pll_clks[APLL],
+ priv->cru, APLL);
+ priv->armclk_init_hz = priv->armclk_enter_hz;
+ }
+
+ if (priv->armclk_init_hz != APLL_HZ) {
+ ret = rk3528_armclk_set_clk(priv, APLL_HZ);
+ if (!ret)
+ priv->armclk_init_hz = APLL_HZ;
+ }
+
+ if (!rk3528_cpu_pvtpll_set_rate(priv, CPU_PVTPLL_HZ)) {
+ debug("cpu pvtpll %d KHz\n", CPU_PVTPLL_HZ / 1000);
+ priv->armclk_init_hz = CPU_PVTPLL_HZ;
+ }
+#endif
+
+ if (priv->cpll_hz != CPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru,
+ CPLL, CPLL_HZ);
+ if (!ret)
+ priv->cpll_hz = CPLL_HZ;
+ }
+
+ if (priv->gpll_hz != GPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru,
+ GPLL, GPLL_HZ);
+ if (!ret)
+ priv->gpll_hz = GPLL_HZ;
+ }
+
+ if (priv->ppll_hz != PPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru,
+ PPLL, PPLL_HZ);
+ if (!ret)
+ priv->ppll_hz = PPLL_HZ;
+ }
+
+#ifdef CONFIG_XPL_BUILD
+ /* Init to override bootrom config */
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_50M_SRC, 50000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_100M_SRC, 100000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_150M_SRC, 150000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_200M_SRC, 200000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_250M_SRC, 250000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_300M_SRC, 300000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_339M_SRC, 340000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_400M_SRC, 400000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_500M_SRC, 500000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_600M_SRC, 600000000);
+ rk3528_cgpll_matrix_set_rate(priv, ACLK_BUS_VOPGL_BIU, 500000000);
+
+ /* The default rate is 100Mhz, it's not friendly for remote IR module */
+ rk3528_pwm_set_clk(priv, CLK_PWM0, 24000000);
+ rk3528_pwm_set_clk(priv, CLK_PWM1, 24000000);
+#endif
+ return 0;
+}
+
+static int rk3528_clk_probe(struct udevice *dev)
+{
+ struct rk3528_clk_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = rk3528_clk_init(priv);
+ if (ret)
+ return ret;
+
+ /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
+ ret = clk_set_defaults(dev, 1);
+ if (ret)
+ debug("%s clk_set_defaults failed %d\n", __func__, ret);
+ else
+ priv->sync_kernel = true;
+
+ return 0;
+}
+
+static int rk3528_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk3528_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = dev_read_addr_ptr(dev);
+
+ return 0;
+}
+
+static int rk3528_clk_bind(struct udevice *dev)
+{
+ struct udevice *sys_child;
+ struct sysreset_reg *priv;
+ int ret;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rk3528_cru,
+ glb_srst_fst);
+ priv->glb_srst_snd_value = offsetof(struct rk3528_cru,
+ glb_srst_snd);
+ dev_set_priv(sys_child, priv);
+ }
+
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
+ ret = offsetof(struct rk3528_cru, softrst_con[0]);
+ ret = rk3528_reset_bind_lut(dev, ret, 47);
+ if (ret)
+ debug("Warning: software reset driver bind failed\n");
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id rk3528_clk_ids[] = {
+ { .compatible = "rockchip,rk3528-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3528_cru) = {
+ .name = "rockchip_rk3528_cru",
+ .id = UCLASS_CLK,
+ .of_match = rk3528_clk_ids,
+ .priv_auto = sizeof(struct rk3528_clk_priv),
+ .of_to_plat = rk3528_clk_ofdata_to_platdata,
+ .ops = &rk3528_clk_ops,
+ .bind = rk3528_clk_bind,
+ .probe = rk3528_clk_probe,
+};
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index b94943960138..53e7d3730653 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -17,7 +17,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
-obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3588.o
+obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3528.o rst-rk3588.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
diff --git a/drivers/reset/rst-rk3528.c b/drivers/reset/rst-rk3528.c
new file mode 100644
index 000000000000..f6e760d468d9
--- /dev/null
+++ b/drivers/reset/rst-rk3528.c
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Based on Sebastian Reichel's implementation for RK3588
+ */
+
+#include <dm.h>
+#include <asm/arch-rockchip/clock.h>
+#include <dt-bindings/reset/rockchip,rk3528-cru.h>
+
+/* 0xFF4A0000 + 0x0A00 */
+#define RK3528_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
+
+/* mapping table for reset ID to register offset */
+static const int rk3528_register_offset[] = {
+ /* CRU_SOFTRST_CON03 */
+ RK3528_CRU_RESET_OFFSET(SRST_CORE0_PO, 3, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE1_PO, 3, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE2_PO, 3, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE3_PO, 3, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE0, 3, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE1, 3, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE2, 3, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE3, 3, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_NL2, 3, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE_BIU, 3, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE_CRYPTO, 3, 10),
+
+ /* CRU_SOFTRST_CON05 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_DBG, 5, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_POT_DBG, 5, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_NT_DBG, 5, 15),
+
+ /* CRU_SOFTRST_CON06 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 6, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DAPLITE_BIU, 6, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CPU_BIU, 6, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 6, 7),
+
+ /* CRU_SOFTRST_CON08 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_VOPGL_BIU, 8, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_H_BIU, 8, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 8, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 8, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 8, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 8, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DFT2APB, 8, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 8, 15),
+
+ /* CRU_SOFTRST_CON09 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_M_BIU, 9, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_A_GIC, 9, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 9, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_A_DMAC, 9, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_P_TIMER, 9, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER0, 9, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER1, 9, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER2, 9, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER3, 9, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER4, 9, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER5, 9, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_P_JDBCK_DAP, 9, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_JDBCK_DAP, 9, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_P_WDT_NS, 9, 15),
+
+ /* CRU_SOFTRST_CON10 */
+ RK3528_CRU_RESET_OFFSET(SRST_T_WDT_NS, 10, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_H_TRNG_NS, 10, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART0, 10, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART0, 10, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_PKA_CRYPTO, 10, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_A_CRYPTO, 10, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_H_CRYPTO, 10, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 10, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 10, 14),
+
+ /* CRU_SOFTRST_CON11 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_PWM0, 11, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_PWM0, 11, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_P_PWM1, 11, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_PWM1, 11, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_SCR, 11, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_A_DCF, 11, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_P_INTMUX, 11, 12),
+
+ /* CRU_SOFTRST_CON25 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_VPU_BIU, 25, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 25, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VPU_BIU, 25, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_A_VPU, 25, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_H_VPU, 25, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CRU_PCIE, 25, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VPU_GRF, 25, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SFC, 25, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_S_SFC, 25, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_C_EMMC, 25, 15),
+
+ /* CRU_SOFTRST_CON26 */
+ RK3528_CRU_RESET_OFFSET(SRST_H_EMMC, 26, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_A_EMMC, 26, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_B_EMMC, 26, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_T_EMMC, 26, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO1, 26, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO1, 26, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_A_VPU_L_BIU, 26, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VPU_IOC, 26, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S0, 26, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S0, 26, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S2, 26, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S2, 26, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_ACODEC, 26, 13),
+
+ /* CRU_SOFTRST_CON27 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO3, 27, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO3, 27, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_P_SPI1, 27, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_SPI1, 27, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART2, 27, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART2, 27, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART5, 27, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART5, 27, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART6, 27, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART6, 27, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART7, 27, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART7, 27, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C3, 27, 15),
+
+ /* CRU_SOFTRST_CON28 */
+ RK3528_CRU_RESET_OFFSET(SRST_I2C3, 28, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C5, 28, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C5, 28, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C6, 28, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C6, 28, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_A_MAC, 28, 5),
+
+ /* CRU_SOFTRST_CON30 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_PCIE, 30, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_PCIE_PIPE_PHY, 30, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_PCIE_POWER_UP, 30, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_PCIE_PHY, 30, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_PIPE_GRF, 30, 7),
+
+ /* CRU_SOFTRST_CON32 */
+ RK3528_CRU_RESET_OFFSET(SRST_H_SDIO0, 32, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SDIO1, 32, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_TS_0, 32, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_TS_1, 32, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CAN2, 32, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_CAN2, 32, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CAN3, 32, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_CAN3, 32, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_P_SARADC, 32, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_SARADC, 32, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_SARADC_PHY, 32, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_P_TSADC, 32, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_TSADC, 32, 15),
+
+ /* CRU_SOFTRST_CON33 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_USB3OTG, 33, 1),
+
+ /* CRU_SOFTRST_CON34 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 34, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 34, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_A_GPU, 34, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 34, 9),
+
+ /* CRU_SOFTRST_CON36 */
+ RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC_BIU, 36, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC_BIU, 36, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_BIU, 36, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC, 36, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC, 36, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE_RKVENC, 36, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S1, 36, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S1, 36, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C1, 36, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C1, 36, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C0, 36, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C0, 36, 14),
+
+ /* CRU_SOFTRST_CON37 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_SPI0, 37, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_SPI0, 37, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO4, 37, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO4, 37, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_IOC, 37, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SPDIF, 37, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_M_SPDIF, 37, 15),
+
+ /* CRU_SOFTRST_CON38 */
+ RK3528_CRU_RESET_OFFSET(SRST_H_PDM, 38, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_M_PDM, 38, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART1, 38, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART1, 38, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART3, 38, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART3, 38, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_GRF, 38, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CAN0, 38, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_CAN0, 38, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CAN1, 38, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_CAN1, 38, 10),
+
+ /* CRU_SOFTRST_CON39 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_VO_BIU, 39, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_H_VO_BIU, 39, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VO_BIU, 39, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_H_RGA2E, 39, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_A_RGA2E, 39, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE_RGA2E, 39, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_H_VDPP, 39, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_A_VDPP, 39, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE_VDPP, 39, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VO_GRF, 39, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CRU, 39, 15),
+
+ /* CRU_SOFTRST_CON40 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 40, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_H_VOP, 40, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_D_VOP0, 40, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_D_VOP1, 40, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_A_VOP, 40, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_P_HDMI, 40, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_HDMI, 40, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_P_HDMIPHY, 40, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_H_HDCP_KEY, 40, 15),
+
+ /* CRU_SOFTRST_CON41 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_HDCP, 41, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_H_HDCP, 41, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_P_HDCP, 41, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_H_CVBS, 41, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_D_CVBS_VOP, 41, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_D_4X_CVBS_VOP, 41, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 41, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 41, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_A_VO_L_BIU, 41, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_A_MAC_VO, 41, 10),
+
+ /* CRU_SOFTRST_CON42 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 42, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S3, 42, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S3, 42, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_MACPHY, 42, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VCDCPHY, 42, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO2, 42, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO2, 42, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VO_IOC, 42, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SDMMC0, 42, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 42, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 42, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 42, 13),
+
+ /* CRU_SOFTRST_CON43 */
+ RK3528_CRU_RESET_OFFSET(SRST_HDMIHDP0, 43, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST, 43, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST_ARB, 43, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_HOST_UTMI, 43, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART4, 43, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART4, 43, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C4, 43, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C4, 43, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C7, 43, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C7, 43, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_USBPHY, 43, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_USBPHY_POR, 43, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_USBPHY_OTG, 43, 15),
+
+ /* CRU_SOFTRST_CON44 */
+ RK3528_CRU_RESET_OFFSET(SRST_USBPHY_HOST, 44, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY_CRU, 44, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 44, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 44, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC, 44, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC, 44, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 44, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_RKVDEC, 44, 12),
+
+ /* CRU_SOFTRST_CON45 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 45, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDRC, 45, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDRMON, 45, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER_DDRMON, 45, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_P_MSCH_BIU, 45, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 45, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDR_HWLP, 45, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY, 45, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_MSCH_BIU, 45, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL, 45, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_DDR_UPCTL, 45, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_DDRMON, 45, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_A_DDR_SCRAMBLE, 45, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_A_SPLIT, 45, 15),
+
+ /* CRU_SOFTRST_CON46 */
+ RK3528_CRU_RESET_OFFSET(SRST_DDR_PHY, 46, 0),
+};
+
+int rk3528_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number)
+{
+ return rockchip_reset_bind_lut(pdev, rk3528_register_offset,
+ reg_offset, reg_number);
+}
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 17/30] pinctrl: rockchip: Add support for RK3528
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (15 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 16/30] clk: rockchip: Add " Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:23 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 18/30] arm: dts: rockchip: Add rk3528-u-boot.dtsi Jonas Karlman
` (12 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman, Steven Liu
From: Steven Liu <steven.liu@rock-chips.com>
Add pinctrl driver for RK3528.
Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with adjustments
to use regmap_update_bits().
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v2: Change to use if/else if instead of switch to match mainline Linux
---
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3528.c | 273 ++++++++++++++++++++++
2 files changed, 274 insertions(+)
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3528.c
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index c91f650b0434..df6c97d6234b 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o
obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3528.c b/drivers/pinctrl/rockchip/pinctrl-rk3528.c
new file mode 100644
index 000000000000..a3e1f0b2c9d5
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3528.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "pinctrl-rockchip.h"
+#include <dt-bindings/pinctrl/rockchip.h>
+
+static int rk3528_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, mask;
+ u8 bit;
+ u32 data, rmask;
+
+ regmap = priv->regmap_base;
+ reg = bank->iomux[iomux_num].offset;
+ if ((pin % 8) >= 4)
+ reg += 0x4;
+ bit = (pin % 4) * 4;
+ mask = 0xf;
+
+ data = (mask << (bit + 16));
+ rmask = data | (data >> 16);
+ data |= (mux & mask) << bit;
+
+ return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3528_DRV_BITS_PER_PIN 8
+#define RK3528_DRV_PINS_PER_REG 2
+#define RK3528_DRV_GPIO0_OFFSET 0x100
+#define RK3528_DRV_GPIO1_OFFSET 0x20120
+#define RK3528_DRV_GPIO2_OFFSET 0x30160
+#define RK3528_DRV_GPIO3_OFFSET 0x20190
+#define RK3528_DRV_GPIO4_OFFSET 0x101C0
+
+static void rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+
+ if (bank->bank_num == 0) {
+ *reg = RK3528_DRV_GPIO0_OFFSET;
+ } else if (bank->bank_num == 1) {
+ *reg = RK3528_DRV_GPIO1_OFFSET;
+ } else if (bank->bank_num == 2) {
+ *reg = RK3528_DRV_GPIO2_OFFSET;
+ } else if (bank->bank_num == 3) {
+ *reg = RK3528_DRV_GPIO3_OFFSET;
+ } else if (bank->bank_num == 4) {
+ *reg = RK3528_DRV_GPIO4_OFFSET;
+ } else {
+ *reg = 0;
+ debug("unsupported bank_num %d\n", bank->bank_num);
+ }
+
+ *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_DRV_PINS_PER_REG;
+ *bit *= RK3528_DRV_BITS_PER_PIN;
+}
+
+static int rk3528_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg;
+ u32 data, rmask;
+ u8 bit;
+ int drv = (1 << (strength + 1)) - 1;
+
+ rk3528_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3528_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+ rmask = data | (data >> 16);
+ data |= (drv << bit);
+
+ return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3528_PULL_BITS_PER_PIN 2
+#define RK3528_PULL_PINS_PER_REG 8
+#define RK3528_PULL_GPIO0_OFFSET 0x200
+#define RK3528_PULL_GPIO1_OFFSET 0x20210
+#define RK3528_PULL_GPIO2_OFFSET 0x30220
+#define RK3528_PULL_GPIO3_OFFSET 0x20230
+#define RK3528_PULL_GPIO4_OFFSET 0x10240
+
+static void rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+
+ if (bank->bank_num == 0) {
+ *reg = RK3528_PULL_GPIO0_OFFSET;
+ } else if (bank->bank_num == 1) {
+ *reg = RK3528_PULL_GPIO1_OFFSET;
+ } else if (bank->bank_num == 2) {
+ *reg = RK3528_PULL_GPIO2_OFFSET;
+ } else if (bank->bank_num == 3) {
+ *reg = RK3528_PULL_GPIO3_OFFSET;
+ } else if (bank->bank_num == 4) {
+ *reg = RK3528_PULL_GPIO4_OFFSET;
+ } else {
+ *reg = 0;
+ debug("unsupported bank_num %d\n", bank->bank_num);
+ }
+
+ *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_PULL_PINS_PER_REG;
+ *bit *= RK3528_PULL_BITS_PER_PIN;
+}
+
+static int rk3528_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data, rmask;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -EOPNOTSUPP;
+
+ rk3528_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ type = bank->pull_type[pin_num / 8];
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3528_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+ rmask = data | (data >> 16);
+ data |= (ret << bit);
+
+ return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+#define RK3528_SMT_BITS_PER_PIN 1
+#define RK3528_SMT_PINS_PER_REG 8
+#define RK3528_SMT_GPIO0_OFFSET 0x400
+#define RK3528_SMT_GPIO1_OFFSET 0x20410
+#define RK3528_SMT_GPIO2_OFFSET 0x30420
+#define RK3528_SMT_GPIO3_OFFSET 0x20430
+#define RK3528_SMT_GPIO4_OFFSET 0x10440
+
+static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+
+ if (bank->bank_num == 0) {
+ *reg = RK3528_SMT_GPIO0_OFFSET;
+ } else if (bank->bank_num == 1) {
+ *reg = RK3528_SMT_GPIO1_OFFSET;
+ } else if (bank->bank_num == 2) {
+ *reg = RK3528_SMT_GPIO2_OFFSET;
+ } else if (bank->bank_num == 3) {
+ *reg = RK3528_SMT_GPIO3_OFFSET;
+ } else if (bank->bank_num == 4) {
+ *reg = RK3528_SMT_GPIO4_OFFSET;
+ } else {
+ *reg = 0;
+ debug("unsupported bank_num %d\n", bank->bank_num);
+ }
+
+ *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_SMT_PINS_PER_REG;
+ *bit *= RK3528_SMT_BITS_PER_PIN;
+
+ return 0;
+}
+
+static int rk3528_set_schmitt(struct rockchip_pin_bank *bank,
+ int pin_num, int enable)
+{
+ struct regmap *regmap;
+ int reg;
+ u32 data, rmask;
+ u8 bit;
+
+ rk3528_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3528_SMT_BITS_PER_PIN) - 1) << (bit + 16);
+ rmask = data | (data >> 16);
+ data |= (enable << bit);
+
+ return regmap_update_bits(regmap, reg, rmask, data);
+}
+
+static struct rockchip_pin_bank rk3528_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x20020, 0x20028, 0x20030, 0x20038),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x30040, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x20060, 0x20068, 0x20070, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x10080, 0x10088, 0x10090, 0x10098),
+};
+
+static const struct rockchip_pin_ctrl rk3528_pin_ctrl = {
+ .pin_banks = rk3528_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3528_pin_banks),
+ .grf_mux_offset = 0x0,
+ .set_mux = rk3528_set_mux,
+ .set_pull = rk3528_set_pull,
+ .set_drive = rk3528_set_drive,
+ .set_schmitt = rk3528_set_schmitt,
+};
+
+static const struct udevice_id rk3528_pinctrl_ids[] = {
+ {
+ .compatible = "rockchip,rk3528-pinctrl",
+ .data = (ulong)&rk3528_pin_ctrl
+ },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3528_pinctrl) = {
+ .name = "rockchip_rk3528_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3528_pinctrl_ids,
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
+ .ops = &rockchip_pinctrl_ops,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .probe = rockchip_pinctrl_probe,
+};
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 18/30] arm: dts: rockchip: Add rk3528-u-boot.dtsi
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (16 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 17/30] pinctrl: " Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:23 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 19/30] arch: arm: rockchip: Add initial support for RK3528 Jonas Karlman
` (11 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman
Add a rk3528-u-boot.dtsi extending the basic dts/upstream rk3528.dtsi
with bare minimum nodes to have a booting system from eMMC and SD-card.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
Changes in v2:
- Use more nodes from dts/upstream rk3528.dtsi
- Use sdmmc node from latest mainline Linux patch
---
arch/arm/dts/rk3528-u-boot.dtsi | 148 ++++++++++++++++++++++++++++++++
1 file changed, 148 insertions(+)
create mode 100644 arch/arm/dts/rk3528-u-boot.dtsi
diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi
new file mode 100644
index 000000000000..eb6a55cd5c93
--- /dev/null
+++ b/arch/arm/dts/rk3528-u-boot.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rockchip-u-boot.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+ };
+
+ dmc {
+ compatible = "rockchip,rk3528-dmc";
+ bootph-all;
+ };
+
+ soc {
+ rng: rng@ffc50000 {
+ compatible = "rockchip,rkrng";
+ reg = <0x0 0xffc50000 0x0 0x200>;
+ };
+
+ otp: nvmem@ffce0000 {
+ compatible = "rockchip,rk3528-otp";
+ reg = <0x0 0xffce0000 0x0 0x4000>;
+ };
+
+ sdmmc: mmc@ffc30000 {
+ compatible = "rockchip,rk3528-dw-mshc",
+ "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xffc30000 0x0 0x4000>;
+ clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
+ <&sdmmc_det>;
+ resets = <&cru SRST_H_SDMMC0>;
+ reset-names = "reset";
+ rockchip,default-sample-phase = <90>;
+ status = "disabled";
+ };
+ };
+};
+
+&cru {
+ bootph-all;
+};
+
+&emmc_bus8 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_strb {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&gmac0_clk {
+ bootph-all;
+};
+
+&ioc_grf {
+ bootph-all;
+};
+
+&otp {
+ bootph-some-ram;
+};
+
+&pcfg_pull_none {
+ bootph-all;
+};
+
+&pcfg_pull_up {
+ bootph-all;
+};
+
+&pcfg_pull_up_drv_level_2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pinctrl {
+ bootph-all;
+};
+
+&sdhci {
+ bootph-pre-ram;
+ bootph-some-ram;
+ u-boot,spl-fifo-mode;
+};
+
+&sdmmc {
+ bootph-pre-ram;
+ bootph-some-ram;
+ u-boot,spl-fifo-mode;
+};
+
+&sdmmc_bus4 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc_det {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&uart0 {
+ bootph-all;
+ clock-frequency = <24000000>;
+};
+
+&uart0m0_xfer {
+ bootph-pre-sram;
+ bootph-pre-ram;
+};
+
+&xin24m {
+ bootph-all;
+};
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 19/30] arch: arm: rockchip: Add initial support for RK3528
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (17 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 18/30] arm: dts: rockchip: Add rk3528-u-boot.dtsi Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:23 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 20/30] mmc: rockchip_sdhci: Extend variant configuration Jonas Karlman
` (10 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini,
Lukasz Majewski, Mattijs Korpershoek, Marek Vasut
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman
Rockchip RK3528 is a ARM-based SoC with quad-core Cortex-A53.
Add initial arch support for the RK3528 SoC.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
Changes in v2:
- Add FIREWALL_DDR handling to fix emmc/fspi/sdmmc/usb dma
- Add imply SYSRESET_PSCI if SPL_ATF
- Add USB_GADGET_PRODUCT_NUM for RK3528
- Drop ifndef CONFIG_XPL_BUILD in rk3528_common.h
---
arch/arm/include/asm/arch-rk3528/boot0.h | 9 ++
arch/arm/include/asm/arch-rk3528/gpio.h | 9 ++
arch/arm/mach-rockchip/Kconfig | 51 +++++++
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3528/Kconfig | 15 ++
arch/arm/mach-rockchip/rk3528/Makefile | 5 +
arch/arm/mach-rockchip/rk3528/clk_rk3528.c | 16 ++
arch/arm/mach-rockchip/rk3528/rk3528.c | 137 ++++++++++++++++++
arch/arm/mach-rockchip/rk3528/syscon_rk3528.c | 19 +++
drivers/usb/gadget/Kconfig | 1 +
include/configs/rk3528_common.h | 38 +++++
11 files changed, 301 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rk3528/boot0.h
create mode 100644 arch/arm/include/asm/arch-rk3528/gpio.h
create mode 100644 arch/arm/mach-rockchip/rk3528/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3528/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3528/clk_rk3528.c
create mode 100644 arch/arm/mach-rockchip/rk3528/rk3528.c
create mode 100644 arch/arm/mach-rockchip/rk3528/syscon_rk3528.c
create mode 100644 include/configs/rk3528_common.h
diff --git a/arch/arm/include/asm/arch-rk3528/boot0.h b/arch/arm/include/asm/arch-rk3528/boot0.h
new file mode 100644
index 000000000000..8ae46f25a87a
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3528/boot0.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright Contributors to the U-Boot project. */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3528/gpio.h b/arch/arm/include/asm/arch-rk3528/gpio.h
new file mode 100644
index 000000000000..5516e649b80b
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3528/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright Contributors to the U-Boot project. */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index f349431bb43c..be1525848411 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -322,6 +322,56 @@ config ROCKCHIP_RK3399
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+config ROCKCHIP_RK3528
+ bool "Support Rockchip RK3528"
+ select ARM64
+ select SUPPORT_SPL
+ select SPL
+ select CLK
+ select PINCTRL
+ select RAM
+ select REGMAP
+ select SYSCON
+ select BOARD_LATE_INIT
+ select DM_REGULATOR_FIXED
+ select DM_RESET
+ imply ARMV8_CRYPTO
+ imply ARMV8_SET_SMPEN
+ imply BOOTSTD_FULL
+ imply DM_RNG
+ imply FIT
+ imply LEGACY_IMAGE_FORMAT
+ imply MISC
+ imply MISC_INIT_R
+ imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
+ imply OF_LIBFDT_OVERLAY
+ imply OF_LIVE
+ imply OF_UPSTREAM
+ imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
+ imply RNG_ROCKCHIP
+ imply ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_COMMON_STACK_ADDR
+ imply ROCKCHIP_EXTERNAL_TPL
+ imply ROCKCHIP_OTP
+ imply SPL_ATF
+ imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
+ imply SPL_CLK
+ imply SPL_DM_SEQ_ALIAS
+ imply SPL_FIT_SIGNATURE
+ imply SPL_LOAD_FIT
+ imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
+ imply SPL_OF_CONTROL
+ imply SPL_PINCTRL
+ imply SPL_RAM
+ imply SPL_REGMAP
+ imply SPL_SERIAL
+ imply SPL_SYSCON
+ imply SYS_RELOC_GD_ENV_ADDR
+ imply SYSRESET
+ imply SYSRESET_PSCI if SPL_ATF
+ help
+ The Rockchip RK3528 is a ARM-based SoC with a quad-core Cortex-A53.
+
config ROCKCHIP_RK3568
bool "Support Rockchip RK3568"
select ARM64
@@ -652,6 +702,7 @@ source "arch/arm/mach-rockchip/rk3308/Kconfig"
source "arch/arm/mach-rockchip/rk3328/Kconfig"
source "arch/arm/mach-rockchip/rk3368/Kconfig"
source "arch/arm/mach-rockchip/rk3399/Kconfig"
+source "arch/arm/mach-rockchip/rk3528/Kconfig"
source "arch/arm/mach-rockchip/rk3568/Kconfig"
source "arch/arm/mach-rockchip/rk3588/Kconfig"
source "arch/arm/mach-rockchip/rv1108/Kconfig"
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 5e7edc99cdc4..5a7dd5b59400 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
+obj-$(CONFIG_ROCKCHIP_RK3528) += rk3528/
obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
diff --git a/arch/arm/mach-rockchip/rk3528/Kconfig b/arch/arm/mach-rockchip/rk3528/Kconfig
new file mode 100644
index 000000000000..993b2dd274ea
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/Kconfig
@@ -0,0 +1,15 @@
+if ROCKCHIP_RK3528
+
+config ROCKCHIP_BOOT_MODE_REG
+ default 0xff370200
+
+config ROCKCHIP_STIMER_BASE
+ default 0xff620000
+
+config SYS_SOC
+ default "rk3528"
+
+config SYS_CONFIG_NAME
+ default "rk3528_common"
+
+endif
diff --git a/arch/arm/mach-rockchip/rk3528/Makefile b/arch/arm/mach-rockchip/rk3528/Makefile
new file mode 100644
index 000000000000..f0c18cd39d29
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+obj-y += rk3528.o
+obj-y += clk_rk3528.o
+obj-y += syscon_rk3528.o
diff --git a/arch/arm/mach-rockchip/rk3528/clk_rk3528.c b/arch/arm/mach-rockchip/rk3528/clk_rk3528.c
new file mode 100644
index 000000000000..6e77f11cbec0
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/clk_rk3528.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+#include <dm.h>
+#include <asm/arch-rockchip/cru_rk3528.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(rockchip_rk3528_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ return RK3528_CRU_BASE;
+}
diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c
new file mode 100644
index 000000000000..4892ff6ba9d2
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/rk3528.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+#define LOG_CATEGORY LOGC_ARCH
+
+#include <dm.h>
+#include <misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/hardware.h>
+
+#define FIREWALL_DDR_BASE 0xff2e0000
+#define FW_DDR_MST6_REG 0x58
+#define FW_DDR_MST7_REG 0x5c
+#define FW_DDR_MST14_REG 0x78
+#define FW_DDR_MST16_REG 0x80
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@ffbf0000",
+ [BROM_BOOTSOURCE_SD] = "/soc/mmc@ffc30000",
+};
+
+static struct mm_region rk3528_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0xfc000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xfc000000UL,
+ .phys = 0xfc000000UL,
+ .size = 0x04000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rk3528_mem_map;
+
+void board_debug_uart_init(void)
+{
+}
+
+int arch_cpu_init(void)
+{
+ u32 val;
+
+ if (!IS_ENABLED(CONFIG_SPL_BUILD))
+ return 0;
+
+ /* Set the emmc to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
+
+ /* Set the fspi to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
+ writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
+
+ /* Set the sdmmc to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
+
+ /* Set the usb to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
+ writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
+
+ return 0;
+}
+
+#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE
+#define HP_CTRL_REG 0x04
+#define TIMER_EN BIT(0)
+#define HP_LOAD_COUNT0_REG 0x14
+#define HP_LOAD_COUNT1_REG 0x18
+
+void rockchip_stimer_init(void)
+{
+ u32 reg;
+
+ if (!IS_ENABLED(CONFIG_XPL_BUILD))
+ return;
+
+ reg = readl(HP_TIMER_BASE + HP_CTRL_REG);
+ if (reg & TIMER_EN)
+ return;
+
+ asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
+ writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG);
+ writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG);
+ writel(TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG);
+}
+
+#define RK3528_OTP_CPU_CODE_OFFSET 0x02
+#define RK3528_OTP_CPU_CHIP_TYPE_OFFSET 0x28
+
+int checkboard(void)
+{
+ u8 cpu_code[2], chip_type;
+ struct udevice *dev;
+ char suffix[2];
+ int ret;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
+ return 0;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(rockchip_otp), &dev);
+ if (ret) {
+ log_debug("Could not find otp device, ret=%d\n", ret);
+ return 0;
+ }
+
+ /* cpu-code: SoC model, e.g. 0x35 0x28 */
+ ret = misc_read(dev, RK3528_OTP_CPU_CODE_OFFSET, cpu_code, 2);
+ if (ret < 0) {
+ log_debug("Could not read cpu-code, ret=%d\n", ret);
+ return 0;
+ }
+
+ ret = misc_read(dev, RK3528_OTP_CPU_CHIP_TYPE_OFFSET, &chip_type, 1);
+ if (ret < 0) {
+ log_debug("Could not read chip type, ret=%d\n", ret);
+ return 0;
+ }
+
+ suffix[0] = chip_type != 0x1 ? 'A' : '\0';
+ suffix[1] = '\0';
+
+ printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix);
+
+ return 0;
+}
diff --git a/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c b/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c
new file mode 100644
index 000000000000..4a32a5f732e9
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright Contributors to the U-Boot project.
+
+#include <dm.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rk3528_syscon_ids[] = {
+ { .compatible = "rockchip,rk3528-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3528_syscon) = {
+ .name = "rockchip_rk3528_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3528_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
+};
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index c815764c2bc4..46a83141481f 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -85,6 +85,7 @@ config USB_GADGET_PRODUCT_NUM
default 0x330e if ROCKCHIP_RK3308
default 0x350a if ROCKCHIP_RK3568
default 0x350b if ROCKCHIP_RK3588
+ default 0x350c if ROCKCHIP_RK3528
default 0x0
help
Product ID of the USB device emulated, reported to the host device.
diff --git a/include/configs/rk3528_common.h b/include/configs/rk3528_common.h
new file mode 100644
index 000000000000..f7dc6ecd5944
--- /dev/null
+++ b/include/configs/rk3528_common.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* Copyright Contributors to the U-Boot project. */
+
+#ifndef __CONFIG_RK3528_COMMON_H
+#define __CONFIG_RK3528_COMMON_H
+
+#define CFG_CPUID_OFFSET 0xa
+
+#include "rockchip-common.h"
+
+#define CFG_IRAM_BASE 0xfe480000
+
+#define CFG_SYS_SDRAM_BASE 0
+#define SDRAM_MAX_SIZE 0xfc000000
+
+#ifndef ROCKCHIP_DEVICE_SETTINGS
+#define ROCKCHIP_DEVICE_SETTINGS
+#endif
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x00c00000\0" \
+ "script_offset_f=0xffe000\0" \
+ "script_size_f=0x2000\0" \
+ "pxefile_addr_r=0x00e00000\0" \
+ "kernel_addr_r=0x02000000\0" \
+ "kernel_comp_addr_r=0x0a000000\0" \
+ "fdt_addr_r=0x12000000\0" \
+ "fdtoverlay_addr_r=0x12100000\0" \
+ "ramdisk_addr_r=0x12180000\0" \
+ "kernel_comp_size=0x8000000\0"
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ ENV_MEM_LAYOUT_SETTINGS \
+ ROCKCHIP_DEVICE_SETTINGS \
+ "boot_targets=" BOOT_TARGETS "\0"
+
+#endif /* __CONFIG_RK3528_COMMON_H */
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 20/30] mmc: rockchip_sdhci: Extend variant configuration
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (18 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 19/30] arch: arm: rockchip: Add initial support for RK3528 Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:23 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 21/30] mmc: rockchip_sdhci: Add initial support for RK3528 Jonas Karlman
` (9 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Peng Fan,
Jaehoon Chung
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman
RK3528 and RK3576 use different tap and delay num for cmdout and strbin.
Move tap and delay num for cmdout and strbin to driver data to prepare
for adding new SoCs.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v2: No change
---
drivers/mmc/rockchip_sdhci.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index da630b9d97a2..4968404bfaed 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -156,6 +156,9 @@ struct sdhci_data {
u32 flags;
u8 hs200_txclk_tapnum;
u8 hs400_txclk_tapnum;
+ u8 hs400_cmdout_tapnum;
+ u8 hs400_strbin_tapnum;
+ u8 ddr50_strbin_delay_num;
};
static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
@@ -348,7 +351,7 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
extra = DLL_CMDOUT_SRC_CLK_NEG |
DLL_CMDOUT_BOTH_CLK_EDGE |
DWCMSHC_EMMC_DLL_DLYENA |
- DLL_CMDOUT_TAPNUM_90_DEGREES |
+ data->hs400_cmdout_tapnum |
DLL_CMDOUT_TAPNUM_FROM_SW;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CMDOUT);
}
@@ -360,7 +363,7 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
extra = DWCMSHC_EMMC_DLL_DLYENA |
- DLL_STRBIN_TAPNUM_DEFAULT |
+ data->hs400_strbin_tapnum |
DLL_STRBIN_TAPNUM_FROM_SW;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
} else {
@@ -380,7 +383,7 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
*/
extra = DWCMSHC_EMMC_DLL_DLYENA |
DLL_STRBIN_DELAY_NUM_SEL |
- DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
+ data->ddr50_strbin_delay_num << DLL_STRBIN_DELAY_NUM_OFFSET;
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
}
@@ -654,6 +657,9 @@ static const struct sdhci_data rk3568_data = {
.flags = FLAG_INVERTER_FLAG_IN_RXCLK,
.hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
.hs400_txclk_tapnum = 0x8,
+ .hs400_cmdout_tapnum = DLL_CMDOUT_TAPNUM_90_DEGREES,
+ .hs400_strbin_tapnum = DLL_STRBIN_TAPNUM_DEFAULT,
+ .ddr50_strbin_delay_num = DLL_STRBIN_DELAY_NUM_DEFAULT,
};
static const struct sdhci_data rk3588_data = {
@@ -662,6 +668,9 @@ static const struct sdhci_data rk3588_data = {
.config_dll = rk3568_sdhci_config_dll,
.hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
.hs400_txclk_tapnum = 0x9,
+ .hs400_cmdout_tapnum = DLL_CMDOUT_TAPNUM_90_DEGREES,
+ .hs400_strbin_tapnum = DLL_STRBIN_TAPNUM_DEFAULT,
+ .ddr50_strbin_delay_num = DLL_STRBIN_DELAY_NUM_DEFAULT,
};
static const struct udevice_id sdhci_ids[] = {
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 21/30] mmc: rockchip_sdhci: Add initial support for RK3528
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (19 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 20/30] mmc: rockchip_sdhci: Extend variant configuration Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:23 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 22/30] mmc: rockchip_sdhci: Gate clock for glitch free phase switching Jonas Karlman
` (8 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Peng Fan,
Jaehoon Chung
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman
Add initial support for SDHCI controller in RK3528.
Only MMC Legacy and MMC High Speed (52MHz) mode is supported after this,
more work is needed to get the faster HS200/HS400/HS400ES modes working.
Variant tap and delay num is copied from vendor Linux tag
linux-6.1-stan-rkr5.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v2: No change
---
drivers/mmc/rockchip_sdhci.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 4968404bfaed..2c54b8a942da 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -650,6 +650,17 @@ static const struct sdhci_data rk3399_data = {
.set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe,
};
+static const struct sdhci_data rk3528_data = {
+ .set_ios_post = rk3568_sdhci_set_ios_post,
+ .set_clock = rk3568_sdhci_set_clock,
+ .config_dll = rk3568_sdhci_config_dll,
+ .hs200_txclk_tapnum = 0xc,
+ .hs400_txclk_tapnum = 0x6,
+ .hs400_cmdout_tapnum = 0x6,
+ .hs400_strbin_tapnum = 0x3,
+ .ddr50_strbin_delay_num = 0xa,
+};
+
static const struct sdhci_data rk3568_data = {
.set_ios_post = rk3568_sdhci_set_ios_post,
.set_clock = rk3568_sdhci_set_clock,
@@ -678,6 +689,10 @@ static const struct udevice_id sdhci_ids[] = {
.compatible = "arasan,sdhci-5.1",
.data = (ulong)&rk3399_data,
},
+ {
+ .compatible = "rockchip,rk3528-dwcmshc",
+ .data = (ulong)&rk3528_data,
+ },
{
.compatible = "rockchip,rk3568-dwcmshc",
.data = (ulong)&rk3568_data,
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 22/30] mmc: rockchip_sdhci: Gate clock for glitch free phase switching
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (20 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 21/30] mmc: rockchip_sdhci: Add initial support for RK3528 Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:23 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 23/30] rockchip: otp: Add support for RK3528 Jonas Karlman
` (7 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Peng Fan,
Jaehoon Chung
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman
Enable clock stopping to gate clock during phase code change to ensure
glitch free phase switching in auto-tuning circuit. Fixes HS200 mode
on RK3528.
POST_CHANGE_DLY
Time taken for phase switching and stable clock output.
- Less than 4-cycle latency
PRE_CHANGE_DLY
Maximum Latency specification between transmit clock and receive clock.
- Less than 4-cycle latency
TUNE_CLK_STOP_EN
Clock stopping control for Tuning and auto-tuning circuit. When enabled,
clock gate control output is pulled low before changing phase select
codes. This effectively stops the receive clock. Changing phase code
when clocks are stopped ensures glitch free phase switching.
- Clocks stopped during phase code change
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v2: No change
---
drivers/mmc/rockchip_sdhci.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 2c54b8a942da..c0f986784366 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -50,6 +50,10 @@
#define DWCMSHC_EMMC_EMMC_CTRL 0x52c
#define DWCMSHC_CARD_IS_EMMC BIT(0)
#define DWCMSHC_ENHANCED_STROBE BIT(8)
+#define DWCMSHC_EMMC_AT_CTRL 0x540
+#define EMMC_AT_CTRL_TUNE_CLK_STOP_EN BIT(16)
+#define EMMC_AT_CTRL_PRE_CHANGE_DLY 17
+#define EMMC_AT_CTRL_POST_CHANGE_DLY 19
#define DWCMSHC_EMMC_DLL_CTRL 0x800
#define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
#define DWCMSHC_EMMC_DLL_RXCLK 0x804
@@ -326,6 +330,11 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
udelay(1);
sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
+ extra = 0x3 << EMMC_AT_CTRL_POST_CHANGE_DLY |
+ 0x3 << EMMC_AT_CTRL_PRE_CHANGE_DLY |
+ EMMC_AT_CTRL_TUNE_CLK_STOP_EN;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_AT_CTRL);
+
/* Init DLL settings */
extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC |
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 23/30] rockchip: otp: Add support for RK3528
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (21 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 22/30] mmc: rockchip_sdhci: Gate clock for glitch free phase switching Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:23 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 24/30] adc: rockchip-saradc: " Jonas Karlman
` (6 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman
Add support for the OTP controller in RK3528. The OTPC is similar to the
OTPC in RK3568 and can use the same ops for reading OTP data.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v2: New patch
---
drivers/misc/rockchip-otp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/misc/rockchip-otp.c b/drivers/misc/rockchip-otp.c
index 2123c31038fc..b5597de39aca 100644
--- a/drivers/misc/rockchip-otp.c
+++ b/drivers/misc/rockchip-otp.c
@@ -383,6 +383,10 @@ static const struct udevice_id rockchip_otp_ids[] = {
.compatible = "rockchip,rk3308-otp",
.data = (ulong)&px30_data,
},
+ {
+ .compatible = "rockchip,rk3528-otp",
+ .data = (ulong)&rk3568_data,
+ },
{
.compatible = "rockchip,rk3568-otp",
.data = (ulong)&rk3568_data,
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 24/30] adc: rockchip-saradc: Add support for RK3528
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (22 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 23/30] rockchip: otp: Add support for RK3528 Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:24 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 25/30] rng: rockchip: Add support for rkrng variant Jonas Karlman
` (5 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman
The Successive Approximation ADC (SARADC) in RK3528 uses the v2
controller and support:
- 10-bit resolution
- Up to 1MS/s sampling rate
- 4 single-ended input channels
- Current consumption: 0.5mA @ 1MS/s
Add support for the 4 channels of 10-bit resolution supported by SARADC
in RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v2: New patch
---
drivers/adc/rockchip-saradc.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c
index 7cf9735f60d0..1515951403c9 100644
--- a/drivers/adc/rockchip-saradc.c
+++ b/drivers/adc/rockchip-saradc.c
@@ -339,6 +339,14 @@ static const struct rockchip_saradc_data rk3399_saradc_data = {
.stop = rockchip_saradc_stop_v1,
};
+static const struct rockchip_saradc_data rk3528_saradc_data = {
+ .num_bits = 10,
+ .num_channels = 4,
+ .clk_rate = 1000000,
+ .channel_data = rockchip_saradc_channel_data_v2,
+ .start_channel = rockchip_saradc_start_channel_v2,
+};
+
static const struct rockchip_saradc_data rk3588_saradc_data = {
.num_bits = 12,
.num_channels = 8,
@@ -354,6 +362,8 @@ static const struct udevice_id rockchip_saradc_ids[] = {
.data = (ulong)&rk3066_tsadc_data },
{ .compatible = "rockchip,rk3399-saradc",
.data = (ulong)&rk3399_saradc_data },
+ { .compatible = "rockchip,rk3528-saradc",
+ .data = (ulong)&rk3528_saradc_data },
{ .compatible = "rockchip,rk3588-saradc",
.data = (ulong)&rk3588_saradc_data },
{ }
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 25/30] rng: rockchip: Add support for rkrng variant
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (23 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 24/30] adc: rockchip-saradc: " Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:24 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 26/30] phy: rockchip-inno-usb2: Add support for clkout_ctl_phy Jonas Karlman
` (4 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Sughosh Ganu,
Heinrich Schuchardt
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman, Lin Jinhan
From: Lin Jinhan <troy.lin@rock-chips.com>
Add support for rkrng variant, used by e.g. RK3528 and RK3576.
Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with minor
adjustments for mainline.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v2: Rebase on "rockchip: Update rng compatible for RK356x and RK3588"
---
drivers/rng/rockchip_rng.c | 73 ++++++++++++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c
index 6e4e3abf08c8..d854ea900442 100644
--- a/drivers/rng/rockchip_rng.c
+++ b/drivers/rng/rockchip_rng.c
@@ -70,6 +70,27 @@
#define TRNG_v1_VERSION_CODE 0x46BC
/* end of TRNG V1 register define */
+/* start of RKRNG register define */
+#define RKRNG_CTRL 0x0010
+#define RKRNG_CTRL_INST_REQ BIT(0)
+#define RKRNG_CTRL_RESEED_REQ BIT(1)
+#define RKRNG_CTRL_TEST_REQ BIT(2)
+#define RKRNG_CTRL_SW_DRNG_REQ BIT(3)
+#define RKRNG_CTRL_SW_TRNG_REQ BIT(4)
+
+#define RKRNG_STATE 0x0014
+#define RKRNG_STATE_INST_ACK BIT(0)
+#define RKRNG_STATE_RESEED_ACK BIT(1)
+#define RKRNG_STATE_TEST_ACK BIT(2)
+#define RKRNG_STATE_SW_DRNG_ACK BIT(3)
+#define RKRNG_STATE_SW_TRNG_ACK BIT(4)
+
+/* DRNG_DATA_0 ~ DNG_DATA_7 */
+#define RKRNG_DRNG_DATA_0 0x0070
+#define RKRNG_DRNG_DATA_7 0x008C
+
+/* end of RKRNG register define */
+
#define RK_RNG_TIME_OUT 50000 /* max 50ms */
#define trng_write(pdata, pos, val) writel(val, (pdata)->base + (pos))
@@ -228,6 +249,49 @@ exit:
return retval;
}
+static int rkrng_init(struct udevice *dev)
+{
+ struct rk_rng_plat *pdata = dev_get_priv(dev);
+ u32 reg = 0;
+
+ rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff);
+
+ reg = trng_read(pdata, RKRNG_STATE);
+ trng_write(pdata, RKRNG_STATE, reg);
+
+ return 0;
+}
+
+static int rkrng_rng_read(struct udevice *dev, void *data, size_t len)
+{
+ struct rk_rng_plat *pdata = dev_get_priv(dev);
+ u32 reg = 0;
+ int retval;
+
+ if (len > RK_HW_RNG_MAX)
+ return -EINVAL;
+
+ reg = RKRNG_CTRL_SW_DRNG_REQ;
+
+ rk_clrsetreg(pdata->base + RKRNG_CTRL, 0xffff, reg);
+
+ retval = readl_poll_timeout(pdata->base + RKRNG_STATE, reg,
+ (reg & RKRNG_STATE_SW_DRNG_ACK),
+ RK_RNG_TIME_OUT);
+ if (retval)
+ goto exit;
+
+ trng_write(pdata, RKRNG_STATE, reg);
+
+ rk_rng_read_regs(pdata->base + RKRNG_DRNG_DATA_0, data, len);
+
+exit:
+ /* close TRNG */
+ rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff);
+
+ return retval;
+}
+
static int rockchip_rng_read(struct udevice *dev, void *data, size_t len)
{
unsigned char *buf = data;
@@ -295,6 +359,11 @@ static const struct rk_rng_soc_data rk_trngv1_soc_data = {
.rk_rng_read = rk_trngv1_rng_read,
};
+static const struct rk_rng_soc_data rkrng_soc_data = {
+ .rk_rng_init = rkrng_init,
+ .rk_rng_read = rkrng_rng_read,
+};
+
static const struct dm_rng_ops rockchip_rng_ops = {
.read = rockchip_rng_read,
};
@@ -324,6 +393,10 @@ static const struct udevice_id rockchip_rng_match[] = {
.compatible = "rockchip,rk3588-rng",
.data = (ulong)&rk_trngv1_soc_data,
},
+ {
+ .compatible = "rockchip,rkrng",
+ .data = (ulong)&rkrng_soc_data,
+ },
{},
};
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 26/30] phy: rockchip-inno-usb2: Add support for clkout_ctl_phy
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (24 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 25/30] rng: rockchip: Add support for rkrng variant Jonas Karlman
@ 2025-04-07 22:46 ` Jonas Karlman
2025-04-08 3:24 ` Kever Yang
2025-04-07 22:47 ` [PATCH v2 27/30] phy: rockchip-inno-usb2: Add support for RK3528 Jonas Karlman
` (3 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:46 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman
The 480m clk is controlled using regs in the PHY address space and not
in the USB GRF address space on e.g. RK3528 and RK3506.
Add a clkout_ctl_phy usb2phy_reg to handle enable/disable of the 480m
clk on these SoCs.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v2: New patch
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 43 ++++++++++++++-----
1 file changed, 33 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 43f6e020a6a0..f40a86bc9dae 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -40,11 +40,13 @@ struct rockchip_usb2phy_port_cfg {
struct rockchip_usb2phy_cfg {
unsigned int reg;
struct usb2phy_reg clkout_ctl;
+ struct usb2phy_reg clkout_ctl_phy;
const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
};
struct rockchip_usb2phy {
struct regmap *reg_base;
+ struct regmap *phy_base;
struct clk phyclk;
const struct rockchip_usb2phy_cfg *phy_cfg;
};
@@ -165,6 +167,22 @@ static struct phy_ops rockchip_usb2phy_ops = {
.of_xlate = rockchip_usb2phy_of_xlate,
};
+static void rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base,
+ const struct usb2phy_reg **clkout_ctl)
+{
+ struct udevice *parent = dev_get_parent(clk->dev);
+ struct rockchip_usb2phy *priv = dev_get_priv(parent);
+ const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
+
+ if (priv->phy_cfg->clkout_ctl_phy.enable) {
+ *base = priv->phy_base;
+ *clkout_ctl = &phy_cfg->clkout_ctl_phy;
+ } else {
+ *base = priv->reg_base;
+ *clkout_ctl = &phy_cfg->clkout_ctl;
+ }
+}
+
/**
* round_rate() - Adjust a rate to the exact rate a clock can provide.
* @clk: The clock to manipulate.
@@ -185,13 +203,14 @@ ulong rockchip_usb2phy_clk_round_rate(struct clk *clk, ulong rate)
*/
int rockchip_usb2phy_clk_enable(struct clk *clk)
{
- struct udevice *parent = dev_get_parent(clk->dev);
- struct rockchip_usb2phy *priv = dev_get_priv(parent);
- const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
+ const struct usb2phy_reg *clkout_ctl;
+ struct regmap *base;
+
+ rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);
/* turn on 480m clk output if it is off */
- if (!property_enabled(priv->reg_base, &phy_cfg->clkout_ctl)) {
- property_enable(priv->reg_base, &phy_cfg->clkout_ctl, true);
+ if (!property_enabled(base, clkout_ctl)) {
+ property_enable(base, clkout_ctl, true);
/* waiting for the clk become stable */
usleep_range(1200, 1300);
@@ -208,12 +227,13 @@ int rockchip_usb2phy_clk_enable(struct clk *clk)
*/
int rockchip_usb2phy_clk_disable(struct clk *clk)
{
- struct udevice *parent = dev_get_parent(clk->dev);
- struct rockchip_usb2phy *priv = dev_get_priv(parent);
- const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
+ const struct usb2phy_reg *clkout_ctl;
+ struct regmap *base;
+
+ rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);
/* turn off 480m clk output */
- property_enable(priv->reg_base, &phy_cfg->clkout_ctl, false);
+ property_enable(base, clkout_ctl, false);
return 0;
}
@@ -281,7 +301,10 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
return ret;
}
- return 0;
+ if (priv->phy_cfg->clkout_ctl_phy.enable)
+ ret = regmap_init_mem_index(dev_ofnode(dev), &priv->phy_base, 0);
+
+ return ret;
}
static int rockchip_usb2phy_bind(struct udevice *dev)
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 27/30] phy: rockchip-inno-usb2: Add support for RK3528
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (25 preceding siblings ...)
2025-04-07 22:46 ` [PATCH v2 26/30] phy: rockchip-inno-usb2: Add support for clkout_ctl_phy Jonas Karlman
@ 2025-04-07 22:47 ` Jonas Karlman
2025-04-08 3:24 ` Kever Yang
2025-04-07 22:47 ` [PATCH v2 28/30] net: dwc_eth_qos_rockchip: " Jonas Karlman
` (2 subsequent siblings)
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:47 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman
Add support for the two USB2.0 PHYs use in the RK3528 SoC.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v2: New patch
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index f40a86bc9dae..88b33de1b2a0 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -412,6 +412,22 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
{ /* sentinel */ }
};
+static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
+ {
+ .reg = 0xffdf0000,
+ .clkout_ctl_phy = { 0x041c, 7, 2, 0, 0x27 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x004c, 1, 0, 2, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0x005c, 1, 0, 2, 1 },
+ }
+ },
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
{
.reg = 0xfe8a0000,
@@ -493,6 +509,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = {
.compatible = "rockchip,rk3399-usb2phy",
.data = (ulong)&rk3399_usb2phy_cfgs,
},
+ {
+ .compatible = "rockchip,rk3528-usb2phy",
+ .data = (ulong)&rk3528_phy_cfgs,
+ },
{
.compatible = "rockchip,rk3568-usb2phy",
.data = (ulong)&rk3568_phy_cfgs,
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 28/30] net: dwc_eth_qos_rockchip: Add support for RK3528
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (26 preceding siblings ...)
2025-04-07 22:47 ` [PATCH v2 27/30] phy: rockchip-inno-usb2: Add support for RK3528 Jonas Karlman
@ 2025-04-07 22:47 ` Jonas Karlman
2025-04-08 3:24 ` Kever Yang
2025-04-07 22:47 ` [PATCH v2 29/30] board: rockchip: Add minimal generic RK3528 board Jonas Karlman
2025-04-07 22:47 ` [PATCH v2 30/30] board: rockchip: Add Radxa E20C Jonas Karlman
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:47 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini,
Joe Hershberger, Ramon Fried
Cc: Yao Zi, Chukun Pan, u-boot, Jonas Karlman
Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC
Ethernet QoS IP.
Add initial support for the RK3528 GMAC variant.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
v2: New patch
---
drivers/net/dwc_eth_qos.c | 4 +
drivers/net/dwc_eth_qos_rockchip.c | 138 +++++++++++++++++++++++++++++
2 files changed, 142 insertions(+)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index b4ec3614696e..d4561784a6ec 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1611,6 +1611,10 @@ static const struct udevice_id eqos_ids[] = {
},
#endif
#if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP)
+ {
+ .compatible = "rockchip,rk3528-gmac",
+ .data = (ulong)&eqos_rockchip_config
+ },
{
.compatible = "rockchip,rk3568-gmac",
.data = (ulong)&eqos_rockchip_config
diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c
index f3a0f63003ea..3a9c46a01ec3 100644
--- a/drivers/net/dwc_eth_qos_rockchip.c
+++ b/drivers/net/dwc_eth_qos_rockchip.c
@@ -50,6 +50,132 @@ struct rockchip_platform_data {
(((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
+#define RK3528_VO_GRF_GMAC_CON 0x0018
+#define RK3528_VPU_GRF_GMAC_CON5 0x0018
+#define RK3528_VPU_GRF_GMAC_CON6 0x001c
+
+#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
+#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
+#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
+#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
+
+#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
+#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
+
+#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
+#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
+#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
+
+#define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12)
+#define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12)
+
+#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3)
+#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3)
+#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
+#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
+
+#define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
+#define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10))
+#define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10))
+
+#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
+#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
+#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
+#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9)
+
+static int rk3528_set_to_rgmii(struct udevice *dev,
+ int tx_delay, int rx_delay)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+
+ regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5,
+ RK3528_GMAC1_PHY_INTF_SEL_RGMII);
+
+ regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5,
+ DELAY_ENABLE(RK3528, tx_delay, rx_delay));
+
+ regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON6,
+ RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
+
+ return 0;
+}
+
+static int rk3528_set_to_rmii(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+
+ if (data->id == 1)
+ regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5,
+ RK3528_GMAC1_PHY_INTF_SEL_RMII);
+ else
+ regmap_write(data->grf, RK3528_VO_GRF_GMAC_CON,
+ RK3528_GMAC0_PHY_INTF_SEL_RMII |
+ RK3528_GMAC0_CLK_RMII_DIV2);
+
+ return 0;
+}
+
+static int rk3528_set_gmac_speed(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+ u32 val, reg;
+
+ switch (eqos->phy->speed) {
+ case SPEED_10:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+ val = data->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV20 :
+ RK3528_GMAC0_CLK_RMII_DIV20;
+ else
+ val = RK3528_GMAC1_CLK_RGMII_DIV50;
+ break;
+ case SPEED_100:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+ val = data->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV2 :
+ RK3528_GMAC0_CLK_RMII_DIV2;
+ else
+ val = RK3528_GMAC1_CLK_RGMII_DIV5;
+ break;
+ case SPEED_1000:
+ if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
+ val = RK3528_GMAC1_CLK_RGMII_DIV1;
+ else
+ return -EINVAL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ reg = data->id == 1 ? RK3528_VPU_GRF_GMAC_CON5 :
+ RK3528_VO_GRF_GMAC_CON;
+ regmap_write(data->grf, reg, val);
+
+ return 0;
+}
+
+static void rk3528_set_clock_selection(struct udevice *dev, bool enable)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+ u32 val;
+
+ if (data->id == 1) {
+ val = data->clock_input ? RK3528_GMAC1_CLK_SELECT_IO :
+ RK3528_GMAC1_CLK_SELECT_CRU;
+ val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
+ RK3528_GMAC1_CLK_RMII_GATE;
+ regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5, val);
+ } else {
+ val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
+ RK3528_GMAC0_CLK_RMII_GATE;
+ regmap_write(data->grf, RK3528_VO_GRF_GMAC_CON, val);
+ }
+}
+
#define RK3568_GRF_GMAC0_CON0 0x0380
#define RK3568_GRF_GMAC0_CON1 0x0384
#define RK3568_GRF_GMAC1_CON0 0x0388
@@ -269,6 +395,18 @@ static void rk3588_set_clock_selection(struct udevice *dev, bool enable)
}
static const struct rk_gmac_ops rk_gmac_ops[] = {
+ {
+ .compatible = "rockchip,rk3528-gmac",
+ .set_to_rgmii = rk3528_set_to_rgmii,
+ .set_to_rmii = rk3528_set_to_rmii,
+ .set_gmac_speed = rk3528_set_gmac_speed,
+ .set_clock_selection = rk3528_set_clock_selection,
+ .regs = {
+ 0xffbd0000, /* gmac0 */
+ 0xffbe0000, /* gmac1 */
+ 0x0, /* sentinel */
+ },
+ },
{
.compatible = "rockchip,rk3568-gmac",
.set_to_rgmii = rk3568_set_to_rgmii,
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 29/30] board: rockchip: Add minimal generic RK3528 board
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (27 preceding siblings ...)
2025-04-07 22:47 ` [PATCH v2 28/30] net: dwc_eth_qos_rockchip: " Jonas Karlman
@ 2025-04-07 22:47 ` Jonas Karlman
2025-04-08 3:24 ` Kever Yang
2025-04-07 22:47 ` [PATCH v2 30/30] board: rockchip: Add Radxa E20C Jonas Karlman
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:47 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Jonas Karlman
Cc: Yao Zi, Chukun Pan, u-boot
Add a minimal generic RK3528 board that only have eMMC and SD-card
enabled. This defconfig can be used to boot from eMMC or SD-card on most
RK3528 boards that follow reference board design.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
Changes in v2:
- Move sdhci node to main .dts-file
- Enable meminfo cmd
Tested on:
- FriendlyElec NanoPi Zero2
- Radxa ROCK 2A
- Radxa ROCK 2F
---
arch/arm/dts/rk3528-generic-u-boot.dtsi | 12 +++++++
arch/arm/dts/rk3528-generic.dts | 31 ++++++++++++++++++
arch/arm/mach-rockchip/rk3528/MAINTAINERS | 5 +++
configs/generic-rk3528_defconfig | 40 +++++++++++++++++++++++
doc/board/rockchip/rockchip.rst | 12 +++++++
5 files changed, 100 insertions(+)
create mode 100644 arch/arm/dts/rk3528-generic-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3528-generic.dts
create mode 100644 arch/arm/mach-rockchip/rk3528/MAINTAINERS
create mode 100644 configs/generic-rk3528_defconfig
diff --git a/arch/arm/dts/rk3528-generic-u-boot.dtsi b/arch/arm/dts/rk3528-generic-u-boot.dtsi
new file mode 100644
index 000000000000..cc830b514567
--- /dev/null
+++ b/arch/arm/dts/rk3528-generic-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3528-u-boot.dtsi"
+
+&sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ no-mmc;
+ no-sdio;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts
new file mode 100644
index 000000000000..792d3e04a4cb
--- /dev/null
+++ b/arch/arm/dts/rk3528-generic.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Minimal generic DT for RK3528 with eMMC enabled
+ */
+
+/dts-v1/;
+#include "rk3528.dtsi"
+
+/ {
+ model = "Generic RK3528";
+ compatible = "rockchip,rk3528";
+
+ chosen {
+ stdout-path = "serial0:1500000n8";
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ no-sd;
+ no-sdio;
+ non-removable;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m0_xfer>;
+ status = "okay";
+};
diff --git a/arch/arm/mach-rockchip/rk3528/MAINTAINERS b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
new file mode 100644
index 000000000000..cfdc92d770c1
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
@@ -0,0 +1,5 @@
+GENERIC-RK3528
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: arch/arm/dts/rk3528-generic*
+F: configs/generic-rk3528_defconfig
diff --git a/configs/generic-rk3528_defconfig b/configs/generic-rk3528_defconfig
new file mode 100644
index 000000000000..e19c7bc4801d
--- /dev/null
+++ b/configs/generic-rk3528_defconfig
@@ -0,0 +1,40 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3528-generic"
+CONFIG_ROCKCHIP_RK3528=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0xFF9F0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_BOOTMETH_VBE is not set
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-generic.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_OF_UPSTREAM is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_NO_NET=y
+# CONFIG_ADC is not set
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 5a029afae305..c636d33b47c1 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -99,6 +99,9 @@ List of mainline supported Rockchip boards:
- Rockchip Evb-RK3399 (evb_rk3399)
- Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)
+* rk3528
+ - Generic RK3528 (generic-rk3528)
+
* rk3566
- Anbernic RGxx3 (anbernic-rgxx3-rk3566)
- FriendlyElec NanoPi R3S (nanopi-r3s-rk3566)
@@ -260,6 +263,15 @@ To build rk3399 boards:
make evb-rk3399_defconfig
make CROSS_COMPILE=aarch64-linux-gnu-
+To build rk3528 boards:
+
+.. code-block:: bash
+
+ export BL31=../rkbin/bin/rk35/rk3528_bl31_v1.18.elf
+ export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3528_ddr_1056MHz_v1.10.bin
+ make generic-rk3528_defconfig
+ make CROSS_COMPILE=aarch64-linux-gnu-
+
To build rk3568 boards:
.. code-block:: bash
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* [PATCH v2 30/30] board: rockchip: Add Radxa E20C
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
` (28 preceding siblings ...)
2025-04-07 22:47 ` [PATCH v2 29/30] board: rockchip: Add minimal generic RK3528 board Jonas Karlman
@ 2025-04-07 22:47 ` Jonas Karlman
2025-04-08 3:25 ` Kever Yang
29 siblings, 1 reply; 61+ messages in thread
From: Jonas Karlman @ 2025-04-07 22:47 UTC (permalink / raw)
To: Kever Yang, Simon Glass, Philipp Tomsich, Tom Rini, Jonas Karlman
Cc: Yao Zi, Chukun Pan, u-boot
The Radxa E20C is an ultra-compact network computer with a RK3528A SoC
that offers a wide range of networking capabilities.
Features tested on a Radxa E20C v1.104:
- SD-card boot
- eMMC boot
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
Changes in v2:
- Drop sdhci from board u-boot.dtsi
- Update sdmmc node to latest mainline Linux patch
- Enable options for DT nodes added to dts/upstream DT
This also enables options for GMAC, PWM-regulators and USB 2.0. Features
that have been tested but are currently missing the necessary DT nodes.
---
arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi | 12 +++++
arch/arm/mach-rockchip/rk3528/MAINTAINERS | 6 +++
configs/radxa-e20c-rk3528_defconfig | 56 ++++++++++++++++++++++
doc/board/rockchip/rockchip.rst | 1 +
4 files changed, 75 insertions(+)
create mode 100644 arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
create mode 100644 configs/radxa-e20c-rk3528_defconfig
diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
new file mode 100644
index 000000000000..9c2f03a786cf
--- /dev/null
+++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include "rk3528-u-boot.dtsi"
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ vmmc-supply = <&vcc_3v3>;
+ status = "okay";
+};
diff --git a/arch/arm/mach-rockchip/rk3528/MAINTAINERS b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
index cfdc92d770c1..f343f71cf7f6 100644
--- a/arch/arm/mach-rockchip/rk3528/MAINTAINERS
+++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
@@ -3,3 +3,9 @@ M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
F: arch/arm/dts/rk3528-generic*
F: configs/generic-rk3528_defconfig
+
+RADXA-E20C
+M: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: arch/arm/dts/rk3528-radxa-e20c*
+F: configs/radxa-e20c-rk3528_defconfig
diff --git a/configs/radxa-e20c-rk3528_defconfig b/configs/radxa-e20c-rk3528_defconfig
new file mode 100644
index 000000000000..08f3a13af3b2
--- /dev/null
+++ b/configs/radxa-e20c-rk3528_defconfig
@@ -0,0 +1,56 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-radxa-e20c"
+CONFIG_ROCKCHIP_RK3528=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0xFF9F0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-radxa-e20c.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMINFO_MAP=y
+CONFIG_CMD_ADC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_RNG=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_BUTTON=y
+CONFIG_BUTTON_ADC=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_MOTORCOMM=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_MDIO=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index c636d33b47c1..f7d4f2a66860 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -101,6 +101,7 @@ List of mainline supported Rockchip boards:
* rk3528
- Generic RK3528 (generic-rk3528)
+ - Radxa E20C (radxa-e20c-rk3528)
* rk3566
- Anbernic RGxx3 (anbernic-rgxx3-rk3566)
--
2.49.0
^ permalink raw reply related [flat|nested] 61+ messages in thread
* Re: [PATCH v2 01/30] dt-bindings: clock: Document clock and reset unit of RK3528
2025-04-07 22:46 ` [PATCH v2 01/30] dt-bindings: clock: Document clock and reset unit of RK3528 Jonas Karlman
@ 2025-04-08 3:21 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:21 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg,
Yao Zi
Cc: Chukun Pan, u-boot, Heiko Stuebner
On 2025/4/8 06:46, Jonas Karlman wrote:
> From: Yao Zi <ziyao@disroot.org>
>
> There are two types of clocks in RK3528 SoC, CRU-managed and
> SCMI-managed. Independent IDs are assigned to them.
>
> For the reset part, differing from previous Rockchip SoCs and
> downstream bindings which embeds register offsets into the IDs, gapless
> numbers starting from zero are used.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Link: https://lore.kernel.org/r/20250217061142.38480-6-ziyao@disroot.org
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: e0c0a97bc308f71b0934e3637ac545ce65195df0 ]
>
> (cherry picked from commit 8768d063e732e64892e4d1d09aa583d1394c8388)
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> .../Bindings/clock/rockchip,rk3528-cru.yaml | 64 +++
> .../dt-bindings/clock/rockchip,rk3528-cru.h | 453 ++++++++++++++++++
> .../dt-bindings/reset/rockchip,rk3528-cru.h | 241 ++++++++++
> 3 files changed, 758 insertions(+)
> create mode 100644 dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml
> create mode 100644 dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h
> create mode 100644 dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h
>
> diff --git a/dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml b/dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml
> new file mode 100644
> index 000000000000..5a3ec902351c
> --- /dev/null
> +++ b/dts/upstream/Bindings/clock/rockchip,rk3528-cru.yaml
> @@ -0,0 +1,64 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip RK3528 Clock and Reset Controller
> +
> +maintainers:
> + - Yao Zi <ziyao@disroot.org>
> +
> +description: |
> + The RK3528 clock controller generates the clock and also implements a reset
> + controller for SoC peripherals. For example, it provides SCLK_UART0 and
> + PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART
> + module.
> + Each clock is assigned an identifier, consumer nodes can use it to specify
> + the clock. All available clock and reset IDs are defined in dt-binding
> + headers.
> +
> +properties:
> + compatible:
> + const: rockchip,rk3528-cru
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: External 24MHz oscillator clock
> + - description: >
> + 50MHz clock generated by PHY module, for generating GMAC0 clocks only.
> +
> + clock-names:
> + items:
> + - const: xin24m
> + - const: gmac0
> +
> + "#clock-cells":
> + const: 1
> +
> + "#reset-cells":
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - "#clock-cells"
> + - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-controller@ff4a0000 {
> + compatible = "rockchip,rk3528-cru";
> + reg = <0xff4a0000 0x30000>;
> + clocks = <&xin24m>, <&gmac0_clk>;
> + clock-names = "xin24m", "gmac0";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> diff --git a/dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h b/dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h
> new file mode 100644
> index 000000000000..55a448f5ed6d
> --- /dev/null
> +++ b/dts/upstream/include/dt-bindings/clock/rockchip,rk3528-cru.h
> @@ -0,0 +1,453 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
> + * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
> + * Author: Joseph Chen <chenjh@rock-chips.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
> +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
> +
> +/* cru-clocks indices */
> +#define PLL_APLL 0
> +#define PLL_CPLL 1
> +#define PLL_GPLL 2
> +#define PLL_PPLL 3
> +#define PLL_DPLL 4
> +#define ARMCLK 5
> +#define XIN_OSC0_HALF 6
> +#define CLK_MATRIX_50M_SRC 7
> +#define CLK_MATRIX_100M_SRC 8
> +#define CLK_MATRIX_150M_SRC 9
> +#define CLK_MATRIX_200M_SRC 10
> +#define CLK_MATRIX_250M_SRC 11
> +#define CLK_MATRIX_300M_SRC 12
> +#define CLK_MATRIX_339M_SRC 13
> +#define CLK_MATRIX_400M_SRC 14
> +#define CLK_MATRIX_500M_SRC 15
> +#define CLK_MATRIX_600M_SRC 16
> +#define CLK_UART0_SRC 17
> +#define CLK_UART0_FRAC 18
> +#define SCLK_UART0 19
> +#define CLK_UART1_SRC 20
> +#define CLK_UART1_FRAC 21
> +#define SCLK_UART1 22
> +#define CLK_UART2_SRC 23
> +#define CLK_UART2_FRAC 24
> +#define SCLK_UART2 25
> +#define CLK_UART3_SRC 26
> +#define CLK_UART3_FRAC 27
> +#define SCLK_UART3 28
> +#define CLK_UART4_SRC 29
> +#define CLK_UART4_FRAC 30
> +#define SCLK_UART4 31
> +#define CLK_UART5_SRC 32
> +#define CLK_UART5_FRAC 33
> +#define SCLK_UART5 34
> +#define CLK_UART6_SRC 35
> +#define CLK_UART6_FRAC 36
> +#define SCLK_UART6 37
> +#define CLK_UART7_SRC 38
> +#define CLK_UART7_FRAC 39
> +#define SCLK_UART7 40
> +#define CLK_I2S0_2CH_SRC 41
> +#define CLK_I2S0_2CH_FRAC 42
> +#define MCLK_I2S0_2CH_SAI_SRC 43
> +#define CLK_I2S3_8CH_SRC 44
> +#define CLK_I2S3_8CH_FRAC 45
> +#define MCLK_I2S3_8CH_SAI_SRC 46
> +#define CLK_I2S1_8CH_SRC 47
> +#define CLK_I2S1_8CH_FRAC 48
> +#define MCLK_I2S1_8CH_SAI_SRC 49
> +#define CLK_I2S2_2CH_SRC 50
> +#define CLK_I2S2_2CH_FRAC 51
> +#define MCLK_I2S2_2CH_SAI_SRC 52
> +#define CLK_SPDIF_SRC 53
> +#define CLK_SPDIF_FRAC 54
> +#define MCLK_SPDIF_SRC 55
> +#define DCLK_VOP_SRC0 56
> +#define DCLK_VOP_SRC1 57
> +#define CLK_HSM 58
> +#define CLK_CORE_SRC_ACS 59
> +#define CLK_CORE_SRC_PVTMUX 60
> +#define CLK_CORE_SRC 61
> +#define CLK_CORE 62
> +#define ACLK_M_CORE_BIU 63
> +#define CLK_CORE_PVTPLL_SRC 64
> +#define PCLK_DBG 65
> +#define SWCLKTCK 66
> +#define CLK_SCANHS_CORE 67
> +#define CLK_SCANHS_ACLKM_CORE 68
> +#define CLK_SCANHS_PCLK_DBG 69
> +#define CLK_SCANHS_PCLK_CPU_BIU 70
> +#define PCLK_CPU_ROOT 71
> +#define PCLK_CORE_GRF 72
> +#define PCLK_DAPLITE_BIU 73
> +#define PCLK_CPU_BIU 74
> +#define CLK_REF_PVTPLL_CORE 75
> +#define ACLK_BUS_VOPGL_ROOT 76
> +#define ACLK_BUS_VOPGL_BIU 77
> +#define ACLK_BUS_H_ROOT 78
> +#define ACLK_BUS_H_BIU 79
> +#define ACLK_BUS_ROOT 80
> +#define HCLK_BUS_ROOT 81
> +#define PCLK_BUS_ROOT 82
> +#define ACLK_BUS_M_ROOT 83
> +#define ACLK_SYSMEM_BIU 84
> +#define CLK_TIMER_ROOT 85
> +#define ACLK_BUS_BIU 86
> +#define HCLK_BUS_BIU 87
> +#define PCLK_BUS_BIU 88
> +#define PCLK_DFT2APB 89
> +#define PCLK_BUS_GRF 90
> +#define ACLK_BUS_M_BIU 91
> +#define ACLK_GIC 92
> +#define ACLK_SPINLOCK 93
> +#define ACLK_DMAC 94
> +#define PCLK_TIMER 95
> +#define CLK_TIMER0 96
> +#define CLK_TIMER1 97
> +#define CLK_TIMER2 98
> +#define CLK_TIMER3 99
> +#define CLK_TIMER4 100
> +#define CLK_TIMER5 101
> +#define PCLK_JDBCK_DAP 102
> +#define CLK_JDBCK_DAP 103
> +#define PCLK_WDT_NS 104
> +#define TCLK_WDT_NS 105
> +#define HCLK_TRNG_NS 106
> +#define PCLK_UART0 107
> +#define PCLK_DMA2DDR 108
> +#define ACLK_DMA2DDR 109
> +#define PCLK_PWM0 110
> +#define CLK_PWM0 111
> +#define CLK_CAPTURE_PWM0 112
> +#define PCLK_PWM1 113
> +#define CLK_PWM1 114
> +#define CLK_CAPTURE_PWM1 115
> +#define PCLK_SCR 116
> +#define ACLK_DCF 117
> +#define PCLK_INTMUX 118
> +#define CLK_PPLL_I 119
> +#define CLK_PPLL_MUX 120
> +#define CLK_PPLL_100M_MATRIX 121
> +#define CLK_PPLL_50M_MATRIX 122
> +#define CLK_REF_PCIE_INNER_PHY 123
> +#define CLK_REF_PCIE_100M_PHY 124
> +#define ACLK_VPU_L_ROOT 125
> +#define CLK_GMAC1_VPU_25M 126
> +#define CLK_PPLL_125M_MATRIX 127
> +#define ACLK_VPU_ROOT 128
> +#define HCLK_VPU_ROOT 129
> +#define PCLK_VPU_ROOT 130
> +#define ACLK_VPU_BIU 131
> +#define HCLK_VPU_BIU 132
> +#define PCLK_VPU_BIU 133
> +#define ACLK_VPU 134
> +#define HCLK_VPU 135
> +#define PCLK_CRU_PCIE 136
> +#define PCLK_VPU_GRF 137
> +#define HCLK_SFC 138
> +#define SCLK_SFC 139
> +#define CCLK_SRC_EMMC 140
> +#define HCLK_EMMC 141
> +#define ACLK_EMMC 142
> +#define BCLK_EMMC 143
> +#define TCLK_EMMC 144
> +#define PCLK_GPIO1 145
> +#define DBCLK_GPIO1 146
> +#define ACLK_VPU_L_BIU 147
> +#define PCLK_VPU_IOC 148
> +#define HCLK_SAI_I2S0 149
> +#define MCLK_SAI_I2S0 150
> +#define HCLK_SAI_I2S2 151
> +#define MCLK_SAI_I2S2 152
> +#define PCLK_ACODEC 153
> +#define MCLK_ACODEC_TX 154
> +#define PCLK_GPIO3 155
> +#define DBCLK_GPIO3 156
> +#define PCLK_SPI1 157
> +#define CLK_SPI1 158
> +#define SCLK_IN_SPI1 159
> +#define PCLK_UART2 160
> +#define PCLK_UART5 161
> +#define PCLK_UART6 162
> +#define PCLK_UART7 163
> +#define PCLK_I2C3 164
> +#define CLK_I2C3 165
> +#define PCLK_I2C5 166
> +#define CLK_I2C5 167
> +#define PCLK_I2C6 168
> +#define CLK_I2C6 169
> +#define ACLK_MAC_VPU 170
> +#define PCLK_MAC_VPU 171
> +#define CLK_GMAC1_RMII_VPU 172
> +#define CLK_GMAC1_SRC_VPU 173
> +#define PCLK_PCIE 174
> +#define CLK_PCIE_AUX 175
> +#define ACLK_PCIE 176
> +#define HCLK_PCIE_SLV 177
> +#define HCLK_PCIE_DBI 178
> +#define PCLK_PCIE_PHY 179
> +#define PCLK_PIPE_GRF 180
> +#define CLK_PIPE_USB3OTG_COMBO 181
> +#define CLK_UTMI_USB3OTG 182
> +#define CLK_PCIE_PIPE_PHY 183
> +#define CCLK_SRC_SDIO0 184
> +#define HCLK_SDIO0 185
> +#define CCLK_SRC_SDIO1 186
> +#define HCLK_SDIO1 187
> +#define CLK_TS_0 188
> +#define CLK_TS_1 189
> +#define PCLK_CAN2 190
> +#define CLK_CAN2 191
> +#define PCLK_CAN3 192
> +#define CLK_CAN3 193
> +#define PCLK_SARADC 194
> +#define CLK_SARADC 195
> +#define PCLK_TSADC 196
> +#define CLK_TSADC 197
> +#define CLK_TSADC_TSEN 198
> +#define ACLK_USB3OTG 199
> +#define CLK_REF_USB3OTG 200
> +#define CLK_SUSPEND_USB3OTG 201
> +#define ACLK_GPU_ROOT 202
> +#define PCLK_GPU_ROOT 203
> +#define ACLK_GPU_BIU 204
> +#define PCLK_GPU_BIU 205
> +#define ACLK_GPU 206
> +#define CLK_GPU_PVTPLL_SRC 207
> +#define ACLK_GPU_MALI 208
> +#define HCLK_RKVENC_ROOT 209
> +#define ACLK_RKVENC_ROOT 210
> +#define PCLK_RKVENC_ROOT 211
> +#define HCLK_RKVENC_BIU 212
> +#define ACLK_RKVENC_BIU 213
> +#define PCLK_RKVENC_BIU 214
> +#define HCLK_RKVENC 215
> +#define ACLK_RKVENC 216
> +#define CLK_CORE_RKVENC 217
> +#define HCLK_SAI_I2S1 218
> +#define MCLK_SAI_I2S1 219
> +#define PCLK_I2C1 220
> +#define CLK_I2C1 221
> +#define PCLK_I2C0 222
> +#define CLK_I2C0 223
> +#define CLK_UART_JTAG 224
> +#define PCLK_SPI0 225
> +#define CLK_SPI0 226
> +#define SCLK_IN_SPI0 227
> +#define PCLK_GPIO4 228
> +#define DBCLK_GPIO4 229
> +#define PCLK_RKVENC_IOC 230
> +#define HCLK_SPDIF 231
> +#define MCLK_SPDIF 232
> +#define HCLK_PDM 233
> +#define MCLK_PDM 234
> +#define PCLK_UART1 235
> +#define PCLK_UART3 236
> +#define PCLK_RKVENC_GRF 237
> +#define PCLK_CAN0 238
> +#define CLK_CAN0 239
> +#define PCLK_CAN1 240
> +#define CLK_CAN1 241
> +#define ACLK_VO_ROOT 242
> +#define HCLK_VO_ROOT 243
> +#define PCLK_VO_ROOT 244
> +#define ACLK_VO_BIU 245
> +#define HCLK_VO_BIU 246
> +#define PCLK_VO_BIU 247
> +#define HCLK_RGA2E 248
> +#define ACLK_RGA2E 249
> +#define CLK_CORE_RGA2E 250
> +#define HCLK_VDPP 251
> +#define ACLK_VDPP 252
> +#define CLK_CORE_VDPP 253
> +#define PCLK_VO_GRF 254
> +#define PCLK_CRU 255
> +#define ACLK_VOP_ROOT 256
> +#define ACLK_VOP_BIU 257
> +#define HCLK_VOP 258
> +#define DCLK_VOP0 259
> +#define DCLK_VOP1 260
> +#define ACLK_VOP 261
> +#define PCLK_HDMI 262
> +#define CLK_SFR_HDMI 263
> +#define CLK_CEC_HDMI 264
> +#define CLK_SPDIF_HDMI 265
> +#define CLK_HDMIPHY_TMDSSRC 266
> +#define CLK_HDMIPHY_PREP 267
> +#define PCLK_HDMIPHY 268
> +#define HCLK_HDCP_KEY 269
> +#define ACLK_HDCP 270
> +#define HCLK_HDCP 271
> +#define PCLK_HDCP 272
> +#define HCLK_CVBS 273
> +#define DCLK_CVBS 274
> +#define DCLK_4X_CVBS 275
> +#define ACLK_JPEG_DECODER 276
> +#define HCLK_JPEG_DECODER 277
> +#define ACLK_VO_L_ROOT 278
> +#define ACLK_VO_L_BIU 279
> +#define ACLK_MAC_VO 280
> +#define PCLK_MAC_VO 281
> +#define CLK_GMAC0_SRC 282
> +#define CLK_GMAC0_RMII_50M 283
> +#define CLK_GMAC0_TX 284
> +#define CLK_GMAC0_RX 285
> +#define ACLK_JPEG_ROOT 286
> +#define ACLK_JPEG_BIU 287
> +#define HCLK_SAI_I2S3 288
> +#define MCLK_SAI_I2S3 289
> +#define CLK_MACPHY 290
> +#define PCLK_VCDCPHY 291
> +#define PCLK_GPIO2 292
> +#define DBCLK_GPIO2 293
> +#define PCLK_VO_IOC 294
> +#define CCLK_SRC_SDMMC0 295
> +#define HCLK_SDMMC0 296
> +#define PCLK_OTPC_NS 297
> +#define CLK_SBPI_OTPC_NS 298
> +#define CLK_USER_OTPC_NS 299
> +#define CLK_HDMIHDP0 300
> +#define HCLK_USBHOST 301
> +#define HCLK_USBHOST_ARB 302
> +#define CLK_USBHOST_OHCI 303
> +#define CLK_USBHOST_UTMI 304
> +#define PCLK_UART4 305
> +#define PCLK_I2C4 306
> +#define CLK_I2C4 307
> +#define PCLK_I2C7 308
> +#define CLK_I2C7 309
> +#define PCLK_USBPHY 310
> +#define CLK_REF_USBPHY 311
> +#define HCLK_RKVDEC_ROOT 312
> +#define ACLK_RKVDEC_ROOT_NDFT 313
> +#define PCLK_DDRPHY_CRU 314
> +#define HCLK_RKVDEC_BIU 315
> +#define ACLK_RKVDEC_BIU 316
> +#define ACLK_RKVDEC 317
> +#define HCLK_RKVDEC 318
> +#define CLK_HEVC_CA_RKVDEC 319
> +#define ACLK_RKVDEC_PVTMUX_ROOT 320
> +#define CLK_RKVDEC_PVTPLL_SRC 321
> +#define PCLK_DDR_ROOT 322
> +#define PCLK_DDR_BIU 323
> +#define PCLK_DDRC 324
> +#define PCLK_DDRMON 325
> +#define CLK_TIMER_DDRMON 326
> +#define PCLK_MSCH_BIU 327
> +#define PCLK_DDR_GRF 328
> +#define PCLK_DDR_HWLP 329
> +#define PCLK_DDRPHY 330
> +#define CLK_MSCH_BIU 331
> +#define ACLK_DDR_UPCTL 332
> +#define CLK_DDR_UPCTL 333
> +#define CLK_DDRMON 334
> +#define ACLK_DDR_SCRAMBLE 335
> +#define ACLK_SPLIT 336
> +#define CLK_DDRC_SRC 337
> +#define CLK_DDR_PHY 338
> +#define PCLK_OTPC_S 339
> +#define CLK_SBPI_OTPC_S 340
> +#define CLK_USER_OTPC_S 341
> +#define PCLK_KEYREADER 342
> +#define PCLK_BUS_SGRF 343
> +#define PCLK_STIMER 344
> +#define CLK_STIMER0 345
> +#define CLK_STIMER1 346
> +#define PCLK_WDT_S 347
> +#define TCLK_WDT_S 348
> +#define HCLK_TRNG_S 349
> +#define HCLK_BOOTROM 350
> +#define PCLK_DCF 351
> +#define ACLK_SYSMEM 352
> +#define HCLK_TSP 353
> +#define ACLK_TSP 354
> +#define CLK_CORE_TSP 355
> +#define CLK_OTPC_ARB 356
> +#define PCLK_OTP_MASK 357
> +#define CLK_PMC_OTP 358
> +#define PCLK_PMU_ROOT 359
> +#define HCLK_PMU_ROOT 360
> +#define PCLK_I2C2 361
> +#define CLK_I2C2 362
> +#define HCLK_PMU_BIU 363
> +#define PCLK_PMU_BIU 364
> +#define FCLK_MCU 365
> +#define RTC_CLK_MCU 366
> +#define PCLK_OSCCHK 367
> +#define CLK_PMU_MCU_JTAG 368
> +#define PCLK_PMU 369
> +#define PCLK_GPIO0 370
> +#define DBCLK_GPIO0 371
> +#define XIN_OSC0_DIV 372
> +#define CLK_DEEPSLOW 373
> +#define CLK_DDR_FAIL_SAFE 374
> +#define PCLK_PMU_HP_TIMER 375
> +#define CLK_PMU_HP_TIMER 376
> +#define CLK_PMU_32K_HP_TIMER 377
> +#define PCLK_PMU_IOC 378
> +#define PCLK_PMU_CRU 379
> +#define PCLK_PMU_GRF 380
> +#define PCLK_PMU_WDT 381
> +#define TCLK_PMU_WDT 382
> +#define PCLK_PMU_MAILBOX 383
> +#define PCLK_SCRKEYGEN 384
> +#define CLK_SCRKEYGEN 385
> +#define CLK_PVTM_OSCCHK 386
> +#define CLK_REFOUT 387
> +#define CLK_PVTM_PMU 388
> +#define PCLK_PVTM_PMU 389
> +#define PCLK_PMU_SGRF 390
> +#define HCLK_PMU_SRAM 391
> +#define CLK_UART0 392
> +#define CLK_UART1 393
> +#define CLK_UART2 394
> +#define CLK_UART3 395
> +#define CLK_UART4 396
> +#define CLK_UART5 397
> +#define CLK_UART6 398
> +#define CLK_UART7 399
> +#define MCLK_I2S0_2CH_SAI_SRC_PRE 400
> +#define MCLK_I2S1_8CH_SAI_SRC_PRE 401
> +#define MCLK_I2S2_2CH_SAI_SRC_PRE 402
> +#define MCLK_I2S3_8CH_SAI_SRC_PRE 403
> +#define MCLK_SDPDIF_SRC_PRE 404
> +
> +/* scmi-clocks indices */
> +#define SCMI_PCLK_KEYREADER 0
> +#define SCMI_HCLK_KLAD 1
> +#define SCMI_PCLK_KLAD 2
> +#define SCMI_HCLK_TRNG_S 3
> +#define SCMI_HCLK_CRYPTO_S 4
> +#define SCMI_PCLK_WDT_S 5
> +#define SCMI_TCLK_WDT_S 6
> +#define SCMI_PCLK_STIMER 7
> +#define SCMI_CLK_STIMER0 8
> +#define SCMI_CLK_STIMER1 9
> +#define SCMI_PCLK_OTP_MASK 10
> +#define SCMI_PCLK_OTPC_S 11
> +#define SCMI_CLK_SBPI_OTPC_S 12
> +#define SCMI_CLK_USER_OTPC_S 13
> +#define SCMI_CLK_PMC_OTP 14
> +#define SCMI_CLK_OTPC_ARB 15
> +#define SCMI_CLK_CORE_TSP 16
> +#define SCMI_ACLK_TSP 17
> +#define SCMI_HCLK_TSP 18
> +#define SCMI_PCLK_DCF 19
> +#define SCMI_CLK_DDR 20
> +#define SCMI_CLK_CPU 21
> +#define SCMI_CLK_GPU 22
> +#define SCMI_CORE_CRYPTO 23
> +#define SCMI_ACLK_CRYPTO 24
> +#define SCMI_PKA_CRYPTO 25
> +#define SCMI_HCLK_CRYPTO 26
> +#define SCMI_CORE_CRYPTO_S 27
> +#define SCMI_ACLK_CRYPTO_S 28
> +#define SCMI_PKA_CRYPTO_S 29
> +#define SCMI_CORE_KLAD 30
> +#define SCMI_ACLK_KLAD 31
> +#define SCMI_HCLK_TRNG 32
> +
> +#endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
> diff --git a/dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h b/dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h
> new file mode 100644
> index 000000000000..6b024c5f2e1c
> --- /dev/null
> +++ b/dts/upstream/include/dt-bindings/reset/rockchip,rk3528-cru.h
> @@ -0,0 +1,241 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> +/*
> + * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
> + * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
> + * Author: Joseph Chen <chenjh@rock-chips.com>
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
> +#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
> +
> +#define SRST_CORE0_PO 0
> +#define SRST_CORE1_PO 1
> +#define SRST_CORE2_PO 2
> +#define SRST_CORE3_PO 3
> +#define SRST_CORE0 4
> +#define SRST_CORE1 5
> +#define SRST_CORE2 6
> +#define SRST_CORE3 7
> +#define SRST_NL2 8
> +#define SRST_CORE_BIU 9
> +#define SRST_CORE_CRYPTO 10
> +#define SRST_P_DBG 11
> +#define SRST_POT_DBG 12
> +#define SRST_NT_DBG 13
> +#define SRST_P_CORE_GRF 14
> +#define SRST_P_DAPLITE_BIU 15
> +#define SRST_P_CPU_BIU 16
> +#define SRST_REF_PVTPLL_CORE 17
> +#define SRST_A_BUS_VOPGL_BIU 18
> +#define SRST_A_BUS_H_BIU 19
> +#define SRST_A_SYSMEM_BIU 20
> +#define SRST_A_BUS_BIU 21
> +#define SRST_H_BUS_BIU 22
> +#define SRST_P_BUS_BIU 23
> +#define SRST_P_DFT2APB 24
> +#define SRST_P_BUS_GRF 25
> +#define SRST_A_BUS_M_BIU 26
> +#define SRST_A_GIC 27
> +#define SRST_A_SPINLOCK 28
> +#define SRST_A_DMAC 29
> +#define SRST_P_TIMER 30
> +#define SRST_TIMER0 31
> +#define SRST_TIMER1 32
> +#define SRST_TIMER2 33
> +#define SRST_TIMER3 34
> +#define SRST_TIMER4 35
> +#define SRST_TIMER5 36
> +#define SRST_P_JDBCK_DAP 37
> +#define SRST_JDBCK_DAP 38
> +#define SRST_P_WDT_NS 39
> +#define SRST_T_WDT_NS 40
> +#define SRST_H_TRNG_NS 41
> +#define SRST_P_UART0 42
> +#define SRST_S_UART0 43
> +#define SRST_PKA_CRYPTO 44
> +#define SRST_A_CRYPTO 45
> +#define SRST_H_CRYPTO 46
> +#define SRST_P_DMA2DDR 47
> +#define SRST_A_DMA2DDR 48
> +#define SRST_P_PWM0 49
> +#define SRST_PWM0 50
> +#define SRST_P_PWM1 51
> +#define SRST_PWM1 52
> +#define SRST_P_SCR 53
> +#define SRST_A_DCF 54
> +#define SRST_P_INTMUX 55
> +#define SRST_A_VPU_BIU 56
> +#define SRST_H_VPU_BIU 57
> +#define SRST_P_VPU_BIU 58
> +#define SRST_A_VPU 59
> +#define SRST_H_VPU 60
> +#define SRST_P_CRU_PCIE 61
> +#define SRST_P_VPU_GRF 62
> +#define SRST_H_SFC 63
> +#define SRST_S_SFC 64
> +#define SRST_C_EMMC 65
> +#define SRST_H_EMMC 66
> +#define SRST_A_EMMC 67
> +#define SRST_B_EMMC 68
> +#define SRST_T_EMMC 69
> +#define SRST_P_GPIO1 70
> +#define SRST_DB_GPIO1 71
> +#define SRST_A_VPU_L_BIU 72
> +#define SRST_P_VPU_IOC 73
> +#define SRST_H_SAI_I2S0 74
> +#define SRST_M_SAI_I2S0 75
> +#define SRST_H_SAI_I2S2 76
> +#define SRST_M_SAI_I2S2 77
> +#define SRST_P_ACODEC 78
> +#define SRST_P_GPIO3 79
> +#define SRST_DB_GPIO3 80
> +#define SRST_P_SPI1 81
> +#define SRST_SPI1 82
> +#define SRST_P_UART2 83
> +#define SRST_S_UART2 84
> +#define SRST_P_UART5 85
> +#define SRST_S_UART5 86
> +#define SRST_P_UART6 87
> +#define SRST_S_UART6 88
> +#define SRST_P_UART7 89
> +#define SRST_S_UART7 90
> +#define SRST_P_I2C3 91
> +#define SRST_I2C3 92
> +#define SRST_P_I2C5 93
> +#define SRST_I2C5 94
> +#define SRST_P_I2C6 95
> +#define SRST_I2C6 96
> +#define SRST_A_MAC 97
> +#define SRST_P_PCIE 98
> +#define SRST_PCIE_PIPE_PHY 99
> +#define SRST_PCIE_POWER_UP 100
> +#define SRST_P_PCIE_PHY 101
> +#define SRST_P_PIPE_GRF 102
> +#define SRST_H_SDIO0 103
> +#define SRST_H_SDIO1 104
> +#define SRST_TS_0 105
> +#define SRST_TS_1 106
> +#define SRST_P_CAN2 107
> +#define SRST_CAN2 108
> +#define SRST_P_CAN3 109
> +#define SRST_CAN3 110
> +#define SRST_P_SARADC 111
> +#define SRST_SARADC 112
> +#define SRST_SARADC_PHY 113
> +#define SRST_P_TSADC 114
> +#define SRST_TSADC 115
> +#define SRST_A_USB3OTG 116
> +#define SRST_A_GPU_BIU 117
> +#define SRST_P_GPU_BIU 118
> +#define SRST_A_GPU 119
> +#define SRST_REF_PVTPLL_GPU 120
> +#define SRST_H_RKVENC_BIU 121
> +#define SRST_A_RKVENC_BIU 122
> +#define SRST_P_RKVENC_BIU 123
> +#define SRST_H_RKVENC 124
> +#define SRST_A_RKVENC 125
> +#define SRST_CORE_RKVENC 126
> +#define SRST_H_SAI_I2S1 127
> +#define SRST_M_SAI_I2S1 128
> +#define SRST_P_I2C1 129
> +#define SRST_I2C1 130
> +#define SRST_P_I2C0 131
> +#define SRST_I2C0 132
> +#define SRST_P_SPI0 133
> +#define SRST_SPI0 134
> +#define SRST_P_GPIO4 135
> +#define SRST_DB_GPIO4 136
> +#define SRST_P_RKVENC_IOC 137
> +#define SRST_H_SPDIF 138
> +#define SRST_M_SPDIF 139
> +#define SRST_H_PDM 140
> +#define SRST_M_PDM 141
> +#define SRST_P_UART1 142
> +#define SRST_S_UART1 143
> +#define SRST_P_UART3 144
> +#define SRST_S_UART3 145
> +#define SRST_P_RKVENC_GRF 146
> +#define SRST_P_CAN0 147
> +#define SRST_CAN0 148
> +#define SRST_P_CAN1 149
> +#define SRST_CAN1 150
> +#define SRST_A_VO_BIU 151
> +#define SRST_H_VO_BIU 152
> +#define SRST_P_VO_BIU 153
> +#define SRST_H_RGA2E 154
> +#define SRST_A_RGA2E 155
> +#define SRST_CORE_RGA2E 156
> +#define SRST_H_VDPP 157
> +#define SRST_A_VDPP 158
> +#define SRST_CORE_VDPP 159
> +#define SRST_P_VO_GRF 160
> +#define SRST_P_CRU 161
> +#define SRST_A_VOP_BIU 162
> +#define SRST_H_VOP 163
> +#define SRST_D_VOP0 164
> +#define SRST_D_VOP1 165
> +#define SRST_A_VOP 166
> +#define SRST_P_HDMI 167
> +#define SRST_HDMI 168
> +#define SRST_P_HDMIPHY 169
> +#define SRST_H_HDCP_KEY 170
> +#define SRST_A_HDCP 171
> +#define SRST_H_HDCP 172
> +#define SRST_P_HDCP 173
> +#define SRST_H_CVBS 174
> +#define SRST_D_CVBS_VOP 175
> +#define SRST_D_4X_CVBS_VOP 176
> +#define SRST_A_JPEG_DECODER 177
> +#define SRST_H_JPEG_DECODER 178
> +#define SRST_A_VO_L_BIU 179
> +#define SRST_A_MAC_VO 180
> +#define SRST_A_JPEG_BIU 181
> +#define SRST_H_SAI_I2S3 182
> +#define SRST_M_SAI_I2S3 183
> +#define SRST_MACPHY 184
> +#define SRST_P_VCDCPHY 185
> +#define SRST_P_GPIO2 186
> +#define SRST_DB_GPIO2 187
> +#define SRST_P_VO_IOC 188
> +#define SRST_H_SDMMC0 189
> +#define SRST_P_OTPC_NS 190
> +#define SRST_SBPI_OTPC_NS 191
> +#define SRST_USER_OTPC_NS 192
> +#define SRST_HDMIHDP0 193
> +#define SRST_H_USBHOST 194
> +#define SRST_H_USBHOST_ARB 195
> +#define SRST_HOST_UTMI 196
> +#define SRST_P_UART4 197
> +#define SRST_S_UART4 198
> +#define SRST_P_I2C4 199
> +#define SRST_I2C4 200
> +#define SRST_P_I2C7 201
> +#define SRST_I2C7 202
> +#define SRST_P_USBPHY 203
> +#define SRST_USBPHY_POR 204
> +#define SRST_USBPHY_OTG 205
> +#define SRST_USBPHY_HOST 206
> +#define SRST_P_DDRPHY_CRU 207
> +#define SRST_H_RKVDEC_BIU 208
> +#define SRST_A_RKVDEC_BIU 209
> +#define SRST_A_RKVDEC 210
> +#define SRST_H_RKVDEC 211
> +#define SRST_HEVC_CA_RKVDEC 212
> +#define SRST_REF_PVTPLL_RKVDEC 213
> +#define SRST_P_DDR_BIU 214
> +#define SRST_P_DDRC 215
> +#define SRST_P_DDRMON 216
> +#define SRST_TIMER_DDRMON 217
> +#define SRST_P_MSCH_BIU 218
> +#define SRST_P_DDR_GRF 219
> +#define SRST_P_DDR_HWLP 220
> +#define SRST_P_DDRPHY 221
> +#define SRST_MSCH_BIU 222
> +#define SRST_A_DDR_UPCTL 223
> +#define SRST_DDR_UPCTL 224
> +#define SRST_DDRMON 225
> +#define SRST_A_DDR_SCRAMBLE 226
> +#define SRST_A_SPLIT 227
> +#define SRST_DDR_PHY 228
> +
> +#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 02/30] arm64: dts: rockchip: Add clock generators for RK3528 SoC
2025-04-07 22:46 ` [PATCH v2 02/30] arm64: dts: rockchip: Add clock generators for RK3528 SoC Jonas Karlman
@ 2025-04-08 3:21 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:21 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Heiko Stuebner
On 2025/4/8 06:46, Jonas Karlman wrote:
> From: Yao Zi <ziyao@disroot.org>
>
> Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is
> generated by internal Ethernet phy, a fixed clock node is added as a
> placeholder to avoid orphans.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> Link: https://lore.kernel.org/r/20250217061142.38480-9-ziyao@disroot.org
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: 858cdcdd11cf9913756297d3869e4de0f01329ea ]
>
> (cherry picked from commit 60741472b42e92d2393327cb70669ab90e3b382f)
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> dts/upstream/src/arm64/rockchip/rk3528.dtsi | 51 +++++++++++++++++++++
> 1 file changed, 51 insertions(+)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> index e58faa985aa4..37fd40377076 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> +++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> @@ -6,6 +6,7 @@
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/clock/rockchip,rk3528-cru.h>
>
> / {
> compatible = "rockchip,rk3528";
> @@ -95,6 +96,13 @@
> #clock-cells = <0>;
> };
>
> + gmac0_clk: clock-gmac50m {
> + compatible = "fixed-clock";
> + clock-frequency = <50000000>;
> + clock-output-names = "gmac0";
> + #clock-cells = <0>;
> + };
> +
> soc {
> compatible = "simple-bus";
> ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
> @@ -114,6 +122,49 @@
> #interrupt-cells = <3>;
> };
>
> + cru: clock-controller@ff4a0000 {
> + compatible = "rockchip,rk3528-cru";
> + reg = <0x0 0xff4a0000 0x0 0x30000>;
> + assigned-clocks =
> + <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>,
> + <&cru PLL_PPLL>, <&cru PLL_CPLL>,
> + <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>,
> + <&cru CLK_MATRIX_500M_SRC>,
> + <&cru CLK_MATRIX_50M_SRC>,
> + <&cru CLK_MATRIX_100M_SRC>,
> + <&cru CLK_MATRIX_150M_SRC>,
> + <&cru CLK_MATRIX_200M_SRC>,
> + <&cru CLK_MATRIX_300M_SRC>,
> + <&cru CLK_MATRIX_339M_SRC>,
> + <&cru CLK_MATRIX_400M_SRC>,
> + <&cru CLK_MATRIX_600M_SRC>,
> + <&cru CLK_PPLL_50M_MATRIX>,
> + <&cru CLK_PPLL_100M_MATRIX>,
> + <&cru CLK_PPLL_125M_MATRIX>,
> + <&cru ACLK_BUS_VOPGL_ROOT>;
> + assigned-clock-rates =
> + <32768>, <1188000000>,
> + <1000000000>, <996000000>,
> + <408000000>, <250000000>,
> + <500000000>,
> + <50000000>,
> + <100000000>,
> + <150000000>,
> + <200000000>,
> + <300000000>,
> + <340000000>,
> + <400000000>,
> + <600000000>,
> + <50000000>,
> + <100000000>,
> + <125000000>,
> + <500000000>;
> + clocks = <&xin24m>, <&gmac0_clk>;
> + clock-names = "xin24m", "gmac0";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> uart0: serial@ff9f0000 {
> compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> reg = <0x0 0xff9f0000 0x0 0x100>;
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 03/30] arm64: dts: rockchip: Add UART clocks for RK3528 SoC
2025-04-07 22:46 ` [PATCH v2 03/30] arm64: dts: rockchip: Add UART clocks " Jonas Karlman
@ 2025-04-08 3:21 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:21 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Heiko Stuebner
On 2025/4/8 06:46, Jonas Karlman wrote:
> From: Yao Zi <ziyao@disroot.org>
>
> Add missing clocks in UART nodes for RK3528 SoC.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> Link: https://lore.kernel.org/r/20250217061142.38480-10-ziyao@disroot.org
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: b9454434d0349223418f74fbfa7b902104da9bc5 ]
>
> (cherry picked from commit 12f69f638472dc9cf1b62816c7d4407de1846d12)
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> dts/upstream/src/arm64/rockchip/rk3528.dtsi | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> index 37fd40377076..5b334690356a 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> +++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> @@ -168,7 +168,8 @@
> uart0: serial@ff9f0000 {
> compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> reg = <0x0 0xff9f0000 0x0 0x100>;
> - clock-frequency = <24000000>;
> + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
> + clock-names = "baudclk", "apb_pclk";
> interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> reg-io-width = <4>;
> reg-shift = <2>;
> @@ -178,6 +179,8 @@
> uart1: serial@ff9f8000 {
> compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> reg = <0x0 0xff9f8000 0x0 0x100>;
> + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
> + clock-names = "baudclk", "apb_pclk";
> interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> reg-io-width = <4>;
> reg-shift = <2>;
> @@ -187,6 +190,8 @@
> uart2: serial@ffa00000 {
> compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> reg = <0x0 0xffa00000 0x0 0x100>;
> + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
> + clock-names = "baudclk", "apb_pclk";
> interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> reg-io-width = <4>;
> reg-shift = <2>;
> @@ -195,6 +200,8 @@
>
> uart3: serial@ffa08000 {
> compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
> + clock-names = "baudclk", "apb_pclk";
> reg = <0x0 0xffa08000 0x0 0x100>;
> reg-io-width = <4>;
> reg-shift = <2>;
> @@ -204,6 +211,8 @@
> uart4: serial@ffa10000 {
> compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> reg = <0x0 0xffa10000 0x0 0x100>;
> + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
> + clock-names = "baudclk", "apb_pclk";
> interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> reg-io-width = <4>;
> reg-shift = <2>;
> @@ -213,6 +222,8 @@
> uart5: serial@ffa18000 {
> compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> reg = <0x0 0xffa18000 0x0 0x100>;
> + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
> + clock-names = "baudclk", "apb_pclk";
> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> reg-io-width = <4>;
> reg-shift = <2>;
> @@ -222,6 +233,8 @@
> uart6: serial@ffa20000 {
> compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> reg = <0x0 0xffa20000 0x0 0x100>;
> + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
> + clock-names = "baudclk", "apb_pclk";
> interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
> reg-io-width = <4>;
> reg-shift = <2>;
> @@ -231,6 +244,8 @@
> uart7: serial@ffa28000 {
> compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> reg = <0x0 0xffa28000 0x0 0x100>;
> + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
> + clock-names = "baudclk", "apb_pclk";
> interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
> reg-io-width = <4>;
> reg-shift = <2>;
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 04/30] arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528
2025-04-07 22:46 ` [PATCH v2 04/30] arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528 Jonas Karlman
@ 2025-04-08 3:21 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:21 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Heiko Stuebner
On 2025/4/8 06:46, Jonas Karlman wrote:
> Add pinctrl and gpio nodes for RK3528 and import rk3528-pinctrl.dtsi
> from vendor linux-6.1-stan-rkr5 kernel with the hdmi-pins-idle node
> removed due to missing label reference to pcfg_output_low_pull_down.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> Link: https://lore.kernel.org/r/20250228064024.3200000-5-jonas@kwiboo.se
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: a31fad19ae39ea27b5068e3b02bcbf30a905339b ]
>
> (cherry picked from commit 89a24fa2e923b68a42ccc8cc9cb2d5bdf291ac40)
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> .../src/arm64/rockchip/rk3528-pinctrl.dtsi | 1397 +++++++++++++++++
> dts/upstream/src/arm64/rockchip/rk3528.dtsi | 82 +
> 2 files changed, 1479 insertions(+)
> create mode 100644 dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi b/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi
> new file mode 100644
> index 000000000000..ea051362fb26
> --- /dev/null
> +++ b/dts/upstream/src/arm64/rockchip/rk3528-pinctrl.dtsi
> @@ -0,0 +1,1397 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
> + */
> +
> +#include <dt-bindings/pinctrl/rockchip.h>
> +#include "rockchip-pinconf.dtsi"
> +
> +/*
> + * This file is auto generated by pin2dts tool, please keep these code
> + * by adding changes at end of this file.
> + */
> +&pinctrl {
> + arm {
> + /omit-if-no-ref/
> + arm_pins: arm-pins {
> + rockchip,pins =
> + /* arm_avs */
> + <4 RK_PC4 3 &pcfg_pull_none>;
> + };
> + };
> +
> + clk {
> + /omit-if-no-ref/
> + clkm0_32k_out: clkm0-32k-out {
> + rockchip,pins =
> + /* clkm0_32k_out */
> + <3 RK_PC3 3 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + clkm1_32k_out: clkm1-32k-out {
> + rockchip,pins =
> + /* clkm1_32k_out */
> + <1 RK_PC3 1 &pcfg_pull_none>;
> + };
> + };
> +
> + emmc {
> + /omit-if-no-ref/
> + emmc_rstnout: emmc-rstnout {
> + rockchip,pins =
> + /* emmc_rstn */
> + <1 RK_PD6 1 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + emmc_bus8: emmc-bus8 {
> + rockchip,pins =
> + /* emmc_d0 */
> + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>,
> + /* emmc_d1 */
> + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>,
> + /* emmc_d2 */
> + <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>,
> + /* emmc_d3 */
> + <1 RK_PC7 1 &pcfg_pull_up_drv_level_2>,
> + /* emmc_d4 */
> + <1 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
> + /* emmc_d5 */
> + <1 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
> + /* emmc_d6 */
> + <1 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
> + /* emmc_d7 */
> + <1 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + emmc_clk: emmc-clk {
> + rockchip,pins =
> + /* emmc_clk */
> + <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + emmc_cmd: emmc-cmd {
> + rockchip,pins =
> + /* emmc_cmd */
> + <1 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + emmc_strb: emmc-strb {
> + rockchip,pins =
> + /* emmc_strb */
> + <1 RK_PD7 1 &pcfg_pull_none>;
> + };
> + };
> +
> + eth {
> + /omit-if-no-ref/
> + eth_pins: eth-pins {
> + rockchip,pins =
> + /* eth_clk_25m_out */
> + <3 RK_PB5 2 &pcfg_pull_none_drv_level_2>;
> + };
> + };
> +
> + fephy {
> + /omit-if-no-ref/
> + fephym0_led_dpx: fephym0-led_dpx {
> + rockchip,pins =
> + /* fephy_led_dpx_m0 */
> + <4 RK_PB5 2 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + fephym0_led_link: fephym0-led_link {
> + rockchip,pins =
> + /* fephy_led_link_m0 */
> + <4 RK_PC0 2 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + fephym0_led_spd: fephym0-led_spd {
> + rockchip,pins =
> + /* fephy_led_spd_m0 */
> + <4 RK_PB7 2 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + fephym1_led_dpx: fephym1-led_dpx {
> + rockchip,pins =
> + /* fephy_led_dpx_m1 */
> + <2 RK_PA4 5 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + fephym1_led_link: fephym1-led_link {
> + rockchip,pins =
> + /* fephy_led_link_m1 */
> + <2 RK_PA6 5 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + fephym1_led_spd: fephym1-led_spd {
> + rockchip,pins =
> + /* fephy_led_spd_m1 */
> + <2 RK_PA5 5 &pcfg_pull_none>;
> + };
> + };
> +
> + fspi {
> + /omit-if-no-ref/
> + fspi_pins: fspi-pins {
> + rockchip,pins =
> + /* fspi_clk */
> + <1 RK_PD5 2 &pcfg_pull_none>,
> + /* fspi_d0 */
> + <1 RK_PC4 2 &pcfg_pull_none>,
> + /* fspi_d1 */
> + <1 RK_PC5 2 &pcfg_pull_none>,
> + /* fspi_d2 */
> + <1 RK_PC6 2 &pcfg_pull_none>,
> + /* fspi_d3 */
> + <1 RK_PC7 2 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + fspi_csn0: fspi-csn0 {
> + rockchip,pins =
> + /* fspi_csn0 */
> + <1 RK_PD0 2 &pcfg_pull_none>;
> + };
> + /omit-if-no-ref/
> + fspi_csn1: fspi-csn1 {
> + rockchip,pins =
> + /* fspi_csn1 */
> + <1 RK_PD1 2 &pcfg_pull_none>;
> + };
> + };
> +
> + gpu {
> + /omit-if-no-ref/
> + gpu_pins: gpu-pins {
> + rockchip,pins =
> + /* gpu_avs */
> + <4 RK_PC3 3 &pcfg_pull_none>;
> + };
> + };
> +
> + hdmi {
> + /omit-if-no-ref/
> + hdmi_pins: hdmi-pins {
> + rockchip,pins =
> + /* hdmi_tx_cec */
> + <0 RK_PA3 1 &pcfg_pull_none>,
> + /* hdmi_tx_hpd */
> + <0 RK_PA2 1 &pcfg_pull_none>,
> + /* hdmi_tx_scl */
> + <0 RK_PA4 1 &pcfg_pull_none>,
> + /* hdmi_tx_sda */
> + <0 RK_PA5 1 &pcfg_pull_none>;
> + };
> + };
> +
> + hsm {
> + /omit-if-no-ref/
> + hsmm0_pins: hsmm0-pins {
> + rockchip,pins =
> + /* hsm_clk_out_m0 */
> + <2 RK_PA2 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + hsmm1_pins: hsmm1-pins {
> + rockchip,pins =
> + /* hsm_clk_out_m1 */
> + <1 RK_PA4 3 &pcfg_pull_none>;
> + };
> + };
> +
> + i2c0 {
> + /omit-if-no-ref/
> + i2c0m0_xfer: i2c0m0-xfer {
> + rockchip,pins =
> + /* i2c0_scl_m0 */
> + <4 RK_PC4 2 &pcfg_pull_none_smt>,
> + /* i2c0_sda_m0 */
> + <4 RK_PC3 2 &pcfg_pull_none_smt>;
> + };
> +
> + /omit-if-no-ref/
> + i2c0m1_xfer: i2c0m1-xfer {
> + rockchip,pins =
> + /* i2c0_scl_m1 */
> + <4 RK_PA1 2 &pcfg_pull_none_smt>,
> + /* i2c0_sda_m1 */
> + <4 RK_PA0 2 &pcfg_pull_none_smt>;
> + };
> + };
> +
> + i2c1 {
> + /omit-if-no-ref/
> + i2c1m0_xfer: i2c1m0-xfer {
> + rockchip,pins =
> + /* i2c1_scl_m0 */
> + <4 RK_PA3 2 &pcfg_pull_none_smt>,
> + /* i2c1_sda_m0 */
> + <4 RK_PA2 2 &pcfg_pull_none_smt>;
> + };
> +
> + /omit-if-no-ref/
> + i2c1m1_xfer: i2c1m1-xfer {
> + rockchip,pins =
> + /* i2c1_scl_m1 */
> + <4 RK_PC5 4 &pcfg_pull_none_smt>,
> + /* i2c1_sda_m1 */
> + <4 RK_PC6 4 &pcfg_pull_none_smt>;
> + };
> + };
> +
> + i2c2 {
> + /omit-if-no-ref/
> + i2c2m0_xfer: i2c2m0-xfer {
> + rockchip,pins =
> + /* i2c2_scl_m0 */
> + <0 RK_PA4 2 &pcfg_pull_none_smt>,
> + /* i2c2_sda_m0 */
> + <0 RK_PA5 2 &pcfg_pull_none_smt>;
> + };
> +
> + /omit-if-no-ref/
> + i2c2m1_xfer: i2c2m1-xfer {
> + rockchip,pins =
> + /* i2c2_scl_m1 */
> + <1 RK_PA5 3 &pcfg_pull_none_smt>,
> + /* i2c2_sda_m1 */
> + <1 RK_PA6 3 &pcfg_pull_none_smt>;
> + };
> + };
> +
> + i2c3 {
> + /omit-if-no-ref/
> + i2c3m0_xfer: i2c3m0-xfer {
> + rockchip,pins =
> + /* i2c3_scl_m0 */
> + <1 RK_PA0 2 &pcfg_pull_none_smt>,
> + /* i2c3_sda_m0 */
> + <1 RK_PA1 2 &pcfg_pull_none_smt>;
> + };
> +
> + /omit-if-no-ref/
> + i2c3m1_xfer: i2c3m1-xfer {
> + rockchip,pins =
> + /* i2c3_scl_m1 */
> + <3 RK_PC1 5 &pcfg_pull_none_smt>,
> + /* i2c3_sda_m1 */
> + <3 RK_PC3 5 &pcfg_pull_none_smt>;
> + };
> + };
> +
> + i2c4 {
> + /omit-if-no-ref/
> + i2c4_xfer: i2c4-xfer {
> + rockchip,pins =
> + /* i2c4_scl */
> + <2 RK_PA0 4 &pcfg_pull_none_smt>,
> + /* i2c4_sda */
> + <2 RK_PA1 4 &pcfg_pull_none_smt>;
> + };
> + };
> +
> + i2c5 {
> + /omit-if-no-ref/
> + i2c5m0_xfer: i2c5m0-xfer {
> + rockchip,pins =
> + /* i2c5_scl_m0 */
> + <1 RK_PB2 3 &pcfg_pull_none_smt>,
> + /* i2c5_sda_m0 */
> + <1 RK_PB3 3 &pcfg_pull_none_smt>;
> + };
> +
> + /omit-if-no-ref/
> + i2c5m1_xfer: i2c5m1-xfer {
> + rockchip,pins =
> + /* i2c5_scl_m1 */
> + <1 RK_PD2 3 &pcfg_pull_none_smt>,
> + /* i2c5_sda_m1 */
> + <1 RK_PD3 3 &pcfg_pull_none_smt>;
> + };
> + };
> +
> + i2c6 {
> + /omit-if-no-ref/
> + i2c6m0_xfer: i2c6m0-xfer {
> + rockchip,pins =
> + /* i2c6_scl_m0 */
> + <3 RK_PB2 5 &pcfg_pull_none_smt>,
> + /* i2c6_sda_m0 */
> + <3 RK_PB3 5 &pcfg_pull_none_smt>;
> + };
> +
> + /omit-if-no-ref/
> + i2c6m1_xfer: i2c6m1-xfer {
> + rockchip,pins =
> + /* i2c6_scl_m1 */
> + <1 RK_PD4 3 &pcfg_pull_none_smt>,
> + /* i2c6_sda_m1 */
> + <1 RK_PD7 3 &pcfg_pull_none_smt>;
> + };
> + };
> +
> + i2c7 {
> + /omit-if-no-ref/
> + i2c7_xfer: i2c7-xfer {
> + rockchip,pins =
> + /* i2c7_scl */
> + <2 RK_PA5 4 &pcfg_pull_none_smt>,
> + /* i2c7_sda */
> + <2 RK_PA6 4 &pcfg_pull_none_smt>;
> + };
> + };
> +
> + i2s0 {
> + /omit-if-no-ref/
> + i2s0m0_lrck: i2s0m0-lrck {
> + rockchip,pins =
> + /* i2s0_lrck_m0 */
> + <3 RK_PB6 1 &pcfg_pull_none_smt>;
> + };
> +
> + /omit-if-no-ref/
> + i2s0m0_mclk: i2s0m0-mclk {
> + rockchip,pins =
> + /* i2s0_mclk_m0 */
> + <3 RK_PB4 1 &pcfg_pull_none_smt>;
> + };
> +
> + /omit-if-no-ref/
> + i2s0m0_sclk: i2s0m0-sclk {
> + rockchip,pins =
> + /* i2s0_sclk_m0 */
> + <3 RK_PB5 1 &pcfg_pull_none_smt>;
> + };
> +
> + /omit-if-no-ref/
> + i2s0m0_sdi: i2s0m0-sdi {
> + rockchip,pins =
> + /* i2s0m0_sdi */
> + <3 RK_PB7 1 &pcfg_pull_none>;
> + };
> + /omit-if-no-ref/
> + i2s0m0_sdo: i2s0m0-sdo {
> + rockchip,pins =
> + /* i2s0m0_sdo */
> + <3 RK_PC0 1 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + i2s0m1_lrck: i2s0m1-lrck {
> + rockchip,pins =
> + /* i2s0_lrck_m1 */
> + <1 RK_PB6 1 &pcfg_pull_none_smt>;
> + };
> +
> + /omit-if-no-ref/
> + i2s0m1_mclk: i2s0m1-mclk {
> + rockchip,pins =
> + /* i2s0_mclk_m1 */
> + <1 RK_PB4 1 &pcfg_pull_none_smt>;
> + };
> +
> + /omit-if-no-ref/
> + i2s0m1_sclk: i2s0m1-sclk {
> + rockchip,pins =
> + /* i2s0_sclk_m1 */
> + <1 RK_PB5 1 &pcfg_pull_none_smt>;
> + };
> +
> + /omit-if-no-ref/
> + i2s0m1_sdi: i2s0m1-sdi {
> + rockchip,pins =
> + /* i2s0m1_sdi */
> + <1 RK_PB7 1 &pcfg_pull_none>;
> + };
> + /omit-if-no-ref/
> + i2s0m1_sdo: i2s0m1-sdo {
> + rockchip,pins =
> + /* i2s0m1_sdo */
> + <1 RK_PC0 1 &pcfg_pull_none>;
> + };
> + };
> +
> + i2s1 {
> + /omit-if-no-ref/
> + i2s1_lrck: i2s1-lrck {
> + rockchip,pins =
> + /* i2s1_lrck */
> + <4 RK_PA6 1 &pcfg_pull_none_smt>;
> + };
> +
> + /omit-if-no-ref/
> + i2s1_mclk: i2s1-mclk {
> + rockchip,pins =
> + /* i2s1_mclk */
> + <4 RK_PA4 1 &pcfg_pull_none_smt>;
> + };
> +
> + /omit-if-no-ref/
> + i2s1_sclk: i2s1-sclk {
> + rockchip,pins =
> + /* i2s1_sclk */
> + <4 RK_PA5 1 &pcfg_pull_none_smt>;
> + };
> +
> + /omit-if-no-ref/
> + i2s1_sdi0: i2s1-sdi0 {
> + rockchip,pins =
> + /* i2s1_sdi0 */
> + <4 RK_PB4 1 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + i2s1_sdi1: i2s1-sdi1 {
> + rockchip,pins =
> + /* i2s1_sdi1 */
> + <4 RK_PB3 1 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + i2s1_sdi2: i2s1-sdi2 {
> + rockchip,pins =
> + /* i2s1_sdi2 */
> + <4 RK_PA3 1 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + i2s1_sdi3: i2s1-sdi3 {
> + rockchip,pins =
> + /* i2s1_sdi3 */
> + <4 RK_PA2 1 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + i2s1_sdo0: i2s1-sdo0 {
> + rockchip,pins =
> + /* i2s1_sdo0 */
> + <4 RK_PA7 1 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + i2s1_sdo1: i2s1-sdo1 {
> + rockchip,pins =
> + /* i2s1_sdo1 */
> + <4 RK_PB0 1 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + i2s1_sdo2: i2s1-sdo2 {
> + rockchip,pins =
> + /* i2s1_sdo2 */
> + <4 RK_PB1 1 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + i2s1_sdo3: i2s1-sdo3 {
> + rockchip,pins =
> + /* i2s1_sdo3 */
> + <4 RK_PB2 1 &pcfg_pull_none>;
> + };
> + };
> +
> + jtag {
> + /omit-if-no-ref/
> + jtagm0_pins: jtagm0-pins {
> + rockchip,pins =
> + /* jtag_cpu_tck_m0 */
> + <2 RK_PA2 2 &pcfg_pull_none>,
> + /* jtag_cpu_tms_m0 */
> + <2 RK_PA3 2 &pcfg_pull_none>,
> + /* jtag_mcu_tck_m0 */
> + <2 RK_PA4 2 &pcfg_pull_none>,
> + /* jtag_mcu_tms_m0 */
> + <2 RK_PA5 2 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + jtagm1_pins: jtagm1-pins {
> + rockchip,pins =
> + /* jtag_cpu_tck_m1 */
> + <4 RK_PD0 2 &pcfg_pull_none>,
> + /* jtag_cpu_tms_m1 */
> + <4 RK_PC7 2 &pcfg_pull_none>,
> + /* jtag_mcu_tck_m1 */
> + <4 RK_PD0 3 &pcfg_pull_none>,
> + /* jtag_mcu_tms_m1 */
> + <4 RK_PC7 3 &pcfg_pull_none>;
> + };
> + };
> +
> + pcie {
> + /omit-if-no-ref/
> + pciem0_pins: pciem0-pins {
> + rockchip,pins =
> + /* pcie_clkreqn_m0 */
> + <3 RK_PA6 5 &pcfg_pull_none>,
> + /* pcie_perstn_m0 */
> + <3 RK_PB0 5 &pcfg_pull_none>,
> + /* pcie_waken_m0 */
> + <3 RK_PA7 5 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pciem1_pins: pciem1-pins {
> + rockchip,pins =
> + /* pcie_clkreqn_m1 */
> + <1 RK_PA0 4 &pcfg_pull_none>,
> + /* pcie_perstn_m1 */
> + <1 RK_PA2 4 &pcfg_pull_none>,
> + /* pcie_waken_m1 */
> + <1 RK_PA1 4 &pcfg_pull_none>;
> + };
> + };
> +
> + pdm {
> + /omit-if-no-ref/
> + pdm_clk0: pdm-clk0 {
> + rockchip,pins =
> + /* pdm_clk0 */
> + <4 RK_PB5 3 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pdm_clk1: pdm-clk1 {
> + rockchip,pins =
> + /* pdm_clk1 */
> + <4 RK_PA4 3 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pdm_sdi0: pdm-sdi0 {
> + rockchip,pins =
> + /* pdm_sdi0 */
> + <4 RK_PB2 3 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pdm_sdi1: pdm-sdi1 {
> + rockchip,pins =
> + /* pdm_sdi1 */
> + <4 RK_PB1 3 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pdm_sdi2: pdm-sdi2 {
> + rockchip,pins =
> + /* pdm_sdi2 */
> + <4 RK_PB3 3 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + pdm_sdi3: pdm-sdi3 {
> + rockchip,pins =
> + /* pdm_sdi3 */
> + <4 RK_PC1 3 &pcfg_pull_none>;
> + };
> + };
> +
> + pmu {
> + /omit-if-no-ref/
> + pmu_pins: pmu-pins {
> + rockchip,pins =
> + /* pmu_debug */
> + <4 RK_PA0 4 &pcfg_pull_none>;
> + };
> + };
> +
> + pwm0 {
> + /omit-if-no-ref/
> + pwm0m0_pins: pwm0m0-pins {
> + rockchip,pins =
> + /* pwm0_m0 */
> + <4 RK_PC3 1 &pcfg_pull_none_drv_level_0>;
> + };
> +
> + /omit-if-no-ref/
> + pwm0m1_pins: pwm0m1-pins {
> + rockchip,pins =
> + /* pwm0_m1 */
> + <1 RK_PA2 5 &pcfg_pull_none_drv_level_0>;
> + };
> + };
> +
> + pwm1 {
> + /omit-if-no-ref/
> + pwm1m0_pins: pwm1m0-pins {
> + rockchip,pins =
> + /* pwm1_m0 */
> + <4 RK_PC4 1 &pcfg_pull_none_drv_level_0>;
> + };
> +
> + /omit-if-no-ref/
> + pwm1m1_pins: pwm1m1-pins {
> + rockchip,pins =
> + /* pwm1_m1 */
> + <1 RK_PA3 4 &pcfg_pull_none_drv_level_0>;
> + };
> + };
> +
> + pwm2 {
> + /omit-if-no-ref/
> + pwm2m0_pins: pwm2m0-pins {
> + rockchip,pins =
> + /* pwm2_m0 */
> + <4 RK_PC5 1 &pcfg_pull_none_drv_level_0>;
> + };
> +
> + /omit-if-no-ref/
> + pwm2m1_pins: pwm2m1-pins {
> + rockchip,pins =
> + /* pwm2_m1 */
> + <1 RK_PA7 2 &pcfg_pull_none_drv_level_0>;
> + };
> + };
> +
> + pwm3 {
> + /omit-if-no-ref/
> + pwm3m0_pins: pwm3m0-pins {
> + rockchip,pins =
> + /* pwm3_m0 */
> + <4 RK_PC6 1 &pcfg_pull_none_drv_level_0>;
> + };
> +
> + /omit-if-no-ref/
> + pwm3m1_pins: pwm3m1-pins {
> + rockchip,pins =
> + /* pwm3_m1 */
> + <2 RK_PA4 3 &pcfg_pull_none_drv_level_0>;
> + };
> + };
> +
> + pwm4 {
> + /omit-if-no-ref/
> + pwm4m0_pins: pwm4m0-pins {
> + rockchip,pins =
> + /* pwm4_m0 */
> + <4 RK_PB7 1 &pcfg_pull_none_drv_level_0>;
> + };
> +
> + /omit-if-no-ref/
> + pwm4m1_pins: pwm4m1-pins {
> + rockchip,pins =
> + /* pwm4_m1 */
> + <1 RK_PA4 2 &pcfg_pull_none_drv_level_0>;
> + };
> + };
> +
> + pwm5 {
> + /omit-if-no-ref/
> + pwm5m0_pins: pwm5m0-pins {
> + rockchip,pins =
> + /* pwm5_m0 */
> + <4 RK_PC0 1 &pcfg_pull_none_drv_level_0>;
> + };
> +
> + /omit-if-no-ref/
> + pwm5m1_pins: pwm5m1-pins {
> + rockchip,pins =
> + /* pwm5_m1 */
> + <3 RK_PC3 1 &pcfg_pull_none_drv_level_0>;
> + };
> + };
> +
> + pwm6 {
> + /omit-if-no-ref/
> + pwm6m0_pins: pwm6m0-pins {
> + rockchip,pins =
> + /* pwm6_m0 */
> + <4 RK_PC1 1 &pcfg_pull_none_drv_level_0>;
> + };
> +
> + /omit-if-no-ref/
> + pwm6m1_pins: pwm6m1-pins {
> + rockchip,pins =
> + /* pwm6_m1 */
> + <1 RK_PC3 3 &pcfg_pull_none_drv_level_0>;
> + };
> +
> + /omit-if-no-ref/
> + pwm6m2_pins: pwm6m2-pins {
> + rockchip,pins =
> + /* pwm6_m2 */
> + <3 RK_PC1 1 &pcfg_pull_none_drv_level_0>;
> + };
> + };
> +
> + pwm7 {
> + /omit-if-no-ref/
> + pwm7m0_pins: pwm7m0-pins {
> + rockchip,pins =
> + /* pwm7_m0 */
> + <4 RK_PC2 1 &pcfg_pull_none_drv_level_0>;
> + };
> +
> + /omit-if-no-ref/
> + pwm7m1_pins: pwm7m1-pins {
> + rockchip,pins =
> + /* pwm7_m1 */
> + <1 RK_PC2 2 &pcfg_pull_none_drv_level_0>;
> + };
> + };
> +
> + pwr {
> + /omit-if-no-ref/
> + pwr_pins: pwr-pins {
> + rockchip,pins =
> + /* pwr_ctrl0 */
> + <4 RK_PC2 2 &pcfg_pull_none>,
> + /* pwr_ctrl1 */
> + <4 RK_PB6 1 &pcfg_pull_none>;
> + };
> + };
> +
> + ref {
> + /omit-if-no-ref/
> + refm0_pins: refm0-pins {
> + rockchip,pins =
> + /* ref_clk_out_m0 */
> + <0 RK_PA1 1 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + refm1_pins: refm1-pins {
> + rockchip,pins =
> + /* ref_clk_out_m1 */
> + <3 RK_PC3 6 &pcfg_pull_none>;
> + };
> + };
> +
> + rgmii {
> + /omit-if-no-ref/
> + rgmii_miim: rgmii-miim {
> + rockchip,pins =
> + /* rgmii_mdc */
> + <3 RK_PB6 2 &pcfg_pull_none_drv_level_2>,
> + /* rgmii_mdio */
> + <3 RK_PB7 2 &pcfg_pull_none_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + rgmii_rx_bus2: rgmii-rx_bus2 {
> + rockchip,pins =
> + /* rgmii_rxd0 */
> + <3 RK_PA3 2 &pcfg_pull_none>,
> + /* rgmii_rxd1 */
> + <3 RK_PA2 2 &pcfg_pull_none>,
> + /* rgmii_rxdv_crs */
> + <3 RK_PC2 2 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + rgmii_tx_bus2: rgmii-tx_bus2 {
> + rockchip,pins =
> + /* rgmii_txd0 */
> + <3 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
> + /* rgmii_txd1 */
> + <3 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
> + /* rgmii_txen */
> + <3 RK_PC0 2 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + rgmii_rgmii_clk: rgmii-rgmii_clk {
> + rockchip,pins =
> + /* rgmii_rxclk */
> + <3 RK_PA5 2 &pcfg_pull_none>,
> + /* rgmii_txclk */
> + <3 RK_PA4 2 &pcfg_pull_none_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + rgmii_rgmii_bus: rgmii-rgmii_bus {
> + rockchip,pins =
> + /* rgmii_rxd2 */
> + <3 RK_PA7 2 &pcfg_pull_none>,
> + /* rgmii_rxd3 */
> + <3 RK_PA6 2 &pcfg_pull_none>,
> + /* rgmii_txd2 */
> + <3 RK_PB1 2 &pcfg_pull_none_drv_level_2>,
> + /* rgmii_txd3 */
> + <3 RK_PB0 2 &pcfg_pull_none_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + rgmii_clk: rgmii-clk {
> + rockchip,pins =
> + /* rgmii_clk */
> + <3 RK_PB4 2 &pcfg_pull_none>;
> + };
> + /omit-if-no-ref/
> + rgmii_txer: rgmii-txer {
> + rockchip,pins =
> + /* rgmii_txer */
> + <3 RK_PC1 2 &pcfg_pull_none>;
> + };
> + };
> +
> + scr {
> + /omit-if-no-ref/
> + scrm0_pins: scrm0-pins {
> + rockchip,pins =
> + /* scr_clk_m0 */
> + <1 RK_PA2 3 &pcfg_pull_none>,
> + /* scr_data_m0 */
> + <1 RK_PA1 3 &pcfg_pull_none>,
> + /* scr_detn_m0 */
> + <1 RK_PA0 3 &pcfg_pull_none>,
> + /* scr_rstn_m0 */
> + <1 RK_PA3 3 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + scrm1_pins: scrm1-pins {
> + rockchip,pins =
> + /* scr_clk_m1 */
> + <2 RK_PA5 3 &pcfg_pull_none>,
> + /* scr_data_m1 */
> + <2 RK_PA3 4 &pcfg_pull_none>,
> + /* scr_detn_m1 */
> + <2 RK_PA6 3 &pcfg_pull_none>,
> + /* scr_rstn_m1 */
> + <2 RK_PA4 4 &pcfg_pull_none>;
> + };
> + };
> +
> + sdio0 {
> + /omit-if-no-ref/
> + sdio0_bus4: sdio0-bus4 {
> + rockchip,pins =
> + /* sdio0_d0 */
> + <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
> + /* sdio0_d1 */
> + <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
> + /* sdio0_d2 */
> + <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
> + /* sdio0_d3 */
> + <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + sdio0_clk: sdio0-clk {
> + rockchip,pins =
> + /* sdio0_clk */
> + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + sdio0_cmd: sdio0-cmd {
> + rockchip,pins =
> + /* sdio0_cmd */
> + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + sdio0_det: sdio0-det {
> + rockchip,pins =
> + /* sdio0_det */
> + <1 RK_PA6 1 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + sdio0_pwren: sdio0-pwren {
> + rockchip,pins =
> + /* sdio0_pwren */
> + <1 RK_PA7 1 &pcfg_pull_none>;
> + };
> + };
> +
> + sdio1 {
> + /omit-if-no-ref/
> + sdio1_bus4: sdio1-bus4 {
> + rockchip,pins =
> + /* sdio1_d0 */
> + <3 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
> + /* sdio1_d1 */
> + <3 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
> + /* sdio1_d2 */
> + <3 RK_PB0 1 &pcfg_pull_up_drv_level_2>,
> + /* sdio1_d3 */
> + <3 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + sdio1_clk: sdio1-clk {
> + rockchip,pins =
> + /* sdio1_clk */
> + <3 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + sdio1_cmd: sdio1-cmd {
> + rockchip,pins =
> + /* sdio1_cmd */
> + <3 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + sdio1_det: sdio1-det {
> + rockchip,pins =
> + /* sdio1_det */
> + <3 RK_PB3 1 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + sdio1_pwren: sdio1-pwren {
> + rockchip,pins =
> + /* sdio1_pwren */
> + <3 RK_PB2 1 &pcfg_pull_none>;
> + };
> + };
> +
> + sdmmc {
> + /omit-if-no-ref/
> + sdmmc_bus4: sdmmc-bus4 {
> + rockchip,pins =
> + /* sdmmc_d0 */
> + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
> + /* sdmmc_d1 */
> + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
> + /* sdmmc_d2 */
> + <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
> + /* sdmmc_d3 */
> + <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + sdmmc_clk: sdmmc-clk {
> + rockchip,pins =
> + /* sdmmc_clk */
> + <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + sdmmc_cmd: sdmmc-cmd {
> + rockchip,pins =
> + /* sdmmc_cmd */
> + <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + sdmmc_det: sdmmc-det {
> + rockchip,pins =
> + /* sdmmc_detn */
> + <2 RK_PA6 1 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + sdmmc_pwren: sdmmc-pwren {
> + rockchip,pins =
> + /* sdmmc_pwren */
> + <4 RK_PA1 1 &pcfg_pull_none>;
> + };
> + };
> +
> + spdif {
> + /omit-if-no-ref/
> + spdifm0_pins: spdifm0-pins {
> + rockchip,pins =
> + /* spdif_tx_m0 */
> + <4 RK_PA0 1 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + spdifm1_pins: spdifm1-pins {
> + rockchip,pins =
> + /* spdif_tx_m1 */
> + <1 RK_PC3 2 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + spdifm2_pins: spdifm2-pins {
> + rockchip,pins =
> + /* spdif_tx_m2 */
> + <3 RK_PC3 2 &pcfg_pull_none>;
> + };
> + };
> +
> + spi0 {
> + /omit-if-no-ref/
> + spi0_pins: spi0-pins {
> + rockchip,pins =
> + /* spi0_clk */
> + <4 RK_PB4 2 &pcfg_pull_none_drv_level_2>,
> + /* spi0_miso */
> + <4 RK_PB3 2 &pcfg_pull_none_drv_level_2>,
> + /* spi0_mosi */
> + <4 RK_PB2 2 &pcfg_pull_none_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + spi0_csn0: spi0-csn0 {
> + rockchip,pins =
> + /* spi0_csn0 */
> + <4 RK_PB6 2 &pcfg_pull_none_drv_level_2>;
> + };
> + /omit-if-no-ref/
> + spi0_csn1: spi0-csn1 {
> + rockchip,pins =
> + /* spi0_csn1 */
> + <4 RK_PC1 2 &pcfg_pull_none_drv_level_2>;
> + };
> + };
> +
> + spi1 {
> + /omit-if-no-ref/
> + spi1_pins: spi1-pins {
> + rockchip,pins =
> + /* spi1_clk */
> + <1 RK_PB6 2 &pcfg_pull_none_drv_level_2>,
> + /* spi1_miso */
> + <1 RK_PC0 2 &pcfg_pull_none_drv_level_2>,
> + /* spi1_mosi */
> + <1 RK_PB7 2 &pcfg_pull_none_drv_level_2>;
> + };
> +
> + /omit-if-no-ref/
> + spi1_csn0: spi1-csn0 {
> + rockchip,pins =
> + /* spi1_csn0 */
> + <1 RK_PC1 1 &pcfg_pull_none_drv_level_2>;
> + };
> + /omit-if-no-ref/
> + spi1_csn1: spi1-csn1 {
> + rockchip,pins =
> + /* spi1_csn1 */
> + <1 RK_PC2 1 &pcfg_pull_none_drv_level_2>;
> + };
> + };
> +
> + tsi0 {
> + /omit-if-no-ref/
> + tsi0_pins: tsi0-pins {
> + rockchip,pins =
> + /* tsi0_clkin */
> + <3 RK_PB2 3 &pcfg_pull_none>,
> + /* tsi0_d0 */
> + <3 RK_PB1 3 &pcfg_pull_none>,
> + /* tsi0_d1 */
> + <3 RK_PB5 3 &pcfg_pull_none>,
> + /* tsi0_d2 */
> + <3 RK_PB6 3 &pcfg_pull_none>,
> + /* tsi0_d3 */
> + <3 RK_PB7 3 &pcfg_pull_none>,
> + /* tsi0_d4 */
> + <3 RK_PA3 3 &pcfg_pull_none>,
> + /* tsi0_d5 */
> + <3 RK_PA2 3 &pcfg_pull_none>,
> + /* tsi0_d6 */
> + <3 RK_PA1 3 &pcfg_pull_none>,
> + /* tsi0_d7 */
> + <3 RK_PA0 3 &pcfg_pull_none>,
> + /* tsi0_fail */
> + <3 RK_PC0 3 &pcfg_pull_none>,
> + /* tsi0_sync */
> + <3 RK_PB4 3 &pcfg_pull_none>,
> + /* tsi0_valid */
> + <3 RK_PB3 3 &pcfg_pull_none>;
> + };
> + };
> +
> + tsi1 {
> + /omit-if-no-ref/
> + tsi1_pins: tsi1-pins {
> + rockchip,pins =
> + /* tsi1_clkin */
> + <3 RK_PA5 3 &pcfg_pull_none>,
> + /* tsi1_d0 */
> + <3 RK_PA4 3 &pcfg_pull_none>,
> + /* tsi1_sync */
> + <3 RK_PA7 3 &pcfg_pull_none>,
> + /* tsi1_valid */
> + <3 RK_PA6 3 &pcfg_pull_none>;
> + };
> + };
> +
> + uart0 {
> + /omit-if-no-ref/
> + uart0m0_xfer: uart0m0-xfer {
> + rockchip,pins =
> + /* uart0_rx_m0 */
> + <4 RK_PC7 1 &pcfg_pull_up>,
> + /* uart0_tx_m0 */
> + <4 RK_PD0 1 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + uart0m1_xfer: uart0m1-xfer {
> + rockchip,pins =
> + /* uart0_rx_m1 */
> + <2 RK_PA0 2 &pcfg_pull_up>,
> + /* uart0_tx_m1 */
> + <2 RK_PA1 2 &pcfg_pull_up>;
> + };
> + };
> +
> + uart1 {
> + /omit-if-no-ref/
> + uart1m0_xfer: uart1m0-xfer {
> + rockchip,pins =
> + /* uart1_rx_m0 */
> + <4 RK_PA7 2 &pcfg_pull_up>,
> + /* uart1_tx_m0 */
> + <4 RK_PA6 2 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + uart1m1_xfer: uart1m1-xfer {
> + rockchip,pins =
> + /* uart1_rx_m1 */
> + <4 RK_PC6 2 &pcfg_pull_up>,
> + /* uart1_tx_m1 */
> + <4 RK_PC5 2 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + uart1_ctsn: uart1-ctsn {
> + rockchip,pins =
> + /* uart1_ctsn */
> + <4 RK_PA4 2 &pcfg_pull_none>;
> + };
> + /omit-if-no-ref/
> + uart1_rtsn: uart1-rtsn {
> + rockchip,pins =
> + /* uart1_rtsn */
> + <4 RK_PA5 2 &pcfg_pull_none>;
> + };
> + };
> +
> + uart2 {
> + /omit-if-no-ref/
> + uart2m0_xfer: uart2m0-xfer {
> + rockchip,pins =
> + /* uart2_rx_m0 */
> + <3 RK_PA0 1 &pcfg_pull_up>,
> + /* uart2_tx_m0 */
> + <3 RK_PA1 1 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + uart2m0_ctsn: uart2m0-ctsn {
> + rockchip,pins =
> + /* uart2m0_ctsn */
> + <3 RK_PA3 1 &pcfg_pull_none>;
> + };
> + /omit-if-no-ref/
> + uart2m0_rtsn: uart2m0-rtsn {
> + rockchip,pins =
> + /* uart2m0_rtsn */
> + <3 RK_PA2 1 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + uart2m1_xfer: uart2m1-xfer {
> + rockchip,pins =
> + /* uart2_rx_m1 */
> + <1 RK_PB0 1 &pcfg_pull_up>,
> + /* uart2_tx_m1 */
> + <1 RK_PB1 1 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + uart2m1_ctsn: uart2m1-ctsn {
> + rockchip,pins =
> + /* uart2m1_ctsn */
> + <1 RK_PB3 1 &pcfg_pull_none>;
> + };
> + /omit-if-no-ref/
> + uart2m1_rtsn: uart2m1-rtsn {
> + rockchip,pins =
> + /* uart2m1_rtsn */
> + <1 RK_PB2 1 &pcfg_pull_none>;
> + };
> + };
> +
> + uart3 {
> + /omit-if-no-ref/
> + uart3m0_xfer: uart3m0-xfer {
> + rockchip,pins =
> + /* uart3_rx_m0 */
> + <4 RK_PB0 2 &pcfg_pull_up>,
> + /* uart3_tx_m0 */
> + <4 RK_PB1 2 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + uart3m1_xfer: uart3m1-xfer {
> + rockchip,pins =
> + /* uart3_rx_m1 */
> + <4 RK_PB7 3 &pcfg_pull_up>,
> + /* uart3_tx_m1 */
> + <4 RK_PC0 3 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + uart3_ctsn: uart3-ctsn {
> + rockchip,pins =
> + /* uart3_ctsn */
> + <4 RK_PA3 3 &pcfg_pull_none>;
> + };
> + /omit-if-no-ref/
> + uart3_rtsn: uart3-rtsn {
> + rockchip,pins =
> + /* uart3_rtsn */
> + <4 RK_PA2 3 &pcfg_pull_none>;
> + };
> + };
> +
> + uart4 {
> + /omit-if-no-ref/
> + uart4_xfer: uart4-xfer {
> + rockchip,pins =
> + /* uart4_rx */
> + <2 RK_PA2 3 &pcfg_pull_up>,
> + /* uart4_tx */
> + <2 RK_PA3 3 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + uart4_ctsn: uart4-ctsn {
> + rockchip,pins =
> + /* uart4_ctsn */
> + <2 RK_PA1 3 &pcfg_pull_none>;
> + };
> + /omit-if-no-ref/
> + uart4_rtsn: uart4-rtsn {
> + rockchip,pins =
> + /* uart4_rtsn */
> + <2 RK_PA0 3 &pcfg_pull_none>;
> + };
> + };
> +
> + uart5 {
> + /omit-if-no-ref/
> + uart5m0_xfer: uart5m0-xfer {
> + rockchip,pins =
> + /* uart5_rx_m0 */
> + <1 RK_PA2 2 &pcfg_pull_up>,
> + /* uart5_tx_m0 */
> + <1 RK_PA3 2 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + uart5m0_ctsn: uart5m0-ctsn {
> + rockchip,pins =
> + /* uart5m0_ctsn */
> + <1 RK_PA6 2 &pcfg_pull_none>;
> + };
> + /omit-if-no-ref/
> + uart5m0_rtsn: uart5m0-rtsn {
> + rockchip,pins =
> + /* uart5m0_rtsn */
> + <1 RK_PA5 2 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + uart5m1_xfer: uart5m1-xfer {
> + rockchip,pins =
> + /* uart5_rx_m1 */
> + <1 RK_PD4 2 &pcfg_pull_up>,
> + /* uart5_tx_m1 */
> + <1 RK_PD7 2 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + uart5m1_ctsn: uart5m1-ctsn {
> + rockchip,pins =
> + /* uart5m1_ctsn */
> + <1 RK_PD3 2 &pcfg_pull_none>;
> + };
> + /omit-if-no-ref/
> + uart5m1_rtsn: uart5m1-rtsn {
> + rockchip,pins =
> + /* uart5m1_rtsn */
> + <1 RK_PD2 2 &pcfg_pull_none>;
> + };
> + };
> +
> + uart6 {
> + /omit-if-no-ref/
> + uart6m0_xfer: uart6m0-xfer {
> + rockchip,pins =
> + /* uart6_rx_m0 */
> + <3 RK_PA7 4 &pcfg_pull_up>,
> + /* uart6_tx_m0 */
> + <3 RK_PA6 4 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + uart6m1_xfer: uart6m1-xfer {
> + rockchip,pins =
> + /* uart6_rx_m1 */
> + <3 RK_PC3 4 &pcfg_pull_up>,
> + /* uart6_tx_m1 */
> + <3 RK_PC1 4 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + uart6_ctsn: uart6-ctsn {
> + rockchip,pins =
> + /* uart6_ctsn */
> + <3 RK_PA4 4 &pcfg_pull_none>;
> + };
> + /omit-if-no-ref/
> + uart6_rtsn: uart6-rtsn {
> + rockchip,pins =
> + /* uart6_rtsn */
> + <3 RK_PA5 4 &pcfg_pull_none>;
> + };
> + };
> +
> + uart7 {
> + /omit-if-no-ref/
> + uart7m0_xfer: uart7m0-xfer {
> + rockchip,pins =
> + /* uart7_rx_m0 */
> + <3 RK_PB3 4 &pcfg_pull_up>,
> + /* uart7_tx_m0 */
> + <3 RK_PB2 4 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + uart7m0_ctsn: uart7m0-ctsn {
> + rockchip,pins =
> + /* uart7m0_ctsn */
> + <3 RK_PB0 4 &pcfg_pull_none>;
> + };
> + /omit-if-no-ref/
> + uart7m0_rtsn: uart7m0-rtsn {
> + rockchip,pins =
> + /* uart7m0_rtsn */
> + <3 RK_PB1 4 &pcfg_pull_none>;
> + };
> +
> + /omit-if-no-ref/
> + uart7m1_xfer: uart7m1-xfer {
> + rockchip,pins =
> + /* uart7_rx_m1 */
> + <1 RK_PB3 4 &pcfg_pull_up>,
> + /* uart7_tx_m1 */
> + <1 RK_PB2 4 &pcfg_pull_up>;
> + };
> +
> + /omit-if-no-ref/
> + uart7m1_ctsn: uart7m1-ctsn {
> + rockchip,pins =
> + /* uart7m1_ctsn */
> + <1 RK_PB0 4 &pcfg_pull_none>;
> + };
> + /omit-if-no-ref/
> + uart7m1_rtsn: uart7m1-rtsn {
> + rockchip,pins =
> + /* uart7m1_rtsn */
> + <1 RK_PB1 4 &pcfg_pull_none>;
> + };
> + };
> +};
> diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> index 5b334690356a..b1713ed4d7e2 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> +++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> @@ -4,8 +4,10 @@
> * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
> */
>
> +#include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/pinctrl/rockchip.h>
> #include <dt-bindings/clock/rockchip,rk3528-cru.h>
>
> / {
> @@ -16,6 +18,11 @@
> #size-cells = <2>;
>
> aliases {
> + gpio0 = &gpio0;
> + gpio1 = &gpio1;
> + gpio2 = &gpio2;
> + gpio3 = &gpio3;
> + gpio4 = &gpio4;
> serial0 = &uart0;
> serial1 = &uart1;
> serial2 = &uart2;
> @@ -165,6 +172,11 @@
> #reset-cells = <1>;
> };
>
> + ioc_grf: syscon@ff540000 {
> + compatible = "rockchip,rk3528-ioc-grf", "syscon";
> + reg = <0x0 0xff540000 0x0 0x40000>;
> + };
> +
> uart0: serial@ff9f0000 {
> compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
> reg = <0x0 0xff9f0000 0x0 0x100>;
> @@ -251,5 +263,75 @@
> reg-shift = <2>;
> status = "disabled";
> };
> +
> + pinctrl: pinctrl {
> + compatible = "rockchip,rk3528-pinctrl";
> + rockchip,grf = <&ioc_grf>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + gpio0: gpio@ff610000 {
> + compatible = "rockchip,gpio-bank";
> + reg = <0x0 0xff610000 0x0 0x200>;
> + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
> + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl 0 0 32>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio1: gpio@ffaf0000 {
> + compatible = "rockchip,gpio-bank";
> + reg = <0x0 0xffaf0000 0x0 0x200>;
> + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
> + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl 0 32 32>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio2: gpio@ffb00000 {
> + compatible = "rockchip,gpio-bank";
> + reg = <0x0 0xffb00000 0x0 0x200>;
> + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl 0 64 32>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio3: gpio@ffb10000 {
> + compatible = "rockchip,gpio-bank";
> + reg = <0x0 0xffb10000 0x0 0x200>;
> + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl 0 96 32>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio4: gpio@ffb20000 {
> + compatible = "rockchip,gpio-bank";
> + reg = <0x0 0xffb20000 0x0 0x200>;
> + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
> + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl 0 128 32>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> };
> };
> +
> +#include "rk3528-pinctrl.dtsi"
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 05/30] arm64: dts: rockchip: Add rk3528 QoS register node
2025-04-07 22:46 ` [PATCH v2 05/30] arm64: dts: rockchip: Add rk3528 QoS register node Jonas Karlman
@ 2025-04-08 3:21 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:21 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Heiko Stuebner
On 2025/4/8 06:46, Jonas Karlman wrote:
> From: Chukun Pan <amadeus@jmu.edu.cn>
>
> The Quality-of-Service (QsS) node stores/restores specific
> register contents when the power domains is turned off/on.
> Add QoS node so that they can connect to the power domain.
>
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> Link: https://lore.kernel.org/r/20250306123809.273655-3-amadeus@jmu.edu.cn
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: 61a05d8ca3030a544175671f5fab7a8f29c24085 ]
>
> (cherry picked from commit 9ee90dfd6957fcc42ea94c43d195b01d1b286713)
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> dts/upstream/src/arm64/rockchip/rk3528.dtsi | 160 ++++++++++++++++++++
> 1 file changed, 160 insertions(+)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> index b1713ed4d7e2..0c0e7f151462 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> +++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> @@ -129,6 +129,166 @@
> #interrupt-cells = <3>;
> };
>
> + qos_crypto_a: qos@ff200000 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff200000 0x0 0x20>;
> + };
> +
> + qos_crypto_p: qos@ff200080 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff200080 0x0 0x20>;
> + };
> +
> + qos_dcf: qos@ff200100 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff200100 0x0 0x20>;
> + };
> +
> + qos_dft2apb: qos@ff200200 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff200200 0x0 0x20>;
> + };
> +
> + qos_dma2ddr: qos@ff200280 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff200280 0x0 0x20>;
> + };
> +
> + qos_dmac: qos@ff200300 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff200300 0x0 0x20>;
> + };
> +
> + qos_keyreader: qos@ff200380 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff200380 0x0 0x20>;
> + };
> +
> + qos_cpu: qos@ff210000 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff210000 0x0 0x20>;
> + };
> +
> + qos_debug: qos@ff210080 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff210080 0x0 0x20>;
> + };
> +
> + qos_gpu_m0: qos@ff220000 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff220000 0x0 0x20>;
> + };
> +
> + qos_gpu_m1: qos@ff220080 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff220080 0x0 0x20>;
> + };
> +
> + qos_pmu_mcu: qos@ff240000 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff240000 0x0 0x20>;
> + };
> +
> + qos_rkvdec: qos@ff250000 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff250000 0x0 0x20>;
> + };
> +
> + qos_rkvenc: qos@ff260000 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff260000 0x0 0x20>;
> + };
> +
> + qos_gmac0: qos@ff270000 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff270000 0x0 0x20>;
> + };
> +
> + qos_hdcp: qos@ff270080 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff270080 0x0 0x20>;
> + };
> +
> + qos_jpegdec: qos@ff270100 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff270100 0x0 0x20>;
> + };
> +
> + qos_rga2_m0ro: qos@ff270200 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff270200 0x0 0x20>;
> + };
> +
> + qos_rga2_m0wo: qos@ff270280 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff270280 0x0 0x20>;
> + };
> +
> + qos_sdmmc0: qos@ff270300 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff270300 0x0 0x20>;
> + };
> +
> + qos_usb2host: qos@ff270380 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff270380 0x0 0x20>;
> + };
> +
> + qos_vdpp: qos@ff270480 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff270480 0x0 0x20>;
> + };
> +
> + qos_vop: qos@ff270500 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff270500 0x0 0x20>;
> + };
> +
> + qos_emmc: qos@ff280000 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff280000 0x0 0x20>;
> + };
> +
> + qos_fspi: qos@ff280080 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff280080 0x0 0x20>;
> + };
> +
> + qos_gmac1: qos@ff280100 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff280100 0x0 0x20>;
> + };
> +
> + qos_pcie: qos@ff280180 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff280180 0x0 0x20>;
> + };
> +
> + qos_sdio0: qos@ff280200 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff280200 0x0 0x20>;
> + };
> +
> + qos_sdio1: qos@ff280280 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff280280 0x0 0x20>;
> + };
> +
> + qos_tsp: qos@ff280300 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff280300 0x0 0x20>;
> + };
> +
> + qos_usb3otg: qos@ff280380 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff280380 0x0 0x20>;
> + };
> +
> + qos_vpu: qos@ff280400 {
> + compatible = "rockchip,rk3528-qos", "syscon";
> + reg = <0x0 0xff280400 0x0 0x20>;
> + };
> +
> cru: clock-controller@ff4a0000 {
> compatible = "rockchip,rk3528-cru";
> reg = <0x0 0xff4a0000 0x0 0x30000>;
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 06/30] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC
2025-04-07 22:46 ` [PATCH v2 06/30] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC Jonas Karlman
@ 2025-04-08 3:21 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:21 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Heiko Stuebner
On 2025/4/8 06:46, Jonas Karlman wrote:
> From: Chukun Pan <amadeus@jmu.edu.cn>
>
> Same as RK3568, RK3528 uses SCMI clk instead of ARMCLK.
> Add SCMI clk for CPU, GPU and RNG will also use it.
>
> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
> Link: https://lore.kernel.org/r/20250307100008.789129-2-amadeus@jmu.edu.cn
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: fbcbc1fb93e14729bd87ab386b7f62694dcc8b51 ]
>
> (cherry picked from commit 6e03c7e28e2d929a420809a24b0379305a9fb86a)
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> dts/upstream/src/arm64/rockchip/rk3528.dtsi | 31 +++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> index 0c0e7f151462..4be53868f324 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> +++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> @@ -59,6 +59,7 @@
> reg = <0x0>;
> device_type = "cpu";
> enable-method = "psci";
> + clocks = <&scmi_clk SCMI_CLK_CPU>;
> };
>
> cpu1: cpu@1 {
> @@ -66,6 +67,7 @@
> reg = <0x1>;
> device_type = "cpu";
> enable-method = "psci";
> + clocks = <&scmi_clk SCMI_CLK_CPU>;
> };
>
> cpu2: cpu@2 {
> @@ -73,6 +75,7 @@
> reg = <0x2>;
> device_type = "cpu";
> enable-method = "psci";
> + clocks = <&scmi_clk SCMI_CLK_CPU>;
> };
>
> cpu3: cpu@3 {
> @@ -80,6 +83,22 @@
> reg = <0x3>;
> device_type = "cpu";
> enable-method = "psci";
> + clocks = <&scmi_clk SCMI_CLK_CPU>;
> + };
> + };
> +
> + firmware {
> + scmi: scmi {
> + compatible = "arm,scmi-smc";
> + arm,smc-id = <0x82000010>;
> + shmem = <&scmi_shmem>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + scmi_clk: protocol@14 {
> + reg = <0x14>;
> + #clock-cells = <1>;
> + };
> };
> };
>
> @@ -88,6 +107,18 @@
> method = "smc";
> };
>
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + scmi_shmem: shmem@10f000 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x0 0x0010f000 0x0 0x100>;
> + no-map;
> + };
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 07/30] arm64: dts: rockchip: Add SARADC node for RK3528
2025-04-07 22:46 ` [PATCH v2 07/30] arm64: dts: rockchip: Add SARADC node for RK3528 Jonas Karlman
@ 2025-04-08 3:21 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:21 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Heiko Stuebner
On 2025/4/8 06:46, Jonas Karlman wrote:
> Add a device tree node for the SARADC controller used by RK3528.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> Link: https://lore.kernel.org/r/20250304201642.831218-4-jonas@kwiboo.se
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: 6e58302c84ce90aadbecd41efe1f69098a6f91e5 ]
>
> (cherry picked from commit 8ba64ba5cb301bca777ba7f0d2a2a72f49af5ff2)
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> dts/upstream/src/arm64/rockchip/rk3528.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> index 4be53868f324..c2eaa0c6ea90 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> +++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> @@ -9,6 +9,7 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/rockchip.h>
> #include <dt-bindings/clock/rockchip,rk3528-cru.h>
> +#include <dt-bindings/reset/rockchip,rk3528-cru.h>
>
> / {
> compatible = "rockchip,rk3528";
> @@ -455,6 +456,18 @@
> status = "disabled";
> };
>
> + saradc: adc@ffae0000 {
> + compatible = "rockchip,rk3528-saradc";
> + reg = <0x0 0xffae0000 0x0 0x10000>;
> + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
> + clock-names = "saradc", "apb_pclk";
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&cru SRST_P_SARADC>;
> + reset-names = "saradc-apb";
> + #io-channel-cells = <1>;
> + status = "disabled";
> + };
> +
> pinctrl: pinctrl {
> compatible = "rockchip,rk3528-pinctrl";
> rockchip,grf = <&ioc_grf>;
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 08/30] arm64: dts: rockchip: Add SDHCI controller for RK3528
2025-04-07 22:46 ` [PATCH v2 08/30] arm64: dts: rockchip: Add SDHCI controller " Jonas Karlman
@ 2025-04-08 3:21 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:21 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Heiko Stuebner
On 2025/4/8 06:46, Jonas Karlman wrote:
> The SDHCI controller in Rockchip RK3528 is similar to the one included
> in RK3588.
>
> Add device tree node for the SDHCI controller in RK3528.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> Link: https://lore.kernel.org/r/20250305214108.1327208-3-jonas@kwiboo.se
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: a98cc47f79ab5b8059b748bf0bd59335edfff7d9 ]
>
> (cherry picked from commit db7a99c423dea0ead19d6a18053d898a762a3b48)
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> dts/upstream/src/arm64/rockchip/rk3528.dtsi | 24 +++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3528.dtsi b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> index c2eaa0c6ea90..26c3559d6a6d 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> +++ b/dts/upstream/src/arm64/rockchip/rk3528.dtsi
> @@ -468,6 +468,30 @@
> status = "disabled";
> };
>
> + sdhci: mmc@ffbf0000 {
> + compatible = "rockchip,rk3528-dwcmshc",
> + "rockchip,rk3588-dwcmshc";
> + reg = <0x0 0xffbf0000 0x0 0x10000>;
> + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
> + <&cru CCLK_SRC_EMMC>;
> + assigned-clock-rates = <200000000>, <24000000>,
> + <200000000>;
> + clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
> + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
> + <&cru TCLK_EMMC>;
> + clock-names = "core", "bus", "axi", "block", "timer";
> + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
> + max-frequency = <200000000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
> + <&emmc_strb>;
> + resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
> + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
> + <&cru SRST_T_EMMC>;
> + reset-names = "core", "bus", "axi", "block", "timer";
> + status = "disabled";
> + };
> +
> pinctrl: pinctrl {
> compatible = "rockchip,rk3528-pinctrl";
> rockchip,grf = <&ioc_grf>;
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 09/30] arm64: dts: rockchip: Add uart0 pinctrl to Radxa E20C
2025-04-07 22:46 ` [PATCH v2 09/30] arm64: dts: rockchip: Add uart0 pinctrl to Radxa E20C Jonas Karlman
@ 2025-04-08 3:22 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:22 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Heiko Stuebner
On 2025/4/8 06:46, Jonas Karlman wrote:
> Radxa E20C route UART0 M0 pins (GPIO4_C7 and GPIO4_D0) to the onboard
> CH340B for debug console use.
>
> Add pinctrl for UART0 M0 pins used for serial console.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> Link: https://lore.kernel.org/r/20250228064024.3200000-6-jonas@kwiboo.se
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: 0d2312f0d3e4ce74af0977c1519a07dfc71a82ac ]
>
> (cherry picked from commit 9bcf6ccdd87c3be48fe7d75150c6e403c5c0a42d)
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
> index d2cdb63d4a9d..5161d22330ab 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
> +++ b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
> @@ -18,5 +18,7 @@
> };
>
> &uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0m0_xfer>;
> status = "okay";
> };
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 10/30] arm64: dts: rockchip: Add leds node to Radxa E20C
2025-04-07 22:46 ` [PATCH v2 10/30] arm64: dts: rockchip: Add leds node " Jonas Karlman
@ 2025-04-08 3:22 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:22 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Heiko Stuebner
On 2025/4/8 06:46, Jonas Karlman wrote:
> Radxa E20C has three gpio controlled leds (sys, wan and lan).
>
> Add led nodes and set default trigger to heartbeat for the sys led and
> netdev for the lan and wan leds.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> Link: https://lore.kernel.org/r/20250304201642.831218-2-jonas@kwiboo.se
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: 6a709e003492e9878d5f1357be0b2e1162e1e6a6 ]
>
> (cherry picked from commit a3556ede6b48c7760ac3608ad77601fca26d2ce0)
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> .../src/arm64/rockchip/rk3528-radxa-e20c.dts | 48 +++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
> index 5161d22330ab..7f0237206405 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
> +++ b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
> @@ -6,6 +6,8 @@
> */
>
> /dts-v1/;
> +
> +#include <dt-bindings/leds/common.h>
> #include "rk3528.dtsi"
>
> / {
> @@ -15,6 +17,52 @@
> chosen {
> stdout-path = "serial0:1500000n8";
> };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&lan_led_g>, <&sys_led_g>, <&wan_led_g>;
> +
> + led-lan {
> + color = <LED_COLOR_ID_GREEN>;
> + default-state = "off";
> + function = LED_FUNCTION_LAN;
> + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "netdev";
> + };
> +
> + led-sys {
> + color = <LED_COLOR_ID_GREEN>;
> + default-state = "on";
> + function = LED_FUNCTION_HEARTBEAT;
> + gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>;
> + linux,default-trigger = "heartbeat";
> + };
> +
> + led-wan {
> + color = <LED_COLOR_ID_GREEN>;
> + default-state = "off";
> + function = LED_FUNCTION_WAN;
> + gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "netdev";
> + };
> + };
> +};
> +
> +&pinctrl {
> + leds {
> + lan_led_g: lan-led-g {
> + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + sys_led_g: sys-led-g {
> + rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + wan_led_g: wan-led-g {
> + rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> };
>
> &uart0 {
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 11/30] arm64: dts: rockchip: Add user button to Radxa E20C
2025-04-07 22:46 ` [PATCH v2 11/30] arm64: dts: rockchip: Add user button " Jonas Karlman
@ 2025-04-08 3:22 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:22 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Heiko Stuebner
On 2025/4/8 06:46, Jonas Karlman wrote:
> Radxa E20C has two buttons, one SARADC maskrom button and one GPIO user
> button.
>
> Add support for the user button using a gpio-keys node.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> Link: https://lore.kernel.org/r/20250304201642.831218-3-jonas@kwiboo.se
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: ad8afc8813567994164f2720189c819da8c22b99 ]
>
> (cherry picked from commit 6793b56b79df26ab3323e5293b97577d0786ddb3)
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> .../src/arm64/rockchip/rk3528-radxa-e20c.dts | 20 +++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
> index 7f0237206405..b378774d2a4e 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
> +++ b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
> @@ -7,6 +7,7 @@
>
> /dts-v1/;
>
> +#include <dt-bindings/input/input.h>
> #include <dt-bindings/leds/common.h>
> #include "rk3528.dtsi"
>
> @@ -18,6 +19,19 @@
> stdout-path = "serial0:1500000n8";
> };
>
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&user_key>;
> +
> + button-user {
> + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
> + label = "USER";
> + linux,code = <BTN_1>;
> + wakeup-source;
> + };
> + };
> +
> leds {
> compatible = "gpio-leds";
> pinctrl-names = "default";
> @@ -50,6 +64,12 @@
> };
>
> &pinctrl {
> + gpio-keys {
> + user_key: user-key {
> + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
> + };
> + };
> +
> leds {
> lan_led_g: lan-led-g {
> rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 12/30] arm64: dts: rockchip: Add maskrom button to Radxa E20C
2025-04-07 22:46 ` [PATCH v2 12/30] arm64: dts: rockchip: Add maskrom " Jonas Karlman
@ 2025-04-08 3:22 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:22 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Heiko Stuebner
On 2025/4/8 06:46, Jonas Karlman wrote:
> Radxa E20C has two buttons, one SARADC maskrom button and one GPIO user
> button.
>
> Add support for the maskrom button using a adc-keys node, also add the
> regulators used by SARADC controller.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> Link: https://lore.kernel.org/r/20250304201642.831218-5-jonas@kwiboo.se
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: 3a2819ee9c71d1c6388e456cc4eb042914d15d7e ]
>
> (cherry picked from commit 460ef5b623e5fa69843305faf50f6b1a8e81e1cd)
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> .../src/arm64/rockchip/rk3528-radxa-e20c.dts | 48 +++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
> index b378774d2a4e..5346ef457c2a 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
> +++ b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
> @@ -19,6 +19,20 @@
> stdout-path = "serial0:1500000n8";
> };
>
> + adc-keys {
> + compatible = "adc-keys";
> + io-channels = <&saradc 0>;
> + io-channel-names = "buttons";
> + keyup-threshold-microvolt = <1800000>;
> + poll-interval = <100>;
> +
> + button-maskrom {
> + label = "MASKROM";
> + linux,code = <KEY_SETUP>;
> + press-threshold-microvolt = <0>;
> + };
> + };
> +
> gpio-keys {
> compatible = "gpio-keys";
> pinctrl-names = "default";
> @@ -61,6 +75,35 @@
> linux,default-trigger = "netdev";
> };
> };
> +
> + vcc_1v8: regulator-1v8-vcc {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc_1v8";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + vin-supply = <&vcc_3v3>;
> + };
> +
> + vcc_3v3: regulator-3v3-vcc {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc_3v3";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <&vcc5v0_sys>;
> + };
> +
> + vcc5v0_sys: regulator-5v0-vcc-sys {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc5v0_sys";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> };
>
> &pinctrl {
> @@ -85,6 +128,11 @@
> };
> };
>
> +&saradc {
> + vref-supply = <&vcc_1v8>;
> + status = "okay";
> +};
> +
> &uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart0m0_xfer>;
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 13/30] arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C
2025-04-07 22:46 ` [PATCH v2 13/30] arm64: dts: rockchip: Enable onboard eMMC on " Jonas Karlman
@ 2025-04-08 3:22 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:22 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini, Sumit Garg
Cc: Yao Zi, Chukun Pan, u-boot, Heiko Stuebner
On 2025/4/8 06:46, Jonas Karlman wrote:
> The Radxa E20C may come with an onboard eMMC (8GB / 16GB / 32GB / 64GB).
>
> Enable support for the onboard eMMC on Radxa E20C.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> Link: https://lore.kernel.org/r/20250305214108.1327208-4-jonas@kwiboo.se
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: 3a01b5f14a8ae2d45aea5aeed30001ac1655de86 ]
>
> (cherry picked from commit bd4c8a1c08f92d863d89c0ddff59e5f5bc6a1e34)
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> .../src/arm64/rockchip/rk3528-radxa-e20c.dts | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
> index 5346ef457c2a..57a446b5cbd6 100644
> --- a/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
> +++ b/dts/upstream/src/arm64/rockchip/rk3528-radxa-e20c.dts
> @@ -15,6 +15,10 @@
> model = "Radxa E20C";
> compatible = "radxa,e20c", "rockchip,rk3528";
>
> + aliases {
> + mmc0 = &sdhci;
> + };
> +
> chosen {
> stdout-path = "serial0:1500000n8";
> };
> @@ -133,6 +137,17 @@
> status = "okay";
> };
>
> +&sdhci {
> + bus-width = <8>;
> + cap-mmc-highspeed;
> + no-sd;
> + no-sdio;
> + non-removable;
> + vmmc-supply = <&vcc_3v3>;
> + vqmmc-supply = <&vcc_1v8>;
> + status = "okay";
> +};
> +
> &uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart0m0_xfer>;
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 14/30] rockchip: mkimage: Add support for RK3528
2025-04-07 22:46 ` [PATCH v2 14/30] rockchip: mkimage: Add support for RK3528 Jonas Karlman
@ 2025-04-08 3:22 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:22 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot, Yifeng Zhao
On 2025/4/8 06:46, Jonas Karlman wrote:
> From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
>
> Add support for generating Rockchip Boot Image for RK3528.
>
> Similar to RK3568, the RK3528 has 64 KiB SRAM and 4 KiB of it is
> reserved for BootROM.
>
> Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> v2: No change
> ---
> tools/rkcommon.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tools/rkcommon.c b/tools/rkcommon.c
> index 3e52236b15a8..f158d1562284 100644
> --- a/tools/rkcommon.c
> +++ b/tools/rkcommon.c
> @@ -134,6 +134,7 @@ static struct spl_info spl_infos[] = {
> { "rk3399", "RK33", 0x30000 - 0x2000, false, RK_HEADER_V1 },
> { "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
> { "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
> + { "rk3528", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
> { "rk3568", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
> { "rk3588", "RK35", 0x100000 - 0x1000, false, RK_HEADER_V2 },
> };
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 15/30] ram: rockchip: Add basic support for RK3528
2025-04-07 22:46 ` [PATCH v2 15/30] ram: rockchip: Add basic " Jonas Karlman
@ 2025-04-08 3:22 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:22 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot
On 2025/4/8 06:46, Jonas Karlman wrote:
> Add support for reading DRAM size information from PMUGRF os_reg18 reg.
>
> Compared to most Rockchip SoCs the RK3528 use os_reg18 for DRAM info,
> instead of os_reg2.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> v2: No change
> ---
> arch/arm/mach-rockchip/sdram.c | 3 ++-
> drivers/ram/rockchip/Makefile | 1 +
> drivers/ram/rockchip/sdram_rk3528.c | 33 +++++++++++++++++++++++++++++
> 3 files changed, 36 insertions(+), 1 deletion(-)
> create mode 100644 drivers/ram/rockchip/sdram_rk3528.c
>
> diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
> index 0bdda77a7926..91a6606d461f 100644
> --- a/arch/arm/mach-rockchip/sdram.c
> +++ b/arch/arm/mach-rockchip/sdram.c
> @@ -110,7 +110,8 @@ static int rockchip_dram_init_banksize(void)
> u8 i, j;
>
> if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
> - !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
> + !IS_ENABLED(CONFIG_ROCKCHIP_RK3568) &&
> + !IS_ENABLED(CONFIG_ROCKCHIP_RK3528))
> return -ENOTSUPP;
>
> if (!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL))
> diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
> index 36dc0500dab5..f222cc99f1e4 100644
> --- a/drivers/ram/rockchip/Makefile
> +++ b/drivers/ram/rockchip/Makefile
> @@ -13,6 +13,7 @@ obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
> obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
> obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
> +obj-$(CONFIG_ROCKCHIP_RK3528) += sdram_rk3528.o
> obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o
> obj-$(CONFIG_ROCKCHIP_RK3588) += sdram_rk3588.o
> obj-$(CONFIG_ROCKCHIP_RV1126) += sdram_rv1126.o sdram_pctl_px30.o
> diff --git a/drivers/ram/rockchip/sdram_rk3528.c b/drivers/ram/rockchip/sdram_rk3528.c
> new file mode 100644
> index 000000000000..89d325bea667
> --- /dev/null
> +++ b/drivers/ram/rockchip/sdram_rk3528.c
> @@ -0,0 +1,33 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +// Copyright Contributors to the U-Boot project.
> +
> +#include <dm.h>
> +#include <ram.h>
> +#include <asm/arch-rockchip/sdram.h>
> +
> +#define PMUGRF_BASE 0xff370000
> +#define OS_REG18_REG 0x248
> +
> +static int rk3528_dmc_get_info(struct udevice *dev, struct ram_info *info)
> +{
> + info->base = CFG_SYS_SDRAM_BASE;
> + info->size = rockchip_sdram_size(PMUGRF_BASE + OS_REG18_REG);
> +
> + return 0;
> +}
> +
> +static struct ram_ops rk3528_dmc_ops = {
> + .get_info = rk3528_dmc_get_info,
> +};
> +
> +static const struct udevice_id rk3528_dmc_ids[] = {
> + { .compatible = "rockchip,rk3528-dmc" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk3528_dmc) = {
> + .name = "rockchip_rk3528_dmc",
> + .id = UCLASS_RAM,
> + .of_match = rk3528_dmc_ids,
> + .ops = &rk3528_dmc_ops,
> +};
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 16/30] clk: rockchip: Add support for RK3528
2025-04-07 22:46 ` [PATCH v2 16/30] clk: rockchip: Add " Jonas Karlman
@ 2025-04-08 3:23 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:23 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini,
Lukasz Majewski, Sean Anderson
Cc: Yao Zi, Chukun Pan, u-boot, Joseph Chen, Finley Xiao
On 2025/4/8 06:46, Jonas Karlman wrote:
> From: Joseph Chen <chenjh@rock-chips.com>
>
> Add clock driver for RK3528.
>
> Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with minor
> adjustments and fixes for mainline.
>
> Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> Changes in v2:
> - Use mainline Linux dt-bindings headers and rst-rk3528
> - Add TCLK_EMMC, BCLK_EMMC, ACLK_BUS_VOPGL_ROOT and XIN_OSC0_DIV
> - Add missing break for CLK_I2C5
> ---
> arch/arm/include/asm/arch-rockchip/clock.h | 17 +
> .../include/asm/arch-rockchip/cru_rk3528.h | 388 ++++
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk_pll.c | 23 +-
> drivers/clk/rockchip/clk_rk3528.c | 1754 +++++++++++++++++
> drivers/reset/Makefile | 2 +-
> drivers/reset/rst-rk3528.c | 302 +++
> 7 files changed, 2480 insertions(+), 7 deletions(-)
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3528.h
> create mode 100644 drivers/clk/rockchip/clk_rk3528.c
> create mode 100644 drivers/reset/rst-rk3528.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
> index 73e5283108b1..a9921fbb6e42 100644
> --- a/arch/arm/include/asm/arch-rockchip/clock.h
> +++ b/arch/arm/include/asm/arch-rockchip/clock.h
> @@ -15,6 +15,13 @@ struct udevice;
> #define RKCLK_PLL_MODE_NORMAL 1
> #define RKCLK_PLL_MODE_DEEP 2
>
> +/*
> + * PLL flags
> + */
> +#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
> +/* normal mode only. now only for pll_rk3036, pll_rk3328 type */
> +#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
> +
> enum {
> ROCKCHIP_SYSCON_NOC,
> ROCKCHIP_SYSCON_GRF,
> @@ -207,6 +214,16 @@ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
> */
> int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table,
> u32 reg_offset, u32 reg_number);
> +/*
> + * rk3528_reset_bind_lut() - Bind soft reset device as child of clock device
> + * using dedicated RK3528 lookup table
> + *
> + * @pdev: clock udevice
> + * @reg_offset: the first offset in cru for softreset registers
> + * @reg_number: the reg numbers of softreset registers
> + * Return: 0 success, or error value
> + */
> +int rk3528_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number);
> /*
> * rk3588_reset_bind_lut() - Bind soft reset device as child of clock device
> * using dedicated RK3588 lookup table
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3528.h b/arch/arm/include/asm/arch-rockchip/cru_rk3528.h
> new file mode 100644
> index 000000000000..b4020958a046
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3528.h
> @@ -0,0 +1,388 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
> + * Author: Joseph Chen <chenjh@rock-chips.com>
> + */
> +
> +#ifndef _ASM_ARCH_CRU_RK3528_H
> +#define _ASM_ARCH_CRU_RK3528_H
> +
> +#define MHz 1000000
> +#define KHz 1000
> +#define OSC_HZ (24 * MHz)
> +
> +#define CPU_PVTPLL_HZ (1200 * MHz)
> +#define APLL_HZ (600 * MHz)
> +#define GPLL_HZ (1188 * MHz)
> +#define CPLL_HZ (996 * MHz)
> +#define PPLL_HZ (1000 * MHz)
> +
> +/* RK3528 pll id */
> +enum rk3528_pll_id {
> + APLL,
> + CPLL,
> + GPLL,
> + PPLL,
> + DPLL,
> + PLL_COUNT,
> +};
> +
> +struct rk3528_clk_priv {
> + struct rk3528_cru *cru;
> + unsigned long ppll_hz;
> + unsigned long gpll_hz;
> + unsigned long cpll_hz;
> + unsigned long armclk_hz;
> + unsigned long armclk_enter_hz;
> + unsigned long armclk_init_hz;
> + bool sync_kernel;
> +};
> +
> +struct rk3528_pll {
> + unsigned int con0;
> + unsigned int con1;
> + unsigned int con2;
> + unsigned int con3;
> + unsigned int con4;
> + unsigned int reserved0[3];
> +};
> +
> +#define RK3528_CRU_BASE ((struct rk3528_cru *)0xff4a0000)
> +
> +struct rk3528_cru {
> + unsigned int apll_con[5];
> + unsigned int reserved0014[3];
> + unsigned int cpll_con[5];
> + unsigned int reserved0034[11];
> + unsigned int gpll_con[5];
> + unsigned int reserved0074[51 + 32];
> + unsigned int reserved01c0[48];
> + unsigned int mode_con[1];
> + unsigned int reserved0284[31];
> + unsigned int clksel_con[91];
> + unsigned int reserved046c[229];
> + unsigned int gate_con[46];
> + unsigned int reserved08b8[82];
> + unsigned int softrst_con[47];
> + unsigned int reserved0abc[81];
> + unsigned int glb_cnt_th;
> + unsigned int glb_rst_st;
> + unsigned int glb_srst_fst;
> + unsigned int glb_srst_snd;
> + unsigned int glb_rst_con;
> + unsigned int reserved0c14[6];
> + unsigned int corewfi_con;
> + unsigned int reserved0c30[15604];
> +
> + /* pmucru */
> + unsigned int reserved10000[192];
> + unsigned int pmuclksel_con[3];
> + unsigned int reserved1030c[317];
> + unsigned int pmugate_con[3];
> + unsigned int reserved1080c[125];
> + unsigned int pmusoftrst_con[3];
> + unsigned int reserved10a08[7550 + 8191];
> +
> + /* pciecru */
> + unsigned int reserved20000[32];
> + unsigned int ppll_con[5];
> + unsigned int reserved20094[155];
> + unsigned int pcieclksel_con[2];
> + unsigned int reserved20308[318];
> + unsigned int pciegate_con;
> +};
> +
> +check_member(rk3528_cru, pciegate_con, 0x20800);
> +
> +struct pll_rate_table {
> + unsigned long rate;
> + unsigned int fbdiv;
> + unsigned int postdiv1;
> + unsigned int refdiv;
> + unsigned int postdiv2;
> + unsigned int dsmpd;
> + unsigned int frac;
> +};
> +
> +#define RK3528_PMU_CRU_BASE 0x10000
> +#define RK3528_PCIE_CRU_BASE 0x20000
> +#define RK3528_DDRPHY_CRU_BASE 0x28000
> +#define RK3528_PLL_CON(x) ((x) * 0x4)
> +#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
> +#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
> +#define RK3528_MODE_CON 0x280
> +#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
> +#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
> +#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
> +#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
> +
> +#define RK3528_DIV_ACLK_M_CORE_SHIFT 11
> +#define RK3528_DIV_ACLK_M_CORE_MASK (0x1f << RK3528_DIV_ACLK_M_CORE_SHIFT)
> +#define RK3528_DIV_PCLK_DBG_SHIFT 1
> +#define RK3528_DIV_PCLK_DBG_MASK (0x1f << RK3528_DIV_PCLK_DBG_SHIFT)
> +
> +enum {
> + /* CRU_CLKSEL_CON00 */
> + CLK_MATRIX_50M_SRC_DIV_SHIFT = 2,
> + CLK_MATRIX_50M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_50M_SRC_DIV_SHIFT,
> + CLK_MATRIX_100M_SRC_DIV_SHIFT = 7,
> + CLK_MATRIX_100M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_100M_SRC_DIV_SHIFT,
> +
> + /* CRU_CLKSEL_CON01 */
> + CLK_MATRIX_150M_SRC_DIV_SHIFT = 0,
> + CLK_MATRIX_150M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_150M_SRC_DIV_SHIFT,
> + CLK_MATRIX_200M_SRC_DIV_SHIFT = 5,
> + CLK_MATRIX_200M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_200M_SRC_DIV_SHIFT,
> + CLK_MATRIX_250M_SRC_DIV_SHIFT = 10,
> + CLK_MATRIX_250M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_250M_SRC_DIV_SHIFT,
> + CLK_MATRIX_250M_SRC_SEL_SHIFT = 15,
> + CLK_MATRIX_250M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_250M_SRC_SEL_SHIFT,
> +
> + /* CRU_CLKSEL_CON02 */
> + CLK_MATRIX_300M_SRC_DIV_SHIFT = 0,
> + CLK_MATRIX_300M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_300M_SRC_DIV_SHIFT,
> + CLK_MATRIX_339M_SRC_DIV_SHIFT = 5,
> + CLK_MATRIX_339M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_339M_SRC_DIV_SHIFT,
> + CLK_MATRIX_400M_SRC_DIV_SHIFT = 10,
> + CLK_MATRIX_400M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_400M_SRC_DIV_SHIFT,
> +
> + /* CRU_CLKSEL_CON03 */
> + CLK_MATRIX_500M_SRC_DIV_SHIFT = 6,
> + CLK_MATRIX_500M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_500M_SRC_DIV_SHIFT,
> + CLK_MATRIX_500M_SRC_SEL_SHIFT = 11,
> + CLK_MATRIX_500M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_500M_SRC_SEL_SHIFT,
> +
> + /* CRU_CLKSEL_CON04 */
> + CLK_MATRIX_600M_SRC_DIV_SHIFT = 0,
> + CLK_MATRIX_600M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_600M_SRC_DIV_SHIFT,
> + CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX = 0U,
> + CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX = 1U,
> + CLK_MATRIX_500M_SRC_SEL_CLK_GPLL_MUX = 0U,
> + CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX = 1U,
> +
> + /* PMUCRU_CLKSEL_CON00 */
> + CLK_I2C2_SEL_SHIFT = 0,
> + CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT,
> +
> + /* PCIE_CRU_CLKSEL_CON01 */
> + PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT = 7,
> + PCIE_CLK_MATRIX_50M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT,
> + PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT = 11,
> + PCIE_CLK_MATRIX_100M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT,
> +
> + /* CRU_CLKSEL_CON32 */
> + DCLK_VOP_SRC0_SEL_SHIFT = 10,
> + DCLK_VOP_SRC0_SEL_MASK = 0x1 << DCLK_VOP_SRC0_SEL_SHIFT,
> + DCLK_VOP_SRC0_DIV_SHIFT = 2,
> + DCLK_VOP_SRC0_DIV_MASK = 0xFF << DCLK_VOP_SRC0_DIV_SHIFT,
> +
> + /* CRU_CLKSEL_CON33 */
> + DCLK_VOP_SRC1_SEL_SHIFT = 8,
> + DCLK_VOP_SRC1_SEL_MASK = 0x1 << DCLK_VOP_SRC1_SEL_SHIFT,
> + DCLK_VOP_SRC1_DIV_SHIFT = 0,
> + DCLK_VOP_SRC1_DIV_MASK = 0xFF << DCLK_VOP_SRC1_DIV_SHIFT,
> +
> + /* CRU_CLKSEL_CON43 */
> + CLK_CORE_CRYPTO_SEL_SHIFT = 14,
> + CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT,
> + ACLK_BUS_VOPGL_ROOT_DIV_SHIFT = 0U,
> + ACLK_BUS_VOPGL_ROOT_DIV_MASK = 0x7U << ACLK_BUS_VOPGL_ROOT_DIV_SHIFT,
> +
> + /* CRU_CLKSEL_CON44 */
> + CLK_PWM0_SEL_SHIFT = 6,
> + CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT,
> + CLK_PWM1_SEL_SHIFT = 8,
> + CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
> + CLK_PWM0_SEL_CLK_MATRIX_100M_SRC = 0U,
> + CLK_PWM0_SEL_CLK_MATRIX_50M_SRC = 1U,
> + CLK_PWM0_SEL_XIN_OSC0_FUNC = 2U,
> + CLK_PWM1_SEL_CLK_MATRIX_100M_SRC = 0U,
> + CLK_PWM1_SEL_CLK_MATRIX_50M_SRC = 1U,
> + CLK_PWM1_SEL_XIN_OSC0_FUNC = 2U,
> + CLK_PKA_CRYPTO_SEL_SHIFT = 0,
> + CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT,
> + CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U,
> + CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U,
> + CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U,
> + CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC = 3U,
> + CLK_PKA_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U,
> + CLK_PKA_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U,
> + CLK_PKA_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U,
> + CLK_PKA_CRYPTO_SEL_XIN_OSC0_FUNC = 3U,
> +
> + /* CRU_CLKSEL_CON60 */
> + CLK_MATRIX_25M_SRC_DIV_SHIFT = 2,
> + CLK_MATRIX_25M_SRC_DIV_MASK = 0xff << CLK_MATRIX_25M_SRC_DIV_SHIFT,
> + CLK_MATRIX_125M_SRC_DIV_SHIFT = 10,
> + CLK_MATRIX_125M_SRC_DIV_MASK = 0x1f << CLK_MATRIX_125M_SRC_DIV_SHIFT,
> +
> + /* CRU_CLKSEL_CON61 */
> + SCLK_SFC_DIV_SHIFT = 6,
> + SCLK_SFC_DIV_MASK = 0x3F << SCLK_SFC_DIV_SHIFT,
> + SCLK_SFC_SEL_SHIFT = 12,
> + SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT,
> + SCLK_SFC_SEL_CLK_GPLL_MUX = 0U,
> + SCLK_SFC_SEL_CLK_CPLL_MUX = 1U,
> + SCLK_SFC_SEL_XIN_OSC0_FUNC = 2U,
> +
> + /* CRU_CLKSEL_CON62 */
> + CCLK_SRC_EMMC_DIV_SHIFT = 0,
> + CCLK_SRC_EMMC_DIV_MASK = 0x3F << CCLK_SRC_EMMC_DIV_SHIFT,
> + CCLK_SRC_EMMC_SEL_SHIFT = 6,
> + CCLK_SRC_EMMC_SEL_MASK = 0x3 << CCLK_SRC_EMMC_SEL_SHIFT,
> + BCLK_EMMC_SEL_SHIFT = 8,
> + BCLK_EMMC_SEL_MASK = 0x3 << BCLK_EMMC_SEL_SHIFT,
> +
> + /* CRU_CLKSEL_CON63 */
> + CLK_I2C3_SEL_SHIFT = 12,
> + CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT,
> + CLK_I2C5_SEL_SHIFT = 14,
> + CLK_I2C5_SEL_MASK = 0x3 << CLK_I2C5_SEL_SHIFT,
> + CLK_SPI1_SEL_SHIFT = 10,
> + CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT,
> +
> + /* CRU_CLKSEL_CON64 */
> + CLK_I2C6_SEL_SHIFT = 0,
> + CLK_I2C6_SEL_MASK = 0x3 << CLK_I2C6_SEL_SHIFT,
> +
> + /* CRU_CLKSEL_CON74 */
> + CLK_SARADC_DIV_SHIFT = 0,
> + CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT,
> + CLK_TSADC_DIV_SHIFT = 3,
> + CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT,
> + CLK_TSADC_TSEN_DIV_SHIFT = 8,
> + CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT,
> +
> + /* CRU_CLKSEL_CON79 */
> + CLK_I2C1_SEL_SHIFT = 9,
> + CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT,
> + CLK_I2C0_SEL_SHIFT = 11,
> + CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT,
> + CLK_SPI0_SEL_SHIFT = 13,
> + CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT,
> +
> + /* CRU_CLKSEL_CON83 */
> + ACLK_VOP_ROOT_DIV_SHIFT = 12,
> + ACLK_VOP_ROOT_DIV_MASK = 0x7 << ACLK_VOP_ROOT_DIV_SHIFT,
> + ACLK_VOP_ROOT_SEL_SHIFT = 15,
> + ACLK_VOP_ROOT_SEL_MASK = 0x1 << ACLK_VOP_ROOT_SEL_SHIFT,
> +
> + /* CRU_CLKSEL_CON84 */
> + DCLK_VOP0_SEL_SHIFT = 0,
> + DCLK_VOP0_SEL_MASK = 0x1 << DCLK_VOP0_SEL_SHIFT,
> + DCLK_VOP_SRC_SEL_CLK_GPLL_MUX = 0U,
> + DCLK_VOP_SRC_SEL_CLK_CPLL_MUX = 1U,
> + ACLK_VOP_ROOT_SEL_CLK_GPLL_MUX = 0U,
> + ACLK_VOP_ROOT_SEL_CLK_CPLL_MUX = 1U,
> + DCLK_VOP0_SEL_DCLK_VOP_SRC0 = 0U,
> + DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL_IO = 1U,
> +
> + /* CRU_CLKSEL_CON85 */
> + CLK_I2C4_SEL_SHIFT = 13,
> + CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT,
> + CLK_I2C7_SEL_SHIFT = 0,
> + CLK_I2C7_SEL_MASK = 0x3 << CLK_I2C7_SEL_SHIFT,
> + CLK_I2C3_SEL_CLK_MATRIX_200M_SRC = 0U,
> + CLK_I2C3_SEL_CLK_MATRIX_100M_SRC = 1U,
> + CLK_I2C3_SEL_CLK_MATRIX_50M_SRC = 2U,
> + CLK_I2C3_SEL_XIN_OSC0_FUNC = 3U,
> + CLK_SPI1_SEL_CLK_MATRIX_200M_SRC = 0U,
> + CLK_SPI1_SEL_CLK_MATRIX_100M_SRC = 1U,
> + CLK_SPI1_SEL_CLK_MATRIX_50M_SRC = 2U,
> + CLK_SPI1_SEL_XIN_OSC0_FUNC = 3U,
> + CCLK_SRC_SDMMC0_DIV_SHIFT = 0,
> + CCLK_SRC_SDMMC0_DIV_MASK = 0x3F << CCLK_SRC_SDMMC0_DIV_SHIFT,
> + CCLK_SRC_SDMMC0_SEL_SHIFT = 6,
> + CCLK_SRC_SDMMC0_SEL_MASK = 0x3 << CCLK_SRC_SDMMC0_SEL_SHIFT,
> + CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX = 0U,
> + CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX = 1U,
> + CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC = 2U,
> + BCLK_EMMC_SEL_CLK_MATRIX_200M_SRC = 0U,
> + BCLK_EMMC_SEL_CLK_MATRIX_100M_SRC = 1U,
> + BCLK_EMMC_SEL_CLK_MATRIX_50M_SRC = 2U,
> + BCLK_EMMC_SEL_XIN_OSC0_FUNC = 3U,
> + CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX = 0U,
> + CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX = 1U,
> + CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC = 2U,
> +
> + /* CRU_CLKSEL_CON04 */
> + CLK_UART0_SRC_DIV_SHIFT = 5,
> + CLK_UART0_SRC_DIV_MASK = 0x1F << CLK_UART0_SRC_DIV_SHIFT,
> + /* CRU_CLKSEL_CON05 */
> + CLK_UART0_FRAC_DIV_SHIFT = 0,
> + CLK_UART0_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART0_FRAC_DIV_SHIFT,
> + /* CRU_CLKSEL_CON06 */
> + SCLK_UART0_SRC_SEL_SHIFT = 0,
> + SCLK_UART0_SRC_SEL_MASK = 0x3 << SCLK_UART0_SRC_SEL_SHIFT,
> + CLK_UART1_SRC_DIV_SHIFT = 2,
> + CLK_UART1_SRC_DIV_MASK = 0x1F << CLK_UART1_SRC_DIV_SHIFT,
> + /* CRU_CLKSEL_CON07 */
> + CLK_UART1_FRAC_DIV_SHIFT = 0,
> + CLK_UART1_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART1_FRAC_DIV_SHIFT,
> + /* CRU_CLKSEL_CON08 */
> + SCLK_UART1_SRC_SEL_SHIFT = 0,
> + SCLK_UART1_SRC_SEL_MASK = 0x3 << SCLK_UART1_SRC_SEL_SHIFT,
> + CLK_UART2_SRC_DIV_SHIFT = 2,
> + CLK_UART2_SRC_DIV_MASK = 0x1F << CLK_UART2_SRC_DIV_SHIFT,
> + /* CRU_CLKSEL_CON09 */
> + CLK_UART2_FRAC_DIV_SHIFT = 0,
> + CLK_UART2_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART2_FRAC_DIV_SHIFT,
> + /* CRU_CLKSEL_CON10 */
> + SCLK_UART2_SRC_SEL_SHIFT = 0,
> + SCLK_UART2_SRC_SEL_MASK = 0x3 << SCLK_UART2_SRC_SEL_SHIFT,
> + CLK_UART3_SRC_DIV_SHIFT = 2,
> + CLK_UART3_SRC_DIV_MASK = 0x1F << CLK_UART3_SRC_DIV_SHIFT,
> + /* CRU_CLKSEL_CON11 */
> + CLK_UART3_FRAC_DIV_SHIFT = 0,
> + CLK_UART3_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART3_FRAC_DIV_SHIFT,
> + /* CRU_CLKSEL_CON12 */
> + SCLK_UART3_SRC_SEL_SHIFT = 0,
> + SCLK_UART3_SRC_SEL_MASK = 0x3 << SCLK_UART3_SRC_SEL_SHIFT,
> + CLK_UART4_SRC_DIV_SHIFT = 2,
> + CLK_UART4_SRC_DIV_MASK = 0x1F << CLK_UART4_SRC_DIV_SHIFT,
> + /* CRU_CLKSEL_CON13 */
> + CLK_UART4_FRAC_DIV_SHIFT = 0,
> + CLK_UART4_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART4_FRAC_DIV_SHIFT,
> + /* CRU_CLKSEL_CON14 */
> + SCLK_UART4_SRC_SEL_SHIFT = 0,
> + SCLK_UART4_SRC_SEL_MASK = 0x3 << SCLK_UART4_SRC_SEL_SHIFT,
> + CLK_UART5_SRC_DIV_SHIFT = 2,
> + CLK_UART5_SRC_DIV_MASK = 0x1F << CLK_UART5_SRC_DIV_SHIFT,
> + /* CRU_CLKSEL_CON15 */
> + CLK_UART5_FRAC_DIV_SHIFT = 0,
> + CLK_UART5_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART5_FRAC_DIV_SHIFT,
> + /* CRU_CLKSEL_CON16 */
> + SCLK_UART5_SRC_SEL_SHIFT = 0,
> + SCLK_UART5_SRC_SEL_MASK = 0x3 << SCLK_UART5_SRC_SEL_SHIFT,
> + CLK_UART6_SRC_DIV_SHIFT = 2,
> + CLK_UART6_SRC_DIV_MASK = 0x1F << CLK_UART6_SRC_DIV_SHIFT,
> + /* CRU_CLKSEL_CON17 */
> + CLK_UART6_FRAC_DIV_SHIFT = 0,
> + CLK_UART6_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART6_FRAC_DIV_SHIFT,
> + /* CRU_CLKSEL_CON18 */
> + SCLK_UART6_SRC_SEL_SHIFT = 0,
> + SCLK_UART6_SRC_SEL_MASK = 0x3 << SCLK_UART6_SRC_SEL_SHIFT,
> + CLK_UART7_SRC_DIV_SHIFT = 2,
> + CLK_UART7_SRC_DIV_MASK = 0x1F << CLK_UART7_SRC_DIV_SHIFT,
> + /* CRU_CLKSEL_CON19 */
> + CLK_UART7_FRAC_DIV_SHIFT = 0,
> + CLK_UART7_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART7_FRAC_DIV_SHIFT,
> + /* CRU_CLKSEL_CON20 */
> + SCLK_UART7_SRC_SEL_SHIFT = 0,
> + SCLK_UART7_SRC_SEL_MASK = 0x3 << SCLK_UART7_SRC_SEL_SHIFT,
> + SCLK_UART0_SRC_SEL_CLK_UART0_SRC = 0U,
> + SCLK_UART0_SRC_SEL_CLK_UART0_FRAC = 1U,
> + SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC = 2U,
> +
> + /* CRU_CLKSEL_CON60 */
> + CLK_GMAC1_VPU_25M_DIV_SHIFT = 2,
> + CLK_GMAC1_VPU_25M_DIV_MASK = 0xFF << CLK_GMAC1_VPU_25M_DIV_SHIFT,
> + /* CRU_CLKSEL_CON66 */
> + CLK_GMAC1_SRC_VPU_DIV_SHIFT = 0,
> + CLK_GMAC1_SRC_VPU_DIV_MASK = 0x3F << CLK_GMAC1_SRC_VPU_DIV_SHIFT,
> + /* CRU_CLKSEL_CON84 */
> + CLK_GMAC0_SRC_DIV_SHIFT = 3,
> + CLK_GMAC0_SRC_DIV_MASK = 0x3F << CLK_GMAC0_SRC_DIV_SHIFT,
> +};
> +
> +#endif /* _ASM_ARCH_CRU_RK3528_H */
> diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
> index 9e379cc2e3b6..70be03164e8f 100644
> --- a/drivers/clk/rockchip/Makefile
> +++ b/drivers/clk/rockchip/Makefile
> @@ -15,6 +15,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o
> obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
> obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
> +obj-$(CONFIG_ROCKCHIP_RK3528) += clk_rk3528.o
> obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
> obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o
> obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o
> diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c
> index 44c6f14618d2..9dec40b1fe83 100644
> --- a/drivers/clk/rockchip/clk_pll.c
> +++ b/drivers/clk/rockchip/clk_pll.c
> @@ -309,9 +309,11 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
> * When power on or changing PLL setting,
> * we must force PLL into slow mode to ensure output stable clock.
> */
> - rk_clrsetreg(base + pll->mode_offset,
> - pll->mode_mask << pll->mode_shift,
> - RKCLK_PLL_MODE_SLOW << pll->mode_shift);
> + if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
> + rk_clrsetreg(base + pll->mode_offset,
> + pll->mode_mask << pll->mode_shift,
> + RKCLK_PLL_MODE_SLOW << pll->mode_shift);
> + }
>
> /* Power down */
> rk_setreg(base + pll->con_offset + 0x4,
> @@ -345,8 +347,11 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
> while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift)))
> udelay(1);
>
> - rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
> - RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
> + if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
> + rk_clrsetreg(base + pll->mode_offset,
> + pll->mode_mask << pll->mode_shift,
> + RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
> + }
> debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",
> pll, readl(base + pll->con_offset),
> readl(base + pll->con_offset + 0x4),
> @@ -362,12 +367,18 @@ static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll,
> u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac;
> u32 con = 0, shift, mask;
> ulong rate;
> + int mode;
>
> con = readl(base + pll->mode_offset);
> shift = pll->mode_shift;
> mask = pll->mode_mask << shift;
>
> - switch ((con & mask) >> shift) {
> + if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE))
> + mode = (con & mask) >> shift;
> + else
> + mode = RKCLK_PLL_MODE_NORMAL;
> +
> + switch (mode) {
> case RKCLK_PLL_MODE_SLOW:
> return OSC_HZ;
> case RKCLK_PLL_MODE_NORMAL:
> diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c
> new file mode 100644
> index 000000000000..06f20895accf
> --- /dev/null
> +++ b/drivers/clk/rockchip/clk_rk3528.c
> @@ -0,0 +1,1754 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
> + * Author: Joseph Chen <chenjh@rock-chips.com>
> + */
> +
> +#include <bitfield.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <syscon.h>
> +#include <asm/arch-rockchip/clock.h>
> +#include <asm/arch-rockchip/cru_rk3528.h>
> +#include <asm/arch-rockchip/hardware.h>
> +#include <dm/device-internal.h>
> +#include <dm/lists.h>
> +#include <dt-bindings/clock/rockchip,rk3528-cru.h>
> +#include <linux/delay.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
> +
> +/*
> + * PLL attention.
> + *
> + * [FRAC PLL]: GPLL, PPLL, DPLL
> + * - frac mode: refdiv can be 1 or 2 only
> + * - int mode: refdiv has no special limit
> + * - VCO range: [950, 3800] MHZ
> + *
> + * [INT PLL]: CPLL, APLL
> + * - int mode: refdiv can be 1 or 2 only
> + * - VCO range: [475, 1900] MHZ
> + *
> + * [PPLL]: normal mode only.
> + *
> + */
> +static struct rockchip_pll_rate_table rk3528_pll_rates[] = {
> + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
> + RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
> + RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
> + RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
> + RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
> + RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
> + RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
> + RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
> + RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
> + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */
> + RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0),
> + RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0),
> + RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */
> + RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */
> + RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0),
> + RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
> + RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
> + RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
> + RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
> + RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
> + RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
> + RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
> + RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0),
> + { /* sentinel */ },
> +};
> +
> +static struct rockchip_pll_clock rk3528_pll_clks[] = {
> + [APLL] = PLL(pll_rk3328, PLL_APLL, RK3528_PLL_CON(0),
> + RK3528_MODE_CON, 0, 10, 0, rk3528_pll_rates),
> +
> + [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3528_PLL_CON(8),
> + RK3528_MODE_CON, 2, 10, 0, rk3528_pll_rates),
> +
> + [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3528_PLL_CON(24),
> + RK3528_MODE_CON, 4, 10, 0, rk3528_pll_rates),
> +
> + [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3528_PCIE_PLL_CON(32),
> + RK3528_MODE_CON, 6, 10, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates),
> +
> + [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3528_DDRPHY_PLL_CON(16),
> + RK3528_DDRPHY_MODE_CON, 0, 10, 0, rk3528_pll_rates),
> +};
> +
> +#define RK3528_CPUCLK_RATE(_rate, _aclk_m_core, _pclk_dbg) \
> +{ \
> + .rate = _rate##U, \
> + .aclk_div = (_aclk_m_core), \
> + .pclk_div = (_pclk_dbg), \
> +}
> +
> +/* sign-off: _aclk_m_core: 550M, _pclk_dbg: 137.5M, */
> +static struct rockchip_cpu_rate_table rk3528_cpu_rates[] = {
> + RK3528_CPUCLK_RATE(1896000000, 1, 13),
> + RK3528_CPUCLK_RATE(1800000000, 1, 12),
> + RK3528_CPUCLK_RATE(1704000000, 1, 11),
> + RK3528_CPUCLK_RATE(1608000000, 1, 11),
> + RK3528_CPUCLK_RATE(1512000000, 1, 11),
> + RK3528_CPUCLK_RATE(1416000000, 1, 9),
> + RK3528_CPUCLK_RATE(1296000000, 1, 8),
> + RK3528_CPUCLK_RATE(1200000000, 1, 8),
> + RK3528_CPUCLK_RATE(1188000000, 1, 8),
> + RK3528_CPUCLK_RATE(1092000000, 1, 7),
> + RK3528_CPUCLK_RATE(1008000000, 1, 6),
> + RK3528_CPUCLK_RATE(1000000000, 1, 6),
> + RK3528_CPUCLK_RATE(996000000, 1, 6),
> + RK3528_CPUCLK_RATE(960000000, 1, 6),
> + RK3528_CPUCLK_RATE(912000000, 1, 6),
> + RK3528_CPUCLK_RATE(816000000, 1, 5),
> + RK3528_CPUCLK_RATE(600000000, 1, 3),
> + RK3528_CPUCLK_RATE(594000000, 1, 3),
> + RK3528_CPUCLK_RATE(408000000, 1, 2),
> + RK3528_CPUCLK_RATE(312000000, 1, 2),
> + RK3528_CPUCLK_RATE(216000000, 1, 1),
> + RK3528_CPUCLK_RATE(96000000, 1, 0),
> +};
> +
> +/*
> + *
> + * rational_best_approximation(31415, 10000,
> + * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
> + *
> + * you may look at given_numerator as a fixed point number,
> + * with the fractional part size described in given_denominator.
> + *
> + * for theoretical background, see:
> + * http://en.wikipedia.org/wiki/Continued_fraction
> + */
> +static void rational_best_approximation(unsigned long given_numerator,
> + unsigned long given_denominator,
> + unsigned long max_numerator,
> + unsigned long max_denominator,
> + unsigned long *best_numerator,
> + unsigned long *best_denominator)
> +{
> + unsigned long n, d, n0, d0, n1, d1;
> +
> + n = given_numerator;
> + d = given_denominator;
> + n0 = 0;
> + d1 = 0;
> + n1 = 1;
> + d0 = 1;
> + for (;;) {
> + unsigned long t, a;
> +
> + if (n1 > max_numerator || d1 > max_denominator) {
> + n1 = n0;
> + d1 = d0;
> + break;
> + }
> + if (d == 0)
> + break;
> + t = d;
> + a = n / d;
> + d = n % d;
> + n = t;
> + t = n0 + a * n1;
> + n0 = n1;
> + n1 = t;
> + t = d0 + a * d1;
> + d0 = d1;
> + d1 = t;
> + }
> + *best_numerator = n1;
> + *best_denominator = d1;
> +}
> +
> +static int rk3528_armclk_set_clk(struct rk3528_clk_priv *priv, ulong new_rate)
> +{
> + const struct rockchip_cpu_rate_table *rate;
> + struct rk3528_cru *cru = priv->cru;
> + ulong old_rate;
> +
> + rate = rockchip_get_cpu_settings(rk3528_cpu_rates, new_rate);
> + if (!rate) {
> + printf("%s unsupported rate\n", __func__);
> + return -EINVAL;
> + }
> +
> + /*
> + * set up dependent divisors for DBG and ACLK clocks.
> + */
> + old_rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, APLL);
> + if (old_rate > new_rate) {
> + if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL],
> + priv->cru, APLL, new_rate))
> + return -EINVAL;
> +
> + rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
> + rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT);
> +
> + rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
> + rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT);
> + } else if (old_rate < new_rate) {
> + rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
> + rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT);
> +
> + rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
> + rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT);
> +
> + if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL],
> + priv->cru, APLL, new_rate))
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static ulong rk3528_ppll_matrix_get_rate(struct rk3528_clk_priv *priv,
> + ulong clk_id)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 div, mask, shift;
> + void *reg;
> +
> + switch (clk_id) {
> + case CLK_PPLL_50M_MATRIX:
> + case CLK_GMAC1_RMII_VPU:
> + mask = PCIE_CLK_MATRIX_50M_SRC_DIV_MASK;
> + shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT;
> + reg = &cru->pcieclksel_con[1];
> + break;
> +
> + case CLK_PPLL_100M_MATRIX:
> + mask = PCIE_CLK_MATRIX_100M_SRC_DIV_MASK;
> + shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT;
> + reg = &cru->pcieclksel_con[1];
> + break;
> +
> + case CLK_PPLL_125M_MATRIX:
> + case CLK_GMAC1_SRC_VPU:
> + mask = CLK_MATRIX_125M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_125M_SRC_DIV_SHIFT;
> + reg = &cru->clksel_con[60];
> + break;
> +
> + case CLK_GMAC1_VPU_25M:
> + mask = CLK_MATRIX_25M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_25M_SRC_DIV_SHIFT;
> + reg = &cru->clksel_con[60];
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + div = (readl(reg) & mask) >> shift;
> +
> + return DIV_TO_RATE(priv->ppll_hz, div);
> +}
> +
> +static ulong rk3528_ppll_matrix_set_rate(struct rk3528_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 id, div, mask, shift;
> + u8 is_pciecru = 0;
> +
> + switch (clk_id) {
> + case CLK_PPLL_50M_MATRIX:
> + id = 1;
> + mask = PCIE_CLK_MATRIX_50M_SRC_DIV_MASK;
> + shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT;
> + is_pciecru = 1;
> + break;
> +
> + case CLK_PPLL_100M_MATRIX:
> + id = 1;
> + mask = PCIE_CLK_MATRIX_100M_SRC_DIV_MASK;
> + shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT;
> + is_pciecru = 1;
> + break;
> +
> + case CLK_PPLL_125M_MATRIX:
> + id = 60;
> + mask = CLK_MATRIX_125M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_125M_SRC_DIV_SHIFT;
> + break;
> + case CLK_GMAC1_VPU_25M:
> + id = 60;
> + mask = CLK_MATRIX_25M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_25M_SRC_DIV_SHIFT;
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + div = DIV_ROUND_UP(priv->ppll_hz, rate);
> + if (is_pciecru)
> + rk_clrsetreg(&cru->pcieclksel_con[id], mask, (div - 1) << shift);
> + else
> + rk_clrsetreg(&cru->clksel_con[id], mask, (div - 1) << shift);
> +
> + return rk3528_ppll_matrix_get_rate(priv, clk_id);
> +}
> +
> +static ulong rk3528_cgpll_matrix_get_rate(struct rk3528_clk_priv *priv,
> + ulong clk_id)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 sel, div, mask, shift, con;
> + u32 sel_mask = 0, sel_shift;
> + u8 is_gpll_parent = 1;
> + u8 is_halfdiv = 0;
> + ulong prate;
> +
> + switch (clk_id) {
> + case CLK_MATRIX_50M_SRC:
> + con = 0;
> + mask = CLK_MATRIX_50M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_50M_SRC_DIV_SHIFT;
> + is_gpll_parent = 0;
> + break;
> +
> + case CLK_MATRIX_100M_SRC:
> + con = 0;
> + mask = CLK_MATRIX_100M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_100M_SRC_DIV_SHIFT;
> + is_gpll_parent = 0;
> + break;
> +
> + case CLK_MATRIX_150M_SRC:
> + con = 1;
> + mask = CLK_MATRIX_150M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_150M_SRC_DIV_SHIFT;
> + break;
> +
> + case CLK_MATRIX_200M_SRC:
> + con = 1;
> + mask = CLK_MATRIX_200M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_200M_SRC_DIV_SHIFT;
> + break;
> +
> + case CLK_MATRIX_250M_SRC:
> + con = 1;
> + mask = CLK_MATRIX_250M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_250M_SRC_DIV_SHIFT;
> + sel_mask = CLK_MATRIX_250M_SRC_SEL_MASK;
> + sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT;
> + break;
> +
> + case CLK_MATRIX_300M_SRC:
> + con = 2;
> + mask = CLK_MATRIX_300M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_300M_SRC_DIV_SHIFT;
> + break;
> +
> + case CLK_MATRIX_339M_SRC:
> + con = 2;
> + mask = CLK_MATRIX_339M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_339M_SRC_DIV_SHIFT;
> + is_halfdiv = 1;
> + break;
> +
> + case CLK_MATRIX_400M_SRC:
> + con = 2;
> + mask = CLK_MATRIX_400M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_400M_SRC_DIV_SHIFT;
> + break;
> +
> + case CLK_MATRIX_500M_SRC:
> + con = 3;
> + mask = CLK_MATRIX_500M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_500M_SRC_DIV_SHIFT;
> + sel_mask = CLK_MATRIX_500M_SRC_SEL_MASK;
> + sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT;
> + break;
> +
> + case CLK_MATRIX_600M_SRC:
> + con = 4;
> + mask = CLK_MATRIX_600M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_600M_SRC_DIV_SHIFT;
> + break;
> +
> + case ACLK_BUS_VOPGL_ROOT:
> + case ACLK_BUS_VOPGL_BIU:
> + con = 43;
> + mask = ACLK_BUS_VOPGL_ROOT_DIV_MASK;
> + shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT;
> + break;
> +
> + default:
> + return -ENOENT;
> + }
> +
> + if (sel_mask) {
> + sel = (readl(&cru->clksel_con[con]) & sel_mask) >> sel_shift;
> + if (sel == CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX) // TODO
> + prate = priv->gpll_hz;
> + else
> + prate = priv->cpll_hz;
> + } else {
> + if (is_gpll_parent)
> + prate = priv->gpll_hz;
> + else
> + prate = priv->cpll_hz;
> + }
> +
> + div = (readl(&cru->clksel_con[con]) & mask) >> shift;
> +
> + /* NOTE: '-1' to balance the DIV_TO_RATE() 'div+1' */
> + return is_halfdiv ? DIV_TO_RATE(prate * 2, (3 + 2 * div) - 1) : DIV_TO_RATE(prate, div);
> +}
> +
> +static ulong rk3528_cgpll_matrix_set_rate(struct rk3528_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 sel, div, mask, shift, con;
> + u32 sel_mask = 0, sel_shift;
> + u8 is_gpll_parent = 1;
> + u8 is_halfdiv = 0;
> + ulong prate = 0;
> +
> + switch (clk_id) {
> + case CLK_MATRIX_50M_SRC:
> + con = 0;
> + mask = CLK_MATRIX_50M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_50M_SRC_DIV_SHIFT;
> + is_gpll_parent = 0;
> + break;
> +
> + case CLK_MATRIX_100M_SRC:
> + con = 0;
> + mask = CLK_MATRIX_100M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_100M_SRC_DIV_SHIFT;
> + is_gpll_parent = 0;
> + break;
> +
> + case CLK_MATRIX_150M_SRC:
> + con = 1;
> + mask = CLK_MATRIX_150M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_150M_SRC_DIV_SHIFT;
> + break;
> +
> + case CLK_MATRIX_200M_SRC:
> + con = 1;
> + mask = CLK_MATRIX_200M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_200M_SRC_DIV_SHIFT;
> + break;
> +
> + case CLK_MATRIX_250M_SRC:
> + con = 1;
> + mask = CLK_MATRIX_250M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_250M_SRC_DIV_SHIFT;
> + sel_mask = CLK_MATRIX_250M_SRC_SEL_MASK;
> + sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT;
> + break;
> +
> + case CLK_MATRIX_300M_SRC:
> + con = 2;
> + mask = CLK_MATRIX_300M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_300M_SRC_DIV_SHIFT;
> + break;
> +
> + case CLK_MATRIX_339M_SRC:
> + con = 2;
> + mask = CLK_MATRIX_339M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_339M_SRC_DIV_SHIFT;
> + is_halfdiv = 1;
> + break;
> +
> + case CLK_MATRIX_400M_SRC:
> + con = 2;
> + mask = CLK_MATRIX_400M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_400M_SRC_DIV_SHIFT;
> + break;
> +
> + case CLK_MATRIX_500M_SRC:
> + con = 3;
> + mask = CLK_MATRIX_500M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_500M_SRC_DIV_SHIFT;
> + sel_mask = CLK_MATRIX_500M_SRC_SEL_MASK;
> + sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT;
> + break;
> +
> + case CLK_MATRIX_600M_SRC:
> + con = 4;
> + mask = CLK_MATRIX_600M_SRC_DIV_MASK;
> + shift = CLK_MATRIX_600M_SRC_DIV_SHIFT;
> + break;
> +
> + case ACLK_BUS_VOPGL_ROOT:
> + case ACLK_BUS_VOPGL_BIU:
> + con = 43;
> + mask = ACLK_BUS_VOPGL_ROOT_DIV_MASK;
> + shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT;
> + break;
> +
> + default:
> + return -ENOENT;
> + }
> +
> + if (sel_mask) {
> + if (priv->gpll_hz % rate == 0) {
> + sel = CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX; // TODO
> + prate = priv->gpll_hz;
> + } else {
> + sel = CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX;
> + prate = priv->cpll_hz;
> + }
> + } else {
> + if (is_gpll_parent)
> + prate = priv->gpll_hz;
> + else
> + prate = priv->cpll_hz;
> + }
> +
> + if (is_halfdiv)
> + /* NOTE: '+1' to balance the following rk_clrsetreg() 'div-1' */
> + div = DIV_ROUND_UP((prate * 2) - (3 * rate), 2 * rate) + 1;
> + else
> + div = DIV_ROUND_UP(prate, rate);
> +
> + rk_clrsetreg(&cru->clksel_con[con], mask, (div - 1) << shift);
> + if (sel_mask)
> + rk_clrsetreg(&cru->clksel_con[con], sel_mask, sel << sel_shift);
> +
> + return rk3528_cgpll_matrix_get_rate(priv, clk_id);
> +}
> +
> +static ulong rk3528_i2c_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 id, sel, con, mask, shift;
> + u8 is_pmucru = 0;
> + ulong rate;
> +
> + switch (clk_id) {
> + case CLK_I2C0:
> + id = 79;
> + mask = CLK_I2C0_SEL_MASK;
> + shift = CLK_I2C0_SEL_SHIFT;
> + break;
> +
> + case CLK_I2C1:
> + id = 79;
> + mask = CLK_I2C1_SEL_MASK;
> + shift = CLK_I2C1_SEL_SHIFT;
> + break;
> +
> + case CLK_I2C2:
> + id = 0;
> + mask = CLK_I2C2_SEL_MASK;
> + shift = CLK_I2C2_SEL_SHIFT;
> + is_pmucru = 1;
> + break;
> +
> + case CLK_I2C3:
> + id = 63;
> + mask = CLK_I2C3_SEL_MASK;
> + shift = CLK_I2C3_SEL_SHIFT;
> + break;
> +
> + case CLK_I2C4:
> + id = 85;
> + mask = CLK_I2C4_SEL_MASK;
> + shift = CLK_I2C4_SEL_SHIFT;
> + break;
> +
> + case CLK_I2C5:
> + id = 63;
> + mask = CLK_I2C5_SEL_MASK;
> + shift = CLK_I2C5_SEL_SHIFT;
> + break;
> +
> + case CLK_I2C6:
> + id = 64;
> + mask = CLK_I2C6_SEL_MASK;
> + shift = CLK_I2C6_SEL_SHIFT;
> + break;
> +
> + case CLK_I2C7:
> + id = 86;
> + mask = CLK_I2C7_SEL_MASK;
> + shift = CLK_I2C7_SEL_SHIFT;
> + break;
> +
> + default:
> + return -ENOENT;
> + }
> +
> + if (is_pmucru)
> + con = readl(&cru->pmuclksel_con[id]);
> + else
> + con = readl(&cru->clksel_con[id]);
> + sel = (con & mask) >> shift;
> + if (sel == CLK_I2C3_SEL_CLK_MATRIX_200M_SRC)
> + rate = 200 * MHz;
> + else if (sel == CLK_I2C3_SEL_CLK_MATRIX_100M_SRC)
> + rate = 100 * MHz;
> + else if (sel == CLK_I2C3_SEL_CLK_MATRIX_50M_SRC)
> + rate = 50 * MHz;
> + else
> + rate = OSC_HZ;
> +
> + return rate;
> +}
> +
> +static ulong rk3528_i2c_set_clk(struct rk3528_clk_priv *priv, ulong clk_id,
> + ulong rate)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 id, sel, mask, shift;
> + u8 is_pmucru = 0;
> +
> + if (rate >= 198 * MHz)
> + sel = CLK_I2C3_SEL_CLK_MATRIX_200M_SRC;
> + else if (rate >= 99 * MHz)
> + sel = CLK_I2C3_SEL_CLK_MATRIX_100M_SRC;
> + else if (rate >= 50 * MHz)
> + sel = CLK_I2C3_SEL_CLK_MATRIX_50M_SRC;
> + else
> + sel = CLK_I2C3_SEL_XIN_OSC0_FUNC;
> +
> + switch (clk_id) {
> + case CLK_I2C0:
> + id = 79;
> + mask = CLK_I2C0_SEL_MASK;
> + shift = CLK_I2C0_SEL_SHIFT;
> + break;
> +
> + case CLK_I2C1:
> + id = 79;
> + mask = CLK_I2C1_SEL_MASK;
> + shift = CLK_I2C1_SEL_SHIFT;
> + break;
> +
> + case CLK_I2C2:
> + id = 0;
> + mask = CLK_I2C2_SEL_MASK;
> + shift = CLK_I2C2_SEL_SHIFT;
> + is_pmucru = 1;
> + break;
> +
> + case CLK_I2C3:
> + id = 63;
> + mask = CLK_I2C3_SEL_MASK;
> + shift = CLK_I2C3_SEL_SHIFT;
> + break;
> +
> + case CLK_I2C4:
> + id = 85;
> + mask = CLK_I2C4_SEL_MASK;
> + shift = CLK_I2C4_SEL_SHIFT;
> + break;
> +
> + case CLK_I2C5:
> + id = 63;
> + mask = CLK_I2C5_SEL_MASK;
> + shift = CLK_I2C5_SEL_SHIFT;
> + break;
> +
> + case CLK_I2C6:
> + id = 64;
> + mask = CLK_I2C6_SEL_MASK;
> + shift = CLK_I2C6_SEL_SHIFT;
> + break;
> +
> + case CLK_I2C7:
> + id = 86;
> + mask = CLK_I2C7_SEL_MASK;
> + shift = CLK_I2C7_SEL_SHIFT;
> + break;
> +
> + default:
> + return -ENOENT;
> + }
> +
> + if (is_pmucru)
> + rk_clrsetreg(&cru->pmuclksel_con[id], mask, sel << shift);
> + else
> + rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
> +
> + return rk3528_i2c_get_clk(priv, clk_id);
> +}
> +
> +static ulong rk3528_spi_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 id, sel, con, mask, shift;
> + ulong rate;
> +
> + switch (clk_id) {
> + case CLK_SPI0:
> + id = 79;
> + mask = CLK_SPI0_SEL_MASK;
> + shift = CLK_SPI0_SEL_SHIFT;
> + break;
> +
> + case CLK_SPI1:
> + id = 63;
> + mask = CLK_SPI1_SEL_MASK;
> + shift = CLK_SPI1_SEL_SHIFT;
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + con = readl(&cru->clksel_con[id]);
> + sel = (con & mask) >> shift;
> + if (sel == CLK_SPI1_SEL_CLK_MATRIX_200M_SRC)
> + rate = 200 * MHz;
> + else if (sel == CLK_SPI1_SEL_CLK_MATRIX_100M_SRC)
> + rate = 100 * MHz;
> + else if (sel == CLK_SPI1_SEL_CLK_MATRIX_50M_SRC)
> + rate = 50 * MHz;
> + else
> + rate = OSC_HZ;
> +
> + return rate;
> +}
> +
> +static ulong rk3528_spi_set_clk(struct rk3528_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 id, sel, mask, shift;
> +
> + if (rate >= 198 * MHz)
> + sel = CLK_SPI1_SEL_CLK_MATRIX_200M_SRC;
> + else if (rate >= 99 * MHz)
> + sel = CLK_SPI1_SEL_CLK_MATRIX_100M_SRC;
> + else if (rate >= 50 * MHz)
> + sel = CLK_SPI1_SEL_CLK_MATRIX_50M_SRC;
> + else
> + sel = CLK_SPI1_SEL_XIN_OSC0_FUNC;
> +
> + switch (clk_id) {
> + case CLK_SPI0:
> + id = 79;
> + mask = CLK_SPI0_SEL_MASK;
> + shift = CLK_SPI0_SEL_SHIFT;
> + break;
> +
> + case CLK_SPI1:
> + id = 63;
> + mask = CLK_SPI1_SEL_MASK;
> + shift = CLK_SPI1_SEL_SHIFT;
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
> +
> + return rk3528_spi_get_clk(priv, clk_id);
> +}
> +
> +static ulong rk3528_pwm_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 id, sel, con, mask, shift;
> + ulong rate;
> +
> + switch (clk_id) {
> + case CLK_PWM0:
> + id = 44;
> + mask = CLK_PWM0_SEL_MASK;
> + shift = CLK_PWM0_SEL_SHIFT;
> + break;
> +
> + case CLK_PWM1:
> + id = 44;
> + mask = CLK_PWM1_SEL_MASK;
> + shift = CLK_PWM1_SEL_SHIFT;
> + break;
> +
> + default:
> + return -ENOENT;
> + }
> +
> + con = readl(&cru->clksel_con[id]);
> + sel = (con & mask) >> shift;
> + if (sel == CLK_PWM0_SEL_CLK_MATRIX_100M_SRC)
> + rate = 100 * MHz;
> + if (sel == CLK_PWM0_SEL_CLK_MATRIX_50M_SRC)
> + rate = 50 * MHz;
> + else
> + rate = OSC_HZ;
> +
> + return rate;
> +}
> +
> +static ulong rk3528_pwm_set_clk(struct rk3528_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 id, sel, mask, shift;
> +
> + if (rate >= 99 * MHz)
> + sel = CLK_PWM0_SEL_CLK_MATRIX_100M_SRC;
> + else if (rate >= 50 * MHz)
> + sel = CLK_PWM0_SEL_CLK_MATRIX_50M_SRC;
> + else
> + sel = CLK_PWM0_SEL_XIN_OSC0_FUNC;
> +
> + switch (clk_id) {
> + case CLK_PWM0:
> + id = 44;
> + mask = CLK_PWM0_SEL_MASK;
> + shift = CLK_PWM0_SEL_SHIFT;
> + break;
> +
> + case CLK_PWM1:
> + id = 44;
> + mask = CLK_PWM1_SEL_MASK;
> + shift = CLK_PWM1_SEL_SHIFT;
> + break;
> +
> + default:
> + return -ENOENT;
> + }
> +
> + rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
> +
> + return rk3528_pwm_get_clk(priv, clk_id);
> +}
> +
> +static ulong rk3528_adc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 div, con;
> +
> + con = readl(&cru->clksel_con[74]);
> + switch (clk_id) {
> + case CLK_SARADC:
> + div = (con & CLK_SARADC_DIV_MASK) >>
> + CLK_SARADC_DIV_SHIFT;
> + break;
> +
> + case CLK_TSADC_TSEN:
> + div = (con & CLK_TSADC_TSEN_DIV_MASK) >>
> + CLK_TSADC_TSEN_DIV_SHIFT;
> + break;
> +
> + case CLK_TSADC:
> + div = (con & CLK_TSADC_DIV_MASK) >>
> + CLK_TSADC_DIV_SHIFT;
> + break;
> +
> + default:
> + return -ENOENT;
> + }
> +
> + return DIV_TO_RATE(OSC_HZ, div);
> +}
> +
> +static ulong rk3528_adc_set_clk(struct rk3528_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 div, mask, shift;
> +
> + switch (clk_id) {
> + case CLK_SARADC:
> + mask = CLK_SARADC_DIV_MASK;
> + shift = CLK_SARADC_DIV_SHIFT;
> + break;
> +
> + case CLK_TSADC_TSEN:
> + mask = CLK_TSADC_TSEN_DIV_MASK;
> + shift = CLK_TSADC_TSEN_DIV_SHIFT;
> + break;
> +
> + case CLK_TSADC:
> + mask = CLK_TSADC_DIV_MASK;
> + shift = CLK_TSADC_DIV_SHIFT;
> + break;
> +
> + default:
> + return -ENOENT;
> + }
> +
> + div = DIV_ROUND_UP(OSC_HZ, rate);
> + rk_clrsetreg(&cru->clksel_con[74], mask, (div - 1) << shift);
> +
> + return rk3528_adc_get_clk(priv, clk_id);
> +}
> +
> +static ulong rk3528_sdmmc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 div, sel, con;
> + ulong prate;
> +
> + con = readl(&cru->clksel_con[85]);
> + div = (con & CCLK_SRC_SDMMC0_DIV_MASK) >>
> + CCLK_SRC_SDMMC0_DIV_SHIFT;
> + sel = (con & CCLK_SRC_SDMMC0_SEL_MASK) >>
> + CCLK_SRC_SDMMC0_SEL_SHIFT;
> +
> + if (sel == CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX)
> + prate = priv->gpll_hz;
> + else if (sel == CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX)
> + prate = priv->cpll_hz;
> + else
> + prate = OSC_HZ;
> +
> + return DIV_TO_RATE(prate, div);
> +}
> +
> +static ulong rk3528_sdmmc_set_clk(struct rk3528_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 div, sel;
> +
> + if (OSC_HZ % rate == 0) {
> + div = DIV_ROUND_UP(OSC_HZ, rate);
> + sel = CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC;
> + } else if ((priv->cpll_hz % rate) == 0) {
> + div = DIV_ROUND_UP(priv->cpll_hz, rate);
> + sel = CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX;
> + } else {
> + div = DIV_ROUND_UP(priv->gpll_hz, rate);
> + sel = CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX;
> + }
> +
> + assert(div - 1 <= 63);
> + rk_clrsetreg(&cru->clksel_con[85],
> + CCLK_SRC_SDMMC0_SEL_MASK |
> + CCLK_SRC_SDMMC0_DIV_MASK,
> + sel << CCLK_SRC_SDMMC0_SEL_SHIFT |
> + (div - 1) << CCLK_SRC_SDMMC0_DIV_SHIFT);
> +
> + return rk3528_sdmmc_get_clk(priv, clk_id);
> +}
> +
> +static ulong rk3528_sfc_get_clk(struct rk3528_clk_priv *priv)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 div, sel, con, parent;
> +
> + con = readl(&cru->clksel_con[61]);
> + div = (con & SCLK_SFC_DIV_MASK) >>
> + SCLK_SFC_DIV_SHIFT;
> + sel = (con & SCLK_SFC_SEL_MASK) >>
> + SCLK_SFC_SEL_SHIFT;
> + if (sel == SCLK_SFC_SEL_CLK_GPLL_MUX)
> + parent = priv->gpll_hz;
> + else if (sel == SCLK_SFC_SEL_CLK_CPLL_MUX)
> + parent = priv->cpll_hz;
> + else
> + parent = OSC_HZ;
> +
> + return DIV_TO_RATE(parent, div);
> +}
> +
> +static ulong rk3528_sfc_set_clk(struct rk3528_clk_priv *priv, ulong rate)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + int div, sel;
> +
> + if (OSC_HZ % rate == 0) {
> + div = DIV_ROUND_UP(OSC_HZ, rate);
> + sel = SCLK_SFC_SEL_XIN_OSC0_FUNC;
> + } else if ((priv->cpll_hz % rate) == 0) {
> + div = DIV_ROUND_UP(priv->cpll_hz, rate);
> + sel = SCLK_SFC_SEL_CLK_CPLL_MUX;
> + } else {
> + div = DIV_ROUND_UP(priv->gpll_hz, rate);
> + sel = SCLK_SFC_SEL_CLK_GPLL_MUX;
> + }
> +
> + assert(div - 1 <= 63);
> + rk_clrsetreg(&cru->clksel_con[61],
> + SCLK_SFC_SEL_MASK |
> + SCLK_SFC_DIV_MASK,
> + sel << SCLK_SFC_SEL_SHIFT |
> + (div - 1) << SCLK_SFC_DIV_SHIFT);
> +
> + return rk3528_sfc_get_clk(priv);
> +}
> +
> +static ulong rk3528_emmc_get_clk(struct rk3528_clk_priv *priv)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 div, sel, con, parent;
> +
> + con = readl(&cru->clksel_con[62]);
> + div = (con & CCLK_SRC_EMMC_DIV_MASK) >>
> + CCLK_SRC_EMMC_DIV_SHIFT;
> + sel = (con & CCLK_SRC_EMMC_SEL_MASK) >>
> + CCLK_SRC_EMMC_SEL_SHIFT;
> +
> + if (sel == CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX)
> + parent = priv->gpll_hz;
> + else if (sel == CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX)
> + parent = priv->cpll_hz;
> + else
> + parent = OSC_HZ;
> +
> + return DIV_TO_RATE(parent, div);
> +}
> +
> +static ulong rk3528_emmc_set_clk(struct rk3528_clk_priv *priv, ulong rate)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 div, sel;
> +
> + if (OSC_HZ % rate == 0) {
> + div = DIV_ROUND_UP(OSC_HZ, rate);
> + sel = CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC;
> + } else if ((priv->cpll_hz % rate) == 0) {
> + div = DIV_ROUND_UP(priv->cpll_hz, rate);
> + sel = CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX;
> + } else {
> + div = DIV_ROUND_UP(priv->gpll_hz, rate);
> + sel = CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX;
> + }
> +
> + assert(div - 1 <= 63);
> + rk_clrsetreg(&cru->clksel_con[62],
> + CCLK_SRC_EMMC_SEL_MASK |
> + CCLK_SRC_EMMC_DIV_MASK,
> + sel << CCLK_SRC_EMMC_SEL_SHIFT |
> + (div - 1) << CCLK_SRC_EMMC_DIV_SHIFT);
> +
> + return rk3528_emmc_get_clk(priv);
> +}
> +
> +static ulong rk3528_dclk_vop_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 div_mask, div_shift;
> + u32 sel_mask, sel_shift;
> + u32 id, con, sel, div;
> + ulong prate;
> +
> + switch (clk_id) {
> + case DCLK_VOP0:
> + id = 32;
> + sel_mask = DCLK_VOP_SRC0_SEL_MASK;
> + sel_shift = DCLK_VOP_SRC0_SEL_SHIFT;
> + /* FIXME if need src: clk_hdmiphy_pixel_io */
> + div_mask = DCLK_VOP_SRC0_DIV_MASK;
> + div_shift = DCLK_VOP_SRC0_DIV_SHIFT;
> + break;
> +
> + case DCLK_VOP1:
> + id = 33;
> + sel_mask = DCLK_VOP_SRC1_SEL_MASK;
> + sel_shift = DCLK_VOP_SRC1_SEL_SHIFT;
> + div_mask = DCLK_VOP_SRC1_DIV_MASK;
> + div_shift = DCLK_VOP_SRC1_DIV_SHIFT;
> + break;
> +
> + default:
> + return -ENOENT;
> + }
> +
> + con = readl(&cru->clksel_con[id]);
> + div = (con & div_mask) >> div_shift;
> + sel = (con & sel_mask) >> sel_shift;
> + if (sel == DCLK_VOP_SRC_SEL_CLK_GPLL_MUX)
> + prate = priv->gpll_hz;
> + else
> + prate = priv->cpll_hz;
> +
> + return DIV_TO_RATE(prate, div);
> +}
> +
> +static ulong rk3528_dclk_vop_set_clk(struct rk3528_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 div_mask, div_shift;
> + u32 sel_mask, sel_shift;
> + u32 id, sel, div;
> + ulong prate;
> +
> + switch (clk_id) {
> + case DCLK_VOP0:
> + id = 32;
> + sel_mask = DCLK_VOP_SRC0_SEL_MASK;
> + sel_shift = DCLK_VOP_SRC0_SEL_SHIFT;
> + /* FIXME if need src: clk_hdmiphy_pixel_io */
> + div_mask = DCLK_VOP_SRC0_DIV_MASK;
> + div_shift = DCLK_VOP_SRC0_DIV_SHIFT;
> + break;
> +
> + case DCLK_VOP1:
> + id = 33;
> + sel_mask = DCLK_VOP_SRC1_SEL_MASK;
> + sel_shift = DCLK_VOP_SRC1_SEL_SHIFT;
> + div_mask = DCLK_VOP_SRC1_DIV_MASK;
> + div_shift = DCLK_VOP_SRC1_DIV_SHIFT;
> + break;
> +
> + default:
> + return -ENOENT;
> + }
> +
> + if ((priv->gpll_hz % rate) == 0) {
> + prate = priv->gpll_hz;
> + sel = (DCLK_VOP_SRC_SEL_CLK_GPLL_MUX << sel_shift) & sel_mask;
> + } else {
> + prate = priv->cpll_hz;
> + sel = (DCLK_VOP_SRC_SEL_CLK_CPLL_MUX << sel_shift) & sel_mask;
> + }
> +
> + div = ((DIV_ROUND_UP(prate, rate) - 1) << div_shift) & div_mask;
> + rk_clrsetreg(&cru->clksel_con[id], sel, div);
> +
> + return rk3528_dclk_vop_get_clk(priv, clk_id);
> +}
> +
> +static ulong rk3528_uart_get_rate(struct rk3528_clk_priv *priv, ulong clk_id)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 sel_shift, sel_mask, div_shift, div_mask;
> + u32 sel, id, con, frac_div, div;
> + ulong m, n, rate;
> +
> + switch (clk_id) {
> + case SCLK_UART0:
> + id = 6;
> + sel_shift = SCLK_UART0_SRC_SEL_SHIFT;
> + sel_mask = SCLK_UART0_SRC_SEL_MASK;
> + div_shift = CLK_UART0_SRC_DIV_SHIFT;
> + div_mask = CLK_UART0_SRC_DIV_MASK;
> + break;
> +
> + case SCLK_UART1:
> + id = 8;
> + sel_shift = SCLK_UART1_SRC_SEL_SHIFT;
> + sel_mask = SCLK_UART1_SRC_SEL_MASK;
> + div_shift = CLK_UART1_SRC_DIV_SHIFT;
> + div_mask = CLK_UART1_SRC_DIV_MASK;
> + break;
> +
> + case SCLK_UART2:
> + id = 10;
> + sel_shift = SCLK_UART2_SRC_SEL_SHIFT;
> + sel_mask = SCLK_UART2_SRC_SEL_MASK;
> + div_shift = CLK_UART2_SRC_DIV_SHIFT;
> + div_mask = CLK_UART2_SRC_DIV_MASK;
> + break;
> +
> + case SCLK_UART3:
> + id = 12;
> + sel_shift = SCLK_UART3_SRC_SEL_SHIFT;
> + sel_mask = SCLK_UART3_SRC_SEL_MASK;
> + div_shift = CLK_UART3_SRC_DIV_SHIFT;
> + div_mask = CLK_UART3_SRC_DIV_MASK;
> + break;
> +
> + case SCLK_UART4:
> + id = 14;
> + sel_shift = SCLK_UART4_SRC_SEL_SHIFT;
> + sel_mask = SCLK_UART4_SRC_SEL_MASK;
> + div_shift = CLK_UART4_SRC_DIV_SHIFT;
> + div_mask = CLK_UART4_SRC_DIV_MASK;
> + break;
> +
> + case SCLK_UART5:
> + id = 16;
> + sel_shift = SCLK_UART5_SRC_SEL_SHIFT;
> + sel_mask = SCLK_UART5_SRC_SEL_MASK;
> + div_shift = CLK_UART5_SRC_DIV_SHIFT;
> + div_mask = CLK_UART5_SRC_DIV_MASK;
> + break;
> +
> + case SCLK_UART6:
> + id = 18;
> + sel_shift = SCLK_UART6_SRC_SEL_SHIFT;
> + sel_mask = SCLK_UART6_SRC_SEL_MASK;
> + div_shift = CLK_UART6_SRC_DIV_SHIFT;
> + div_mask = CLK_UART6_SRC_DIV_MASK;
> + break;
> +
> + case SCLK_UART7:
> + id = 20;
> + sel_shift = SCLK_UART7_SRC_SEL_SHIFT;
> + sel_mask = SCLK_UART7_SRC_SEL_MASK;
> + div_shift = CLK_UART7_SRC_DIV_SHIFT;
> + div_mask = CLK_UART7_SRC_DIV_MASK;
> + break;
> +
> + default:
> + return -ENOENT;
> + }
> +
> + con = readl(&cru->clksel_con[id - 2]);
> + div = (con & div_mask) >> div_shift;
> +
> + con = readl(&cru->clksel_con[id]);
> + sel = (con & sel_mask) >> sel_shift;
> +
> + if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_SRC) {
> + rate = DIV_TO_RATE(priv->gpll_hz, div);
> + } else if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_FRAC) {
> + frac_div = readl(&cru->clksel_con[id - 1]);
> + n = (frac_div & 0xffff0000) >> 16;
> + m = frac_div & 0x0000ffff;
> + rate = DIV_TO_RATE(priv->gpll_hz, div) * n / m;
> + } else {
> + rate = OSC_HZ;
> + }
> +
> + return rate;
> +}
> +
> +static ulong rk3528_uart_set_rate(struct rk3528_clk_priv *priv,
> + ulong clk_id, ulong rate)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 sel_shift, sel_mask, div_shift, div_mask;
> + u32 sel, id, div;
> + ulong m = 0, n = 0, val;
> +
> + if (rate == OSC_HZ) {
> + sel = SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC;
> + div = DIV_ROUND_UP(OSC_HZ, rate);
> + } else if (priv->gpll_hz % rate == 0) {
> + sel = SCLK_UART0_SRC_SEL_CLK_UART0_SRC;
> + div = DIV_ROUND_UP(priv->gpll_hz, rate);
> + } else {
> + sel = SCLK_UART0_SRC_SEL_CLK_UART0_FRAC;
> + div = 2;
> + rational_best_approximation(rate, priv->gpll_hz / div,
> + GENMASK(16 - 1, 0),
> + GENMASK(16 - 1, 0),
> + &n, &m);
> + }
> +
> + switch (clk_id) {
> + case SCLK_UART0:
> + id = 6;
> + sel_shift = SCLK_UART0_SRC_SEL_SHIFT;
> + sel_mask = SCLK_UART0_SRC_SEL_MASK;
> + div_shift = CLK_UART0_SRC_DIV_SHIFT;
> + div_mask = CLK_UART0_SRC_DIV_MASK;
> + break;
> +
> + case SCLK_UART1:
> + id = 8;
> + sel_shift = SCLK_UART1_SRC_SEL_SHIFT;
> + sel_mask = SCLK_UART1_SRC_SEL_MASK;
> + div_shift = CLK_UART1_SRC_DIV_SHIFT;
> + div_mask = CLK_UART1_SRC_DIV_MASK;
> + break;
> +
> + case SCLK_UART2:
> + id = 10;
> + sel_shift = SCLK_UART2_SRC_SEL_SHIFT;
> + sel_mask = SCLK_UART2_SRC_SEL_MASK;
> + div_shift = CLK_UART2_SRC_DIV_SHIFT;
> + div_mask = CLK_UART2_SRC_DIV_MASK;
> + break;
> +
> + case SCLK_UART3:
> + id = 12;
> + sel_shift = SCLK_UART3_SRC_SEL_SHIFT;
> + sel_mask = SCLK_UART3_SRC_SEL_MASK;
> + div_shift = CLK_UART3_SRC_DIV_SHIFT;
> + div_mask = CLK_UART3_SRC_DIV_MASK;
> + break;
> +
> + case SCLK_UART4:
> + id = 14;
> + sel_shift = SCLK_UART4_SRC_SEL_SHIFT;
> + sel_mask = SCLK_UART4_SRC_SEL_MASK;
> + div_shift = CLK_UART4_SRC_DIV_SHIFT;
> + div_mask = CLK_UART4_SRC_DIV_MASK;
> + break;
> +
> + case SCLK_UART5:
> + id = 16;
> + sel_shift = SCLK_UART5_SRC_SEL_SHIFT;
> + sel_mask = SCLK_UART5_SRC_SEL_MASK;
> + div_shift = CLK_UART5_SRC_DIV_SHIFT;
> + div_mask = CLK_UART5_SRC_DIV_MASK;
> + break;
> +
> + case SCLK_UART6:
> + id = 18;
> + sel_shift = SCLK_UART6_SRC_SEL_SHIFT;
> + sel_mask = SCLK_UART6_SRC_SEL_MASK;
> + div_shift = CLK_UART6_SRC_DIV_SHIFT;
> + div_mask = CLK_UART6_SRC_DIV_MASK;
> + break;
> +
> + case SCLK_UART7:
> + id = 20;
> + sel_shift = SCLK_UART7_SRC_SEL_SHIFT;
> + sel_mask = SCLK_UART7_SRC_SEL_MASK;
> + div_shift = CLK_UART7_SRC_DIV_SHIFT;
> + div_mask = CLK_UART7_SRC_DIV_MASK;
> + break;
> +
> + default:
> + return -ENOENT;
> + }
> +
> + rk_clrsetreg(&cru->clksel_con[id - 2], div_mask, (div - 1) << div_shift);
> + rk_clrsetreg(&cru->clksel_con[id], sel_mask, sel << sel_shift);
> + if (m && n) {
> + val = n << 16 | m;
> + writel(val, &cru->clksel_con[id - 1]);
> + }
> +
> + return rk3528_uart_get_rate(priv, clk_id);
> +}
> +
> +static ulong rk3528_clk_get_rate(struct clk *clk)
> +{
> + struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
> + ulong rate = 0;
> +
> + if (!priv->gpll_hz || !priv->cpll_hz) {
> + printf("%s: gpll=%lu, cpll=%ld\n",
> + __func__, priv->gpll_hz, priv->cpll_hz);
> + return -ENOENT;
> + }
> +
> + switch (clk->id) {
> + case PLL_APLL:
> + case ARMCLK:
> + rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru,
> + APLL);
> + break;
> + case PLL_CPLL:
> + rate = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], priv->cru,
> + CPLL);
> + break;
> + case PLL_GPLL:
> + rate = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], priv->cru,
> + GPLL);
> + break;
> +
> + case PLL_PPLL:
> + rate = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], priv->cru,
> + PPLL);
> + break;
> + case PLL_DPLL:
> + rate = rockchip_pll_get_rate(&rk3528_pll_clks[DPLL], priv->cru,
> + DPLL);
> + break;
> +
> + case TCLK_EMMC:
> + case TCLK_WDT_NS:
> + rate = OSC_HZ;
> + break;
> + case CLK_I2C0:
> + case CLK_I2C1:
> + case CLK_I2C2:
> + case CLK_I2C3:
> + case CLK_I2C4:
> + case CLK_I2C5:
> + case CLK_I2C6:
> + case CLK_I2C7:
> + rate = rk3528_i2c_get_clk(priv, clk->id);
> + break;
> + case CLK_SPI0:
> + case CLK_SPI1:
> + rate = rk3528_spi_get_clk(priv, clk->id);
> + break;
> + case CLK_PWM0:
> + case CLK_PWM1:
> + rate = rk3528_pwm_get_clk(priv, clk->id);
> + break;
> + case CLK_SARADC:
> + case CLK_TSADC:
> + case CLK_TSADC_TSEN:
> + rate = rk3528_adc_get_clk(priv, clk->id);
> + break;
> + case CCLK_SRC_EMMC:
> + rate = rk3528_emmc_get_clk(priv);
> + break;
> + case HCLK_SDMMC0:
> + case CCLK_SRC_SDMMC0:
> + rate = rk3528_sdmmc_get_clk(priv, clk->id);
> + break;
> + case SCLK_SFC:
> + rate = rk3528_sfc_get_clk(priv);
> + break;
> + case DCLK_VOP0:
> + case DCLK_VOP1:
> + rate = rk3528_dclk_vop_get_clk(priv, clk->id);
> + break;
> + case DCLK_CVBS:
> + rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1) / 4;
> + break;
> + case DCLK_4X_CVBS:
> + rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1);
> + break;
> + case SCLK_UART0:
> + case SCLK_UART1:
> + case SCLK_UART2:
> + case SCLK_UART3:
> + case SCLK_UART4:
> + case SCLK_UART5:
> + case SCLK_UART6:
> + case SCLK_UART7:
> + rate = rk3528_uart_get_rate(priv, clk->id);
> + break;
> + case CLK_MATRIX_50M_SRC:
> + case CLK_MATRIX_100M_SRC:
> + case CLK_MATRIX_150M_SRC:
> + case CLK_MATRIX_200M_SRC:
> + case CLK_MATRIX_250M_SRC:
> + case CLK_MATRIX_300M_SRC:
> + case CLK_MATRIX_339M_SRC:
> + case CLK_MATRIX_400M_SRC:
> + case CLK_MATRIX_500M_SRC:
> + case CLK_MATRIX_600M_SRC:
> + case ACLK_BUS_VOPGL_BIU:
> + rate = rk3528_cgpll_matrix_get_rate(priv, clk->id);
> + break;
> + case CLK_PPLL_50M_MATRIX:
> + case CLK_PPLL_100M_MATRIX:
> + case CLK_PPLL_125M_MATRIX:
> + case CLK_GMAC1_VPU_25M:
> + case CLK_GMAC1_RMII_VPU:
> + case CLK_GMAC1_SRC_VPU:
> + rate = rk3528_ppll_matrix_get_rate(priv, clk->id);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return rate;
> +};
> +
> +static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
> +{
> + struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
> + ulong ret = 0;
> +
> + if (!priv->gpll_hz) {
> + printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
> + return -ENOENT;
> + }
> +
> + switch (clk->id) {
> + case PLL_APLL:
> + case ARMCLK:
> + if (priv->armclk_hz)
> + rk3528_armclk_set_clk(priv, rate);
> + priv->armclk_hz = rate;
> + break;
> + case PLL_CPLL:
> + ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru,
> + CPLL, rate);
> + priv->cpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL],
> + priv->cru, CPLL);
> + break;
> + case PLL_GPLL:
> + ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru,
> + GPLL, rate);
> + priv->gpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL],
> + priv->cru, GPLL);
> + break;
> + case PLL_PPLL:
> + ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru,
> + PPLL, rate);
> + priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL],
> + priv->cru, PPLL);
> + break;
> + case TCLK_EMMC:
> + case TCLK_WDT_NS:
> + return (rate == OSC_HZ) ? 0 : -EINVAL;
> + case CLK_I2C0:
> + case CLK_I2C1:
> + case CLK_I2C2:
> + case CLK_I2C3:
> + case CLK_I2C4:
> + case CLK_I2C5:
> + case CLK_I2C6:
> + case CLK_I2C7:
> + ret = rk3528_i2c_set_clk(priv, clk->id, rate);
> + break;
> + case CLK_SPI0:
> + case CLK_SPI1:
> + ret = rk3528_spi_set_clk(priv, clk->id, rate);
> + break;
> + case CLK_PWM0:
> + case CLK_PWM1:
> + ret = rk3528_pwm_set_clk(priv, clk->id, rate);
> + break;
> + case CLK_SARADC:
> + case CLK_TSADC:
> + case CLK_TSADC_TSEN:
> + ret = rk3528_adc_set_clk(priv, clk->id, rate);
> + break;
> + case HCLK_SDMMC0:
> + case CCLK_SRC_SDMMC0:
> + ret = rk3528_sdmmc_set_clk(priv, clk->id, rate);
> + break;
> + case SCLK_SFC:
> + ret = rk3528_sfc_set_clk(priv, rate);
> + break;
> + case CCLK_SRC_EMMC:
> + ret = rk3528_emmc_set_clk(priv, rate);
> + break;
> + case DCLK_VOP0:
> + case DCLK_VOP1:
> + ret = rk3528_dclk_vop_set_clk(priv, clk->id, rate);
> + break;
> + case SCLK_UART0:
> + case SCLK_UART1:
> + case SCLK_UART2:
> + case SCLK_UART3:
> + case SCLK_UART4:
> + case SCLK_UART5:
> + case SCLK_UART6:
> + case SCLK_UART7:
> + ret = rk3528_uart_set_rate(priv, clk->id, rate);
> + break;
> + case CLK_MATRIX_50M_SRC:
> + case CLK_MATRIX_100M_SRC:
> + case CLK_MATRIX_150M_SRC:
> + case CLK_MATRIX_200M_SRC:
> + case CLK_MATRIX_250M_SRC:
> + case CLK_MATRIX_300M_SRC:
> + case CLK_MATRIX_339M_SRC:
> + case CLK_MATRIX_400M_SRC:
> + case CLK_MATRIX_500M_SRC:
> + case CLK_MATRIX_600M_SRC:
> + case ACLK_BUS_VOPGL_BIU:
> + ret = rk3528_cgpll_matrix_set_rate(priv, clk->id, rate);
> + break;
> + case CLK_PPLL_50M_MATRIX:
> + case CLK_PPLL_100M_MATRIX:
> + case CLK_PPLL_125M_MATRIX:
> + case CLK_GMAC1_VPU_25M:
> + ret = rk3528_ppll_matrix_set_rate(priv, clk->id, rate);
> + break;
> + case CLK_GMAC1_RMII_VPU:
> + case CLK_GMAC1_SRC_VPU:
> + /* dummy set */
> + ret = rk3528_ppll_matrix_get_rate(priv, clk->id);
> + break;
> +
> + /* Might occur in cru assigned-clocks, can be ignored here */
> + case ACLK_BUS_VOPGL_ROOT:
> + case BCLK_EMMC:
> + case XIN_OSC0_DIV:
> + ret = 0;
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return ret;
> +};
> +
> +static struct clk_ops rk3528_clk_ops = {
> + .get_rate = rk3528_clk_get_rate,
> + .set_rate = rk3528_clk_set_rate,
> +};
> +
> +#ifdef CONFIG_XPL_BUILD
> +
> +#define COREGRF_BASE 0xff300000
> +#define PVTPLL_CON0_L 0x0
> +#define PVTPLL_CON0_H 0x4
> +
> +static int rk3528_cpu_pvtpll_set_rate(struct rk3528_clk_priv *priv, ulong rate)
> +{
> + struct rk3528_cru *cru = priv->cru;
> + u32 length;
> +
> + if (rate >= 1200000000)
> + length = 8;
> + else if (rate >= 1008000000)
> + length = 11;
> + else
> + length = 17;
> +
> + /* set pclk dbg div to 9 */
> + rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
> + 9 << RK3528_DIV_PCLK_DBG_SHIFT);
> + /* set aclk_m_core div to 1 */
> + rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
> + 1 << RK3528_DIV_ACLK_M_CORE_SHIFT);
> +
> + /* set ring sel = 1 */
> + writel(0x07000000 | (1 << 8), COREGRF_BASE + PVTPLL_CON0_L);
> + /* set length */
> + writel(0x007f0000 | length, COREGRF_BASE + PVTPLL_CON0_H);
> + /* enable pvtpll */
> + writel(0x00020002, COREGRF_BASE + PVTPLL_CON0_L);
> + /* start monitor */
> + writel(0x00010001, COREGRF_BASE + PVTPLL_CON0_L);
> +
> + /* set core mux pvtpll */
> + writel(0x00010001, &cru->clksel_con[40]);
> + writel(0x00100010, &cru->clksel_con[39]);
> +
> + /* set pclk dbg div to 8 */
> + rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
> + 8 << RK3528_DIV_PCLK_DBG_SHIFT);
> +
> + return 0;
> +}
> +#endif
> +
> +static int rk3528_clk_init(struct rk3528_clk_priv *priv)
> +{
> + int ret;
> +
> + priv->sync_kernel = false;
> +
> +#ifdef CONFIG_XPL_BUILD
> + /*
> + * BOOTROM:
> + * CPU 1902/2(postdiv1)=546M
> + * CPLL 996/2(postdiv1)=498M
> + * GPLL 1188/2(postdiv1)=594M
> + * |-- clk_matrix_200m_src_div=1 => rate: 300M
> + * |-- clk_matrix_300m_src_div=2 => rate: 200M
> + *
> + * Avoid overclocking when change GPLL rate:
> + * Change clk_matrix_200m_src_div to 5.
> + * Change clk_matrix_300m_src_div to 3.
> + */
> + writel(0x01200120, &priv->cru->clksel_con[1]);
> + writel(0x00030003, &priv->cru->clksel_con[2]);
> +
> + if (!priv->armclk_enter_hz) {
> + priv->armclk_enter_hz =
> + rockchip_pll_get_rate(&rk3528_pll_clks[APLL],
> + priv->cru, APLL);
> + priv->armclk_init_hz = priv->armclk_enter_hz;
> + }
> +
> + if (priv->armclk_init_hz != APLL_HZ) {
> + ret = rk3528_armclk_set_clk(priv, APLL_HZ);
> + if (!ret)
> + priv->armclk_init_hz = APLL_HZ;
> + }
> +
> + if (!rk3528_cpu_pvtpll_set_rate(priv, CPU_PVTPLL_HZ)) {
> + debug("cpu pvtpll %d KHz\n", CPU_PVTPLL_HZ / 1000);
> + priv->armclk_init_hz = CPU_PVTPLL_HZ;
> + }
> +#endif
> +
> + if (priv->cpll_hz != CPLL_HZ) {
> + ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru,
> + CPLL, CPLL_HZ);
> + if (!ret)
> + priv->cpll_hz = CPLL_HZ;
> + }
> +
> + if (priv->gpll_hz != GPLL_HZ) {
> + ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru,
> + GPLL, GPLL_HZ);
> + if (!ret)
> + priv->gpll_hz = GPLL_HZ;
> + }
> +
> + if (priv->ppll_hz != PPLL_HZ) {
> + ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru,
> + PPLL, PPLL_HZ);
> + if (!ret)
> + priv->ppll_hz = PPLL_HZ;
> + }
> +
> +#ifdef CONFIG_XPL_BUILD
> + /* Init to override bootrom config */
> + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_50M_SRC, 50000000);
> + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_100M_SRC, 100000000);
> + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_150M_SRC, 150000000);
> + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_200M_SRC, 200000000);
> + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_250M_SRC, 250000000);
> + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_300M_SRC, 300000000);
> + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_339M_SRC, 340000000);
> + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_400M_SRC, 400000000);
> + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_500M_SRC, 500000000);
> + rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_600M_SRC, 600000000);
> + rk3528_cgpll_matrix_set_rate(priv, ACLK_BUS_VOPGL_BIU, 500000000);
> +
> + /* The default rate is 100Mhz, it's not friendly for remote IR module */
> + rk3528_pwm_set_clk(priv, CLK_PWM0, 24000000);
> + rk3528_pwm_set_clk(priv, CLK_PWM1, 24000000);
> +#endif
> + return 0;
> +}
> +
> +static int rk3528_clk_probe(struct udevice *dev)
> +{
> + struct rk3528_clk_priv *priv = dev_get_priv(dev);
> + int ret;
> +
> + ret = rk3528_clk_init(priv);
> + if (ret)
> + return ret;
> +
> + /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
> + ret = clk_set_defaults(dev, 1);
> + if (ret)
> + debug("%s clk_set_defaults failed %d\n", __func__, ret);
> + else
> + priv->sync_kernel = true;
> +
> + return 0;
> +}
> +
> +static int rk3528_clk_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct rk3528_clk_priv *priv = dev_get_priv(dev);
> +
> + priv->cru = dev_read_addr_ptr(dev);
> +
> + return 0;
> +}
> +
> +static int rk3528_clk_bind(struct udevice *dev)
> +{
> + struct udevice *sys_child;
> + struct sysreset_reg *priv;
> + int ret;
> +
> + /* The reset driver does not have a device node, so bind it here */
> + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
> + &sys_child);
> + if (ret) {
> + debug("Warning: No sysreset driver: ret=%d\n", ret);
> + } else {
> + priv = malloc(sizeof(struct sysreset_reg));
> + priv->glb_srst_fst_value = offsetof(struct rk3528_cru,
> + glb_srst_fst);
> + priv->glb_srst_snd_value = offsetof(struct rk3528_cru,
> + glb_srst_snd);
> + dev_set_priv(sys_child, priv);
> + }
> +
> +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
> + ret = offsetof(struct rk3528_cru, softrst_con[0]);
> + ret = rk3528_reset_bind_lut(dev, ret, 47);
> + if (ret)
> + debug("Warning: software reset driver bind failed\n");
> +#endif
> +
> + return 0;
> +}
> +
> +static const struct udevice_id rk3528_clk_ids[] = {
> + { .compatible = "rockchip,rk3528-cru" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk3528_cru) = {
> + .name = "rockchip_rk3528_cru",
> + .id = UCLASS_CLK,
> + .of_match = rk3528_clk_ids,
> + .priv_auto = sizeof(struct rk3528_clk_priv),
> + .of_to_plat = rk3528_clk_ofdata_to_platdata,
> + .ops = &rk3528_clk_ops,
> + .bind = rk3528_clk_bind,
> + .probe = rk3528_clk_probe,
> +};
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index b94943960138..53e7d3730653 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -17,7 +17,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
> obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
> obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
> obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
> -obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3588.o
> +obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3528.o rst-rk3588.o
> obj-$(CONFIG_RESET_MESON) += reset-meson.o
> obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
> obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
> diff --git a/drivers/reset/rst-rk3528.c b/drivers/reset/rst-rk3528.c
> new file mode 100644
> index 000000000000..f6e760d468d9
> --- /dev/null
> +++ b/drivers/reset/rst-rk3528.c
> @@ -0,0 +1,302 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
> + * Based on Sebastian Reichel's implementation for RK3588
> + */
> +
> +#include <dm.h>
> +#include <asm/arch-rockchip/clock.h>
> +#include <dt-bindings/reset/rockchip,rk3528-cru.h>
> +
> +/* 0xFF4A0000 + 0x0A00 */
> +#define RK3528_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
> +
> +/* mapping table for reset ID to register offset */
> +static const int rk3528_register_offset[] = {
> + /* CRU_SOFTRST_CON03 */
> + RK3528_CRU_RESET_OFFSET(SRST_CORE0_PO, 3, 0),
> + RK3528_CRU_RESET_OFFSET(SRST_CORE1_PO, 3, 1),
> + RK3528_CRU_RESET_OFFSET(SRST_CORE2_PO, 3, 2),
> + RK3528_CRU_RESET_OFFSET(SRST_CORE3_PO, 3, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_CORE0, 3, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_CORE1, 3, 5),
> + RK3528_CRU_RESET_OFFSET(SRST_CORE2, 3, 6),
> + RK3528_CRU_RESET_OFFSET(SRST_CORE3, 3, 7),
> + RK3528_CRU_RESET_OFFSET(SRST_NL2, 3, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_CORE_BIU, 3, 9),
> + RK3528_CRU_RESET_OFFSET(SRST_CORE_CRYPTO, 3, 10),
> +
> + /* CRU_SOFTRST_CON05 */
> + RK3528_CRU_RESET_OFFSET(SRST_P_DBG, 5, 13),
> + RK3528_CRU_RESET_OFFSET(SRST_POT_DBG, 5, 14),
> + RK3528_CRU_RESET_OFFSET(SRST_NT_DBG, 5, 15),
> +
> + /* CRU_SOFTRST_CON06 */
> + RK3528_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 6, 2),
> + RK3528_CRU_RESET_OFFSET(SRST_P_DAPLITE_BIU, 6, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_P_CPU_BIU, 6, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 6, 7),
> +
> + /* CRU_SOFTRST_CON08 */
> + RK3528_CRU_RESET_OFFSET(SRST_A_BUS_VOPGL_BIU, 8, 1),
> + RK3528_CRU_RESET_OFFSET(SRST_A_BUS_H_BIU, 8, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 8, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 8, 10),
> + RK3528_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 8, 11),
> + RK3528_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 8, 12),
> + RK3528_CRU_RESET_OFFSET(SRST_P_DFT2APB, 8, 13),
> + RK3528_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 8, 15),
> +
> + /* CRU_SOFTRST_CON09 */
> + RK3528_CRU_RESET_OFFSET(SRST_A_BUS_M_BIU, 9, 0),
> + RK3528_CRU_RESET_OFFSET(SRST_A_GIC, 9, 1),
> + RK3528_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 9, 2),
> + RK3528_CRU_RESET_OFFSET(SRST_A_DMAC, 9, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_P_TIMER, 9, 5),
> + RK3528_CRU_RESET_OFFSET(SRST_TIMER0, 9, 6),
> + RK3528_CRU_RESET_OFFSET(SRST_TIMER1, 9, 7),
> + RK3528_CRU_RESET_OFFSET(SRST_TIMER2, 9, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_TIMER3, 9, 9),
> + RK3528_CRU_RESET_OFFSET(SRST_TIMER4, 9, 10),
> + RK3528_CRU_RESET_OFFSET(SRST_TIMER5, 9, 11),
> + RK3528_CRU_RESET_OFFSET(SRST_P_JDBCK_DAP, 9, 12),
> + RK3528_CRU_RESET_OFFSET(SRST_JDBCK_DAP, 9, 13),
> + RK3528_CRU_RESET_OFFSET(SRST_P_WDT_NS, 9, 15),
> +
> + /* CRU_SOFTRST_CON10 */
> + RK3528_CRU_RESET_OFFSET(SRST_T_WDT_NS, 10, 0),
> + RK3528_CRU_RESET_OFFSET(SRST_H_TRNG_NS, 10, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_P_UART0, 10, 7),
> + RK3528_CRU_RESET_OFFSET(SRST_S_UART0, 10, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_PKA_CRYPTO, 10, 10),
> + RK3528_CRU_RESET_OFFSET(SRST_A_CRYPTO, 10, 11),
> + RK3528_CRU_RESET_OFFSET(SRST_H_CRYPTO, 10, 12),
> + RK3528_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 10, 13),
> + RK3528_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 10, 14),
> +
> + /* CRU_SOFTRST_CON11 */
> + RK3528_CRU_RESET_OFFSET(SRST_P_PWM0, 11, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_PWM0, 11, 5),
> + RK3528_CRU_RESET_OFFSET(SRST_P_PWM1, 11, 7),
> + RK3528_CRU_RESET_OFFSET(SRST_PWM1, 11, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_P_SCR, 11, 10),
> + RK3528_CRU_RESET_OFFSET(SRST_A_DCF, 11, 11),
> + RK3528_CRU_RESET_OFFSET(SRST_P_INTMUX, 11, 12),
> +
> + /* CRU_SOFTRST_CON25 */
> + RK3528_CRU_RESET_OFFSET(SRST_A_VPU_BIU, 25, 6),
> + RK3528_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 25, 7),
> + RK3528_CRU_RESET_OFFSET(SRST_P_VPU_BIU, 25, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_A_VPU, 25, 9),
> + RK3528_CRU_RESET_OFFSET(SRST_H_VPU, 25, 10),
> + RK3528_CRU_RESET_OFFSET(SRST_P_CRU_PCIE, 25, 11),
> + RK3528_CRU_RESET_OFFSET(SRST_P_VPU_GRF, 25, 12),
> + RK3528_CRU_RESET_OFFSET(SRST_H_SFC, 25, 13),
> + RK3528_CRU_RESET_OFFSET(SRST_S_SFC, 25, 14),
> + RK3528_CRU_RESET_OFFSET(SRST_C_EMMC, 25, 15),
> +
> + /* CRU_SOFTRST_CON26 */
> + RK3528_CRU_RESET_OFFSET(SRST_H_EMMC, 26, 0),
> + RK3528_CRU_RESET_OFFSET(SRST_A_EMMC, 26, 1),
> + RK3528_CRU_RESET_OFFSET(SRST_B_EMMC, 26, 2),
> + RK3528_CRU_RESET_OFFSET(SRST_T_EMMC, 26, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_P_GPIO1, 26, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO1, 26, 5),
> + RK3528_CRU_RESET_OFFSET(SRST_A_VPU_L_BIU, 26, 6),
> + RK3528_CRU_RESET_OFFSET(SRST_P_VPU_IOC, 26, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S0, 26, 9),
> + RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S0, 26, 10),
> + RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S2, 26, 11),
> + RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S2, 26, 12),
> + RK3528_CRU_RESET_OFFSET(SRST_P_ACODEC, 26, 13),
> +
> + /* CRU_SOFTRST_CON27 */
> + RK3528_CRU_RESET_OFFSET(SRST_P_GPIO3, 27, 0),
> + RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO3, 27, 1),
> + RK3528_CRU_RESET_OFFSET(SRST_P_SPI1, 27, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_SPI1, 27, 5),
> + RK3528_CRU_RESET_OFFSET(SRST_P_UART2, 27, 7),
> + RK3528_CRU_RESET_OFFSET(SRST_S_UART2, 27, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_P_UART5, 27, 9),
> + RK3528_CRU_RESET_OFFSET(SRST_S_UART5, 27, 10),
> + RK3528_CRU_RESET_OFFSET(SRST_P_UART6, 27, 11),
> + RK3528_CRU_RESET_OFFSET(SRST_S_UART6, 27, 12),
> + RK3528_CRU_RESET_OFFSET(SRST_P_UART7, 27, 13),
> + RK3528_CRU_RESET_OFFSET(SRST_S_UART7, 27, 14),
> + RK3528_CRU_RESET_OFFSET(SRST_P_I2C3, 27, 15),
> +
> + /* CRU_SOFTRST_CON28 */
> + RK3528_CRU_RESET_OFFSET(SRST_I2C3, 28, 0),
> + RK3528_CRU_RESET_OFFSET(SRST_P_I2C5, 28, 1),
> + RK3528_CRU_RESET_OFFSET(SRST_I2C5, 28, 2),
> + RK3528_CRU_RESET_OFFSET(SRST_P_I2C6, 28, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_I2C6, 28, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_A_MAC, 28, 5),
> +
> + /* CRU_SOFTRST_CON30 */
> + RK3528_CRU_RESET_OFFSET(SRST_P_PCIE, 30, 1),
> + RK3528_CRU_RESET_OFFSET(SRST_PCIE_PIPE_PHY, 30, 2),
> + RK3528_CRU_RESET_OFFSET(SRST_PCIE_POWER_UP, 30, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_P_PCIE_PHY, 30, 6),
> + RK3528_CRU_RESET_OFFSET(SRST_P_PIPE_GRF, 30, 7),
> +
> + /* CRU_SOFTRST_CON32 */
> + RK3528_CRU_RESET_OFFSET(SRST_H_SDIO0, 32, 2),
> + RK3528_CRU_RESET_OFFSET(SRST_H_SDIO1, 32, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_TS_0, 32, 5),
> + RK3528_CRU_RESET_OFFSET(SRST_TS_1, 32, 6),
> + RK3528_CRU_RESET_OFFSET(SRST_P_CAN2, 32, 7),
> + RK3528_CRU_RESET_OFFSET(SRST_CAN2, 32, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_P_CAN3, 32, 9),
> + RK3528_CRU_RESET_OFFSET(SRST_CAN3, 32, 10),
> + RK3528_CRU_RESET_OFFSET(SRST_P_SARADC, 32, 11),
> + RK3528_CRU_RESET_OFFSET(SRST_SARADC, 32, 12),
> + RK3528_CRU_RESET_OFFSET(SRST_SARADC_PHY, 32, 13),
> + RK3528_CRU_RESET_OFFSET(SRST_P_TSADC, 32, 14),
> + RK3528_CRU_RESET_OFFSET(SRST_TSADC, 32, 15),
> +
> + /* CRU_SOFTRST_CON33 */
> + RK3528_CRU_RESET_OFFSET(SRST_A_USB3OTG, 33, 1),
> +
> + /* CRU_SOFTRST_CON34 */
> + RK3528_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 34, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 34, 5),
> + RK3528_CRU_RESET_OFFSET(SRST_A_GPU, 34, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 34, 9),
> +
> + /* CRU_SOFTRST_CON36 */
> + RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC_BIU, 36, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC_BIU, 36, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_BIU, 36, 5),
> + RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC, 36, 6),
> + RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC, 36, 7),
> + RK3528_CRU_RESET_OFFSET(SRST_CORE_RKVENC, 36, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S1, 36, 9),
> + RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S1, 36, 10),
> + RK3528_CRU_RESET_OFFSET(SRST_P_I2C1, 36, 11),
> + RK3528_CRU_RESET_OFFSET(SRST_I2C1, 36, 12),
> + RK3528_CRU_RESET_OFFSET(SRST_P_I2C0, 36, 13),
> + RK3528_CRU_RESET_OFFSET(SRST_I2C0, 36, 14),
> +
> + /* CRU_SOFTRST_CON37 */
> + RK3528_CRU_RESET_OFFSET(SRST_P_SPI0, 37, 2),
> + RK3528_CRU_RESET_OFFSET(SRST_SPI0, 37, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_P_GPIO4, 37, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO4, 37, 9),
> + RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_IOC, 37, 10),
> + RK3528_CRU_RESET_OFFSET(SRST_H_SPDIF, 37, 14),
> + RK3528_CRU_RESET_OFFSET(SRST_M_SPDIF, 37, 15),
> +
> + /* CRU_SOFTRST_CON38 */
> + RK3528_CRU_RESET_OFFSET(SRST_H_PDM, 38, 0),
> + RK3528_CRU_RESET_OFFSET(SRST_M_PDM, 38, 1),
> + RK3528_CRU_RESET_OFFSET(SRST_P_UART1, 38, 2),
> + RK3528_CRU_RESET_OFFSET(SRST_S_UART1, 38, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_P_UART3, 38, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_S_UART3, 38, 5),
> + RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_GRF, 38, 6),
> + RK3528_CRU_RESET_OFFSET(SRST_P_CAN0, 38, 7),
> + RK3528_CRU_RESET_OFFSET(SRST_CAN0, 38, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_P_CAN1, 38, 9),
> + RK3528_CRU_RESET_OFFSET(SRST_CAN1, 38, 10),
> +
> + /* CRU_SOFTRST_CON39 */
> + RK3528_CRU_RESET_OFFSET(SRST_A_VO_BIU, 39, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_H_VO_BIU, 39, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_P_VO_BIU, 39, 5),
> + RK3528_CRU_RESET_OFFSET(SRST_H_RGA2E, 39, 7),
> + RK3528_CRU_RESET_OFFSET(SRST_A_RGA2E, 39, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_CORE_RGA2E, 39, 9),
> + RK3528_CRU_RESET_OFFSET(SRST_H_VDPP, 39, 10),
> + RK3528_CRU_RESET_OFFSET(SRST_A_VDPP, 39, 11),
> + RK3528_CRU_RESET_OFFSET(SRST_CORE_VDPP, 39, 12),
> + RK3528_CRU_RESET_OFFSET(SRST_P_VO_GRF, 39, 13),
> + RK3528_CRU_RESET_OFFSET(SRST_P_CRU, 39, 15),
> +
> + /* CRU_SOFTRST_CON40 */
> + RK3528_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 40, 1),
> + RK3528_CRU_RESET_OFFSET(SRST_H_VOP, 40, 2),
> + RK3528_CRU_RESET_OFFSET(SRST_D_VOP0, 40, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_D_VOP1, 40, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_A_VOP, 40, 5),
> + RK3528_CRU_RESET_OFFSET(SRST_P_HDMI, 40, 6),
> + RK3528_CRU_RESET_OFFSET(SRST_HDMI, 40, 7),
> + RK3528_CRU_RESET_OFFSET(SRST_P_HDMIPHY, 40, 14),
> + RK3528_CRU_RESET_OFFSET(SRST_H_HDCP_KEY, 40, 15),
> +
> + /* CRU_SOFTRST_CON41 */
> + RK3528_CRU_RESET_OFFSET(SRST_A_HDCP, 41, 0),
> + RK3528_CRU_RESET_OFFSET(SRST_H_HDCP, 41, 1),
> + RK3528_CRU_RESET_OFFSET(SRST_P_HDCP, 41, 2),
> + RK3528_CRU_RESET_OFFSET(SRST_H_CVBS, 41, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_D_CVBS_VOP, 41, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_D_4X_CVBS_VOP, 41, 5),
> + RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 41, 6),
> + RK3528_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 41, 7),
> + RK3528_CRU_RESET_OFFSET(SRST_A_VO_L_BIU, 41, 9),
> + RK3528_CRU_RESET_OFFSET(SRST_A_MAC_VO, 41, 10),
> +
> + /* CRU_SOFTRST_CON42 */
> + RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 42, 0),
> + RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S3, 42, 1),
> + RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S3, 42, 2),
> + RK3528_CRU_RESET_OFFSET(SRST_MACPHY, 42, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_P_VCDCPHY, 42, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_P_GPIO2, 42, 5),
> + RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO2, 42, 6),
> + RK3528_CRU_RESET_OFFSET(SRST_P_VO_IOC, 42, 7),
> + RK3528_CRU_RESET_OFFSET(SRST_H_SDMMC0, 42, 9),
> + RK3528_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 42, 11),
> + RK3528_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 42, 12),
> + RK3528_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 42, 13),
> +
> + /* CRU_SOFTRST_CON43 */
> + RK3528_CRU_RESET_OFFSET(SRST_HDMIHDP0, 43, 2),
> + RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST, 43, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST_ARB, 43, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_HOST_UTMI, 43, 6),
> + RK3528_CRU_RESET_OFFSET(SRST_P_UART4, 43, 7),
> + RK3528_CRU_RESET_OFFSET(SRST_S_UART4, 43, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_P_I2C4, 43, 9),
> + RK3528_CRU_RESET_OFFSET(SRST_I2C4, 43, 10),
> + RK3528_CRU_RESET_OFFSET(SRST_P_I2C7, 43, 11),
> + RK3528_CRU_RESET_OFFSET(SRST_I2C7, 43, 12),
> + RK3528_CRU_RESET_OFFSET(SRST_P_USBPHY, 43, 13),
> + RK3528_CRU_RESET_OFFSET(SRST_USBPHY_POR, 43, 14),
> + RK3528_CRU_RESET_OFFSET(SRST_USBPHY_OTG, 43, 15),
> +
> + /* CRU_SOFTRST_CON44 */
> + RK3528_CRU_RESET_OFFSET(SRST_USBPHY_HOST, 44, 0),
> + RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY_CRU, 44, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 44, 6),
> + RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 44, 7),
> + RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC, 44, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC, 44, 9),
> + RK3528_CRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 44, 11),
> + RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_RKVDEC, 44, 12),
> +
> + /* CRU_SOFTRST_CON45 */
> + RK3528_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 45, 1),
> + RK3528_CRU_RESET_OFFSET(SRST_P_DDRC, 45, 2),
> + RK3528_CRU_RESET_OFFSET(SRST_P_DDRMON, 45, 3),
> + RK3528_CRU_RESET_OFFSET(SRST_TIMER_DDRMON, 45, 4),
> + RK3528_CRU_RESET_OFFSET(SRST_P_MSCH_BIU, 45, 5),
> + RK3528_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 45, 6),
> + RK3528_CRU_RESET_OFFSET(SRST_P_DDR_HWLP, 45, 8),
> + RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY, 45, 9),
> + RK3528_CRU_RESET_OFFSET(SRST_MSCH_BIU, 45, 10),
> + RK3528_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL, 45, 11),
> + RK3528_CRU_RESET_OFFSET(SRST_DDR_UPCTL, 45, 12),
> + RK3528_CRU_RESET_OFFSET(SRST_DDRMON, 45, 13),
> + RK3528_CRU_RESET_OFFSET(SRST_A_DDR_SCRAMBLE, 45, 14),
> + RK3528_CRU_RESET_OFFSET(SRST_A_SPLIT, 45, 15),
> +
> + /* CRU_SOFTRST_CON46 */
> + RK3528_CRU_RESET_OFFSET(SRST_DDR_PHY, 46, 0),
> +};
> +
> +int rk3528_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number)
> +{
> + return rockchip_reset_bind_lut(pdev, rk3528_register_offset,
> + reg_offset, reg_number);
> +}
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 17/30] pinctrl: rockchip: Add support for RK3528
2025-04-07 22:46 ` [PATCH v2 17/30] pinctrl: " Jonas Karlman
@ 2025-04-08 3:23 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:23 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot
On 2025/4/8 06:46, Jonas Karlman wrote:
> From: Steven Liu <steven.liu@rock-chips.com>
>
> Add pinctrl driver for RK3528.
>
> Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with adjustments
> to use regmap_update_bits().
>
> Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> v2: Change to use if/else if instead of switch to match mainline Linux
> ---
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl-rk3528.c | 273 ++++++++++++++++++++++
> 2 files changed, 274 insertions(+)
> create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3528.c
>
> diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
> index c91f650b0434..df6c97d6234b 100644
> --- a/drivers/pinctrl/rockchip/Makefile
> +++ b/drivers/pinctrl/rockchip/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl-rk3308.o
> obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
> obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
> +obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o
> obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
> obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o
> obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3528.c b/drivers/pinctrl/rockchip/pinctrl-rk3528.c
> new file mode 100644
> index 000000000000..a3e1f0b2c9d5
> --- /dev/null
> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3528.c
> @@ -0,0 +1,273 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
> + */
> +
> +#include <dm.h>
> +#include <dm/pinctrl.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +
> +#include "pinctrl-rockchip.h"
> +#include <dt-bindings/pinctrl/rockchip.h>
> +
> +static int rk3528_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int iomux_num = (pin / 8);
> + struct regmap *regmap;
> + int reg, mask;
> + u8 bit;
> + u32 data, rmask;
> +
> + regmap = priv->regmap_base;
> + reg = bank->iomux[iomux_num].offset;
> + if ((pin % 8) >= 4)
> + reg += 0x4;
> + bit = (pin % 4) * 4;
> + mask = 0xf;
> +
> + data = (mask << (bit + 16));
> + rmask = data | (data >> 16);
> + data |= (mux & mask) << bit;
> +
> + return regmap_update_bits(regmap, reg, rmask, data);
> +}
> +
> +#define RK3528_DRV_BITS_PER_PIN 8
> +#define RK3528_DRV_PINS_PER_REG 2
> +#define RK3528_DRV_GPIO0_OFFSET 0x100
> +#define RK3528_DRV_GPIO1_OFFSET 0x20120
> +#define RK3528_DRV_GPIO2_OFFSET 0x30160
> +#define RK3528_DRV_GPIO3_OFFSET 0x20190
> +#define RK3528_DRV_GPIO4_OFFSET 0x101C0
> +
> +static void rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + *regmap = priv->regmap_base;
> +
> + if (bank->bank_num == 0) {
> + *reg = RK3528_DRV_GPIO0_OFFSET;
> + } else if (bank->bank_num == 1) {
> + *reg = RK3528_DRV_GPIO1_OFFSET;
> + } else if (bank->bank_num == 2) {
> + *reg = RK3528_DRV_GPIO2_OFFSET;
> + } else if (bank->bank_num == 3) {
> + *reg = RK3528_DRV_GPIO3_OFFSET;
> + } else if (bank->bank_num == 4) {
> + *reg = RK3528_DRV_GPIO4_OFFSET;
> + } else {
> + *reg = 0;
> + debug("unsupported bank_num %d\n", bank->bank_num);
> + }
> +
> + *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3528_DRV_PINS_PER_REG;
> + *bit *= RK3528_DRV_BITS_PER_PIN;
> +}
> +
> +static int rk3528_set_drive(struct rockchip_pin_bank *bank,
> + int pin_num, int strength)
> +{
> + struct regmap *regmap;
> + int reg;
> + u32 data, rmask;
> + u8 bit;
> + int drv = (1 << (strength + 1)) - 1;
> +
> + rk3528_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RK3528_DRV_BITS_PER_PIN) - 1) << (bit + 16);
> + rmask = data | (data >> 16);
> + data |= (drv << bit);
> +
> + return regmap_update_bits(regmap, reg, rmask, data);
> +}
> +
> +#define RK3528_PULL_BITS_PER_PIN 2
> +#define RK3528_PULL_PINS_PER_REG 8
> +#define RK3528_PULL_GPIO0_OFFSET 0x200
> +#define RK3528_PULL_GPIO1_OFFSET 0x20210
> +#define RK3528_PULL_GPIO2_OFFSET 0x30220
> +#define RK3528_PULL_GPIO3_OFFSET 0x20230
> +#define RK3528_PULL_GPIO4_OFFSET 0x10240
> +
> +static void rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num, struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + *regmap = priv->regmap_base;
> +
> + if (bank->bank_num == 0) {
> + *reg = RK3528_PULL_GPIO0_OFFSET;
> + } else if (bank->bank_num == 1) {
> + *reg = RK3528_PULL_GPIO1_OFFSET;
> + } else if (bank->bank_num == 2) {
> + *reg = RK3528_PULL_GPIO2_OFFSET;
> + } else if (bank->bank_num == 3) {
> + *reg = RK3528_PULL_GPIO3_OFFSET;
> + } else if (bank->bank_num == 4) {
> + *reg = RK3528_PULL_GPIO4_OFFSET;
> + } else {
> + *reg = 0;
> + debug("unsupported bank_num %d\n", bank->bank_num);
> + }
> +
> + *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3528_PULL_PINS_PER_REG;
> + *bit *= RK3528_PULL_BITS_PER_PIN;
> +}
> +
> +static int rk3528_set_pull(struct rockchip_pin_bank *bank,
> + int pin_num, int pull)
> +{
> + struct regmap *regmap;
> + int reg, ret;
> + u8 bit, type;
> + u32 data, rmask;
> +
> + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
> + return -EOPNOTSUPP;
> +
> + rk3528_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> + type = bank->pull_type[pin_num / 8];
> + ret = rockchip_translate_pull_value(type, pull);
> + if (ret < 0) {
> + debug("unsupported pull setting %d\n", pull);
> + return ret;
> + }
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RK3528_PULL_BITS_PER_PIN) - 1) << (bit + 16);
> + rmask = data | (data >> 16);
> + data |= (ret << bit);
> +
> + return regmap_update_bits(regmap, reg, rmask, data);
> +}
> +
> +#define RK3528_SMT_BITS_PER_PIN 1
> +#define RK3528_SMT_PINS_PER_REG 8
> +#define RK3528_SMT_GPIO0_OFFSET 0x400
> +#define RK3528_SMT_GPIO1_OFFSET 0x20410
> +#define RK3528_SMT_GPIO2_OFFSET 0x30420
> +#define RK3528_SMT_GPIO3_OFFSET 0x20430
> +#define RK3528_SMT_GPIO4_OFFSET 0x10440
> +
> +static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
> + int pin_num,
> + struct regmap **regmap,
> + int *reg, u8 *bit)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> +
> + *regmap = priv->regmap_base;
> +
> + if (bank->bank_num == 0) {
> + *reg = RK3528_SMT_GPIO0_OFFSET;
> + } else if (bank->bank_num == 1) {
> + *reg = RK3528_SMT_GPIO1_OFFSET;
> + } else if (bank->bank_num == 2) {
> + *reg = RK3528_SMT_GPIO2_OFFSET;
> + } else if (bank->bank_num == 3) {
> + *reg = RK3528_SMT_GPIO3_OFFSET;
> + } else if (bank->bank_num == 4) {
> + *reg = RK3528_SMT_GPIO4_OFFSET;
> + } else {
> + *reg = 0;
> + debug("unsupported bank_num %d\n", bank->bank_num);
> + }
> +
> + *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
> + *bit = pin_num % RK3528_SMT_PINS_PER_REG;
> + *bit *= RK3528_SMT_BITS_PER_PIN;
> +
> + return 0;
> +}
> +
> +static int rk3528_set_schmitt(struct rockchip_pin_bank *bank,
> + int pin_num, int enable)
> +{
> + struct regmap *regmap;
> + int reg;
> + u32 data, rmask;
> + u8 bit;
> +
> + rk3528_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
> +
> + /* enable the write to the equivalent lower bits */
> + data = ((1 << RK3528_SMT_BITS_PER_PIN) - 1) << (bit + 16);
> + rmask = data | (data >> 16);
> + data |= (enable << bit);
> +
> + return regmap_update_bits(regmap, reg, rmask, data);
> +}
> +
> +static struct rockchip_pin_bank rk3528_pin_banks[] = {
> + PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + 0, 0, 0, 0),
> + PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + 0x20020, 0x20028, 0x20030, 0x20038),
> + PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + 0x30040, 0, 0, 0),
> + PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + 0x20060, 0x20068, 0x20070, 0),
> + PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + IOMUX_WIDTH_4BIT,
> + 0x10080, 0x10088, 0x10090, 0x10098),
> +};
> +
> +static const struct rockchip_pin_ctrl rk3528_pin_ctrl = {
> + .pin_banks = rk3528_pin_banks,
> + .nr_banks = ARRAY_SIZE(rk3528_pin_banks),
> + .grf_mux_offset = 0x0,
> + .set_mux = rk3528_set_mux,
> + .set_pull = rk3528_set_pull,
> + .set_drive = rk3528_set_drive,
> + .set_schmitt = rk3528_set_schmitt,
> +};
> +
> +static const struct udevice_id rk3528_pinctrl_ids[] = {
> + {
> + .compatible = "rockchip,rk3528-pinctrl",
> + .data = (ulong)&rk3528_pin_ctrl
> + },
> + { }
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk3528_pinctrl) = {
> + .name = "rockchip_rk3528_pinctrl",
> + .id = UCLASS_PINCTRL,
> + .of_match = rk3528_pinctrl_ids,
> + .priv_auto = sizeof(struct rockchip_pinctrl_priv),
> + .ops = &rockchip_pinctrl_ops,
> +#if CONFIG_IS_ENABLED(OF_REAL)
> + .bind = dm_scan_fdt_dev,
> +#endif
> + .probe = rockchip_pinctrl_probe,
> +};
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 18/30] arm: dts: rockchip: Add rk3528-u-boot.dtsi
2025-04-07 22:46 ` [PATCH v2 18/30] arm: dts: rockchip: Add rk3528-u-boot.dtsi Jonas Karlman
@ 2025-04-08 3:23 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:23 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot
On 2025/4/8 06:46, Jonas Karlman wrote:
> Add a rk3528-u-boot.dtsi extending the basic dts/upstream rk3528.dtsi
> with bare minimum nodes to have a booting system from eMMC and SD-card.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> Changes in v2:
> - Use more nodes from dts/upstream rk3528.dtsi
> - Use sdmmc node from latest mainline Linux patch
> ---
> arch/arm/dts/rk3528-u-boot.dtsi | 148 ++++++++++++++++++++++++++++++++
> 1 file changed, 148 insertions(+)
> create mode 100644 arch/arm/dts/rk3528-u-boot.dtsi
>
> diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi
> new file mode 100644
> index 000000000000..eb6a55cd5c93
> --- /dev/null
> +++ b/arch/arm/dts/rk3528-u-boot.dtsi
> @@ -0,0 +1,148 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +#include "rockchip-u-boot.dtsi"
> +
> +/ {
> + aliases {
> + mmc0 = &sdhci;
> + mmc1 = &sdmmc;
> + };
> +
> + chosen {
> + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
> + };
> +
> + dmc {
> + compatible = "rockchip,rk3528-dmc";
> + bootph-all;
> + };
> +
> + soc {
> + rng: rng@ffc50000 {
> + compatible = "rockchip,rkrng";
> + reg = <0x0 0xffc50000 0x0 0x200>;
> + };
> +
> + otp: nvmem@ffce0000 {
> + compatible = "rockchip,rk3528-otp";
> + reg = <0x0 0xffce0000 0x0 0x4000>;
> + };
> +
> + sdmmc: mmc@ffc30000 {
> + compatible = "rockchip,rk3528-dw-mshc",
> + "rockchip,rk3288-dw-mshc";
> + reg = <0x0 0xffc30000 0x0 0x4000>;
> + clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
> + clock-names = "biu", "ciu";
> + fifo-depth = <0x100>;
> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> + max-frequency = <150000000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
> + <&sdmmc_det>;
> + resets = <&cru SRST_H_SDMMC0>;
> + reset-names = "reset";
> + rockchip,default-sample-phase = <90>;
> + status = "disabled";
> + };
> + };
> +};
> +
> +&cru {
> + bootph-all;
> +};
> +
> +&emmc_bus8 {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&emmc_clk {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&emmc_cmd {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&emmc_strb {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&gmac0_clk {
> + bootph-all;
> +};
> +
> +&ioc_grf {
> + bootph-all;
> +};
> +
> +&otp {
> + bootph-some-ram;
> +};
> +
> +&pcfg_pull_none {
> + bootph-all;
> +};
> +
> +&pcfg_pull_up {
> + bootph-all;
> +};
> +
> +&pcfg_pull_up_drv_level_2 {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&pinctrl {
> + bootph-all;
> +};
> +
> +&sdhci {
> + bootph-pre-ram;
> + bootph-some-ram;
> + u-boot,spl-fifo-mode;
> +};
> +
> +&sdmmc {
> + bootph-pre-ram;
> + bootph-some-ram;
> + u-boot,spl-fifo-mode;
> +};
> +
> +&sdmmc_bus4 {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&sdmmc_clk {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&sdmmc_cmd {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&sdmmc_det {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&uart0 {
> + bootph-all;
> + clock-frequency = <24000000>;
> +};
> +
> +&uart0m0_xfer {
> + bootph-pre-sram;
> + bootph-pre-ram;
> +};
> +
> +&xin24m {
> + bootph-all;
> +};
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 19/30] arch: arm: rockchip: Add initial support for RK3528
2025-04-07 22:46 ` [PATCH v2 19/30] arch: arm: rockchip: Add initial support for RK3528 Jonas Karlman
@ 2025-04-08 3:23 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:23 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini,
Lukasz Majewski, Mattijs Korpershoek, Marek Vasut
Cc: Yao Zi, Chukun Pan, u-boot
On 2025/4/8 06:46, Jonas Karlman wrote:
> Rockchip RK3528 is a ARM-based SoC with quad-core Cortex-A53.
>
> Add initial arch support for the RK3528 SoC.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> Changes in v2:
> - Add FIREWALL_DDR handling to fix emmc/fspi/sdmmc/usb dma
> - Add imply SYSRESET_PSCI if SPL_ATF
> - Add USB_GADGET_PRODUCT_NUM for RK3528
> - Drop ifndef CONFIG_XPL_BUILD in rk3528_common.h
> ---
> arch/arm/include/asm/arch-rk3528/boot0.h | 9 ++
> arch/arm/include/asm/arch-rk3528/gpio.h | 9 ++
> arch/arm/mach-rockchip/Kconfig | 51 +++++++
> arch/arm/mach-rockchip/Makefile | 1 +
> arch/arm/mach-rockchip/rk3528/Kconfig | 15 ++
> arch/arm/mach-rockchip/rk3528/Makefile | 5 +
> arch/arm/mach-rockchip/rk3528/clk_rk3528.c | 16 ++
> arch/arm/mach-rockchip/rk3528/rk3528.c | 137 ++++++++++++++++++
> arch/arm/mach-rockchip/rk3528/syscon_rk3528.c | 19 +++
> drivers/usb/gadget/Kconfig | 1 +
> include/configs/rk3528_common.h | 38 +++++
> 11 files changed, 301 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rk3528/boot0.h
> create mode 100644 arch/arm/include/asm/arch-rk3528/gpio.h
> create mode 100644 arch/arm/mach-rockchip/rk3528/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk3528/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk3528/clk_rk3528.c
> create mode 100644 arch/arm/mach-rockchip/rk3528/rk3528.c
> create mode 100644 arch/arm/mach-rockchip/rk3528/syscon_rk3528.c
> create mode 100644 include/configs/rk3528_common.h
>
> diff --git a/arch/arm/include/asm/arch-rk3528/boot0.h b/arch/arm/include/asm/arch-rk3528/boot0.h
> new file mode 100644
> index 000000000000..8ae46f25a87a
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rk3528/boot0.h
> @@ -0,0 +1,9 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/* Copyright Contributors to the U-Boot project. */
> +
> +#ifndef __ASM_ARCH_BOOT0_H__
> +#define __ASM_ARCH_BOOT0_H__
> +
> +#include <asm/arch-rockchip/boot0.h>
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-rk3528/gpio.h b/arch/arm/include/asm/arch-rk3528/gpio.h
> new file mode 100644
> index 000000000000..5516e649b80b
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rk3528/gpio.h
> @@ -0,0 +1,9 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/* Copyright Contributors to the U-Boot project. */
> +
> +#ifndef __ASM_ARCH_GPIO_H__
> +#define __ASM_ARCH_GPIO_H__
> +
> +#include <asm/arch-rockchip/gpio.h>
> +
> +#endif
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index f349431bb43c..be1525848411 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -322,6 +322,56 @@ config ROCKCHIP_RK3399
> and video codec support. Peripherals include Gigabit Ethernet,
> USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
>
> +config ROCKCHIP_RK3528
> + bool "Support Rockchip RK3528"
> + select ARM64
> + select SUPPORT_SPL
> + select SPL
> + select CLK
> + select PINCTRL
> + select RAM
> + select REGMAP
> + select SYSCON
> + select BOARD_LATE_INIT
> + select DM_REGULATOR_FIXED
> + select DM_RESET
> + imply ARMV8_CRYPTO
> + imply ARMV8_SET_SMPEN
> + imply BOOTSTD_FULL
> + imply DM_RNG
> + imply FIT
> + imply LEGACY_IMAGE_FORMAT
> + imply MISC
> + imply MISC_INIT_R
> + imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
> + imply OF_LIBFDT_OVERLAY
> + imply OF_LIVE
> + imply OF_UPSTREAM
> + imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
> + imply RNG_ROCKCHIP
> + imply ROCKCHIP_COMMON_BOARD
> + imply ROCKCHIP_COMMON_STACK_ADDR
> + imply ROCKCHIP_EXTERNAL_TPL
> + imply ROCKCHIP_OTP
> + imply SPL_ATF
> + imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
> + imply SPL_CLK
> + imply SPL_DM_SEQ_ALIAS
> + imply SPL_FIT_SIGNATURE
> + imply SPL_LOAD_FIT
> + imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
> + imply SPL_OF_CONTROL
> + imply SPL_PINCTRL
> + imply SPL_RAM
> + imply SPL_REGMAP
> + imply SPL_SERIAL
> + imply SPL_SYSCON
> + imply SYS_RELOC_GD_ENV_ADDR
> + imply SYSRESET
> + imply SYSRESET_PSCI if SPL_ATF
> + help
> + The Rockchip RK3528 is a ARM-based SoC with a quad-core Cortex-A53.
> +
> config ROCKCHIP_RK3568
> bool "Support Rockchip RK3568"
> select ARM64
> @@ -652,6 +702,7 @@ source "arch/arm/mach-rockchip/rk3308/Kconfig"
> source "arch/arm/mach-rockchip/rk3328/Kconfig"
> source "arch/arm/mach-rockchip/rk3368/Kconfig"
> source "arch/arm/mach-rockchip/rk3399/Kconfig"
> +source "arch/arm/mach-rockchip/rk3528/Kconfig"
> source "arch/arm/mach-rockchip/rk3568/Kconfig"
> source "arch/arm/mach-rockchip/rk3588/Kconfig"
> source "arch/arm/mach-rockchip/rv1108/Kconfig"
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index 5e7edc99cdc4..5a7dd5b59400 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -42,6 +42,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/
> obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
> obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
> obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
> +obj-$(CONFIG_ROCKCHIP_RK3528) += rk3528/
> obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
> obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
> obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
> diff --git a/arch/arm/mach-rockchip/rk3528/Kconfig b/arch/arm/mach-rockchip/rk3528/Kconfig
> new file mode 100644
> index 000000000000..993b2dd274ea
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3528/Kconfig
> @@ -0,0 +1,15 @@
> +if ROCKCHIP_RK3528
> +
> +config ROCKCHIP_BOOT_MODE_REG
> + default 0xff370200
> +
> +config ROCKCHIP_STIMER_BASE
> + default 0xff620000
> +
> +config SYS_SOC
> + default "rk3528"
> +
> +config SYS_CONFIG_NAME
> + default "rk3528_common"
> +
> +endif
> diff --git a/arch/arm/mach-rockchip/rk3528/Makefile b/arch/arm/mach-rockchip/rk3528/Makefile
> new file mode 100644
> index 000000000000..f0c18cd39d29
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3528/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0-or-later
> +
> +obj-y += rk3528.o
> +obj-y += clk_rk3528.o
> +obj-y += syscon_rk3528.o
> diff --git a/arch/arm/mach-rockchip/rk3528/clk_rk3528.c b/arch/arm/mach-rockchip/rk3528/clk_rk3528.c
> new file mode 100644
> index 000000000000..6e77f11cbec0
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3528/clk_rk3528.c
> @@ -0,0 +1,16 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +// Copyright Contributors to the U-Boot project.
> +
> +#include <dm.h>
> +#include <asm/arch-rockchip/cru_rk3528.h>
> +
> +int rockchip_get_clk(struct udevice **devp)
> +{
> + return uclass_get_device_by_driver(UCLASS_CLK,
> + DM_DRIVER_GET(rockchip_rk3528_cru), devp);
> +}
> +
> +void *rockchip_get_cru(void)
> +{
> + return RK3528_CRU_BASE;
> +}
> diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c
> new file mode 100644
> index 000000000000..4892ff6ba9d2
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3528/rk3528.c
> @@ -0,0 +1,137 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +// Copyright Contributors to the U-Boot project.
> +
> +#define LOG_CATEGORY LOGC_ARCH
> +
> +#include <dm.h>
> +#include <misc.h>
> +#include <asm/armv8/mmu.h>
> +#include <asm/arch-rockchip/bootrom.h>
> +#include <asm/arch-rockchip/hardware.h>
> +
> +#define FIREWALL_DDR_BASE 0xff2e0000
> +#define FW_DDR_MST6_REG 0x58
> +#define FW_DDR_MST7_REG 0x5c
> +#define FW_DDR_MST14_REG 0x78
> +#define FW_DDR_MST16_REG 0x80
> +
> +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
> + [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@ffbf0000",
> + [BROM_BOOTSOURCE_SD] = "/soc/mmc@ffc30000",
> +};
> +
> +static struct mm_region rk3528_mem_map[] = {
> + {
> + .virt = 0x0UL,
> + .phys = 0x0UL,
> + .size = 0xfc000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE
> + }, {
> + .virt = 0xfc000000UL,
> + .phys = 0xfc000000UL,
> + .size = 0x04000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* List terminator */
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = rk3528_mem_map;
> +
> +void board_debug_uart_init(void)
> +{
> +}
> +
> +int arch_cpu_init(void)
> +{
> + u32 val;
> +
> + if (!IS_ENABLED(CONFIG_SPL_BUILD))
> + return 0;
> +
> + /* Set the emmc to access ddr memory */
> + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
> + writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
> +
> + /* Set the fspi to access ddr memory */
> + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
> + writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
> +
> + /* Set the sdmmc to access ddr memory */
> + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
> + writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
> +
> + /* Set the usb to access ddr memory */
> + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
> + writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
> +
> + return 0;
> +}
> +
> +#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE
> +#define HP_CTRL_REG 0x04
> +#define TIMER_EN BIT(0)
> +#define HP_LOAD_COUNT0_REG 0x14
> +#define HP_LOAD_COUNT1_REG 0x18
> +
> +void rockchip_stimer_init(void)
> +{
> + u32 reg;
> +
> + if (!IS_ENABLED(CONFIG_XPL_BUILD))
> + return;
> +
> + reg = readl(HP_TIMER_BASE + HP_CTRL_REG);
> + if (reg & TIMER_EN)
> + return;
> +
> + asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
> + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG);
> + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG);
> + writel(TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG);
> +}
> +
> +#define RK3528_OTP_CPU_CODE_OFFSET 0x02
> +#define RK3528_OTP_CPU_CHIP_TYPE_OFFSET 0x28
> +
> +int checkboard(void)
> +{
> + u8 cpu_code[2], chip_type;
> + struct udevice *dev;
> + char suffix[2];
> + int ret;
> +
> + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
> + return 0;
> +
> + ret = uclass_get_device_by_driver(UCLASS_MISC,
> + DM_DRIVER_GET(rockchip_otp), &dev);
> + if (ret) {
> + log_debug("Could not find otp device, ret=%d\n", ret);
> + return 0;
> + }
> +
> + /* cpu-code: SoC model, e.g. 0x35 0x28 */
> + ret = misc_read(dev, RK3528_OTP_CPU_CODE_OFFSET, cpu_code, 2);
> + if (ret < 0) {
> + log_debug("Could not read cpu-code, ret=%d\n", ret);
> + return 0;
> + }
> +
> + ret = misc_read(dev, RK3528_OTP_CPU_CHIP_TYPE_OFFSET, &chip_type, 1);
> + if (ret < 0) {
> + log_debug("Could not read chip type, ret=%d\n", ret);
> + return 0;
> + }
> +
> + suffix[0] = chip_type != 0x1 ? 'A' : '\0';
> + suffix[1] = '\0';
> +
> + printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix);
> +
> + return 0;
> +}
> diff --git a/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c b/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c
> new file mode 100644
> index 000000000000..4a32a5f732e9
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c
> @@ -0,0 +1,19 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +// Copyright Contributors to the U-Boot project.
> +
> +#include <dm.h>
> +#include <asm/arch-rockchip/clock.h>
> +
> +static const struct udevice_id rk3528_syscon_ids[] = {
> + { .compatible = "rockchip,rk3528-grf", .data = ROCKCHIP_SYSCON_GRF },
> + { }
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk3528_syscon) = {
> + .name = "rockchip_rk3528_syscon",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3528_syscon_ids,
> +#if CONFIG_IS_ENABLED(OF_REAL)
> + .bind = dm_scan_fdt_dev,
> +#endif
> +};
> diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
> index c815764c2bc4..46a83141481f 100644
> --- a/drivers/usb/gadget/Kconfig
> +++ b/drivers/usb/gadget/Kconfig
> @@ -85,6 +85,7 @@ config USB_GADGET_PRODUCT_NUM
> default 0x330e if ROCKCHIP_RK3308
> default 0x350a if ROCKCHIP_RK3568
> default 0x350b if ROCKCHIP_RK3588
> + default 0x350c if ROCKCHIP_RK3528
> default 0x0
> help
> Product ID of the USB device emulated, reported to the host device.
> diff --git a/include/configs/rk3528_common.h b/include/configs/rk3528_common.h
> new file mode 100644
> index 000000000000..f7dc6ecd5944
> --- /dev/null
> +++ b/include/configs/rk3528_common.h
> @@ -0,0 +1,38 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/* Copyright Contributors to the U-Boot project. */
> +
> +#ifndef __CONFIG_RK3528_COMMON_H
> +#define __CONFIG_RK3528_COMMON_H
> +
> +#define CFG_CPUID_OFFSET 0xa
> +
> +#include "rockchip-common.h"
> +
> +#define CFG_IRAM_BASE 0xfe480000
> +
> +#define CFG_SYS_SDRAM_BASE 0
> +#define SDRAM_MAX_SIZE 0xfc000000
> +
> +#ifndef ROCKCHIP_DEVICE_SETTINGS
> +#define ROCKCHIP_DEVICE_SETTINGS
> +#endif
> +
> +#define ENV_MEM_LAYOUT_SETTINGS \
> + "scriptaddr=0x00c00000\0" \
> + "script_offset_f=0xffe000\0" \
> + "script_size_f=0x2000\0" \
> + "pxefile_addr_r=0x00e00000\0" \
> + "kernel_addr_r=0x02000000\0" \
> + "kernel_comp_addr_r=0x0a000000\0" \
> + "fdt_addr_r=0x12000000\0" \
> + "fdtoverlay_addr_r=0x12100000\0" \
> + "ramdisk_addr_r=0x12180000\0" \
> + "kernel_comp_size=0x8000000\0"
> +
> +#define CFG_EXTRA_ENV_SETTINGS \
> + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
> + ENV_MEM_LAYOUT_SETTINGS \
> + ROCKCHIP_DEVICE_SETTINGS \
> + "boot_targets=" BOOT_TARGETS "\0"
> +
> +#endif /* __CONFIG_RK3528_COMMON_H */
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 20/30] mmc: rockchip_sdhci: Extend variant configuration
2025-04-07 22:46 ` [PATCH v2 20/30] mmc: rockchip_sdhci: Extend variant configuration Jonas Karlman
@ 2025-04-08 3:23 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:23 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini, Peng Fan,
Jaehoon Chung
Cc: Yao Zi, Chukun Pan, u-boot
On 2025/4/8 06:46, Jonas Karlman wrote:
> RK3528 and RK3576 use different tap and delay num for cmdout and strbin.
>
> Move tap and delay num for cmdout and strbin to driver data to prepare
> for adding new SoCs.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> v2: No change
> ---
> drivers/mmc/rockchip_sdhci.c | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
> index da630b9d97a2..4968404bfaed 100644
> --- a/drivers/mmc/rockchip_sdhci.c
> +++ b/drivers/mmc/rockchip_sdhci.c
> @@ -156,6 +156,9 @@ struct sdhci_data {
> u32 flags;
> u8 hs200_txclk_tapnum;
> u8 hs400_txclk_tapnum;
> + u8 hs400_cmdout_tapnum;
> + u8 hs400_strbin_tapnum;
> + u8 ddr50_strbin_delay_num;
> };
>
> static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
> @@ -348,7 +351,7 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
> extra = DLL_CMDOUT_SRC_CLK_NEG |
> DLL_CMDOUT_BOTH_CLK_EDGE |
> DWCMSHC_EMMC_DLL_DLYENA |
> - DLL_CMDOUT_TAPNUM_90_DEGREES |
> + data->hs400_cmdout_tapnum |
> DLL_CMDOUT_TAPNUM_FROM_SW;
> sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CMDOUT);
> }
> @@ -360,7 +363,7 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
> sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
>
> extra = DWCMSHC_EMMC_DLL_DLYENA |
> - DLL_STRBIN_TAPNUM_DEFAULT |
> + data->hs400_strbin_tapnum |
> DLL_STRBIN_TAPNUM_FROM_SW;
> sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
> } else {
> @@ -380,7 +383,7 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
> */
> extra = DWCMSHC_EMMC_DLL_DLYENA |
> DLL_STRBIN_DELAY_NUM_SEL |
> - DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET;
> + data->ddr50_strbin_delay_num << DLL_STRBIN_DELAY_NUM_OFFSET;
> sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
> }
>
> @@ -654,6 +657,9 @@ static const struct sdhci_data rk3568_data = {
> .flags = FLAG_INVERTER_FLAG_IN_RXCLK,
> .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
> .hs400_txclk_tapnum = 0x8,
> + .hs400_cmdout_tapnum = DLL_CMDOUT_TAPNUM_90_DEGREES,
> + .hs400_strbin_tapnum = DLL_STRBIN_TAPNUM_DEFAULT,
> + .ddr50_strbin_delay_num = DLL_STRBIN_DELAY_NUM_DEFAULT,
> };
>
> static const struct sdhci_data rk3588_data = {
> @@ -662,6 +668,9 @@ static const struct sdhci_data rk3588_data = {
> .config_dll = rk3568_sdhci_config_dll,
> .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
> .hs400_txclk_tapnum = 0x9,
> + .hs400_cmdout_tapnum = DLL_CMDOUT_TAPNUM_90_DEGREES,
> + .hs400_strbin_tapnum = DLL_STRBIN_TAPNUM_DEFAULT,
> + .ddr50_strbin_delay_num = DLL_STRBIN_DELAY_NUM_DEFAULT,
> };
>
> static const struct udevice_id sdhci_ids[] = {
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 21/30] mmc: rockchip_sdhci: Add initial support for RK3528
2025-04-07 22:46 ` [PATCH v2 21/30] mmc: rockchip_sdhci: Add initial support for RK3528 Jonas Karlman
@ 2025-04-08 3:23 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:23 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini, Peng Fan,
Jaehoon Chung
Cc: Yao Zi, Chukun Pan, u-boot
On 2025/4/8 06:46, Jonas Karlman wrote:
> Add initial support for SDHCI controller in RK3528.
>
> Only MMC Legacy and MMC High Speed (52MHz) mode is supported after this,
> more work is needed to get the faster HS200/HS400/HS400ES modes working.
>
> Variant tap and delay num is copied from vendor Linux tag
> linux-6.1-stan-rkr5.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> v2: No change
> ---
> drivers/mmc/rockchip_sdhci.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
> index 4968404bfaed..2c54b8a942da 100644
> --- a/drivers/mmc/rockchip_sdhci.c
> +++ b/drivers/mmc/rockchip_sdhci.c
> @@ -650,6 +650,17 @@ static const struct sdhci_data rk3399_data = {
> .set_enhanced_strobe = rk3399_sdhci_set_enhanced_strobe,
> };
>
> +static const struct sdhci_data rk3528_data = {
> + .set_ios_post = rk3568_sdhci_set_ios_post,
> + .set_clock = rk3568_sdhci_set_clock,
> + .config_dll = rk3568_sdhci_config_dll,
> + .hs200_txclk_tapnum = 0xc,
> + .hs400_txclk_tapnum = 0x6,
> + .hs400_cmdout_tapnum = 0x6,
> + .hs400_strbin_tapnum = 0x3,
> + .ddr50_strbin_delay_num = 0xa,
> +};
> +
> static const struct sdhci_data rk3568_data = {
> .set_ios_post = rk3568_sdhci_set_ios_post,
> .set_clock = rk3568_sdhci_set_clock,
> @@ -678,6 +689,10 @@ static const struct udevice_id sdhci_ids[] = {
> .compatible = "arasan,sdhci-5.1",
> .data = (ulong)&rk3399_data,
> },
> + {
> + .compatible = "rockchip,rk3528-dwcmshc",
> + .data = (ulong)&rk3528_data,
> + },
> {
> .compatible = "rockchip,rk3568-dwcmshc",
> .data = (ulong)&rk3568_data,
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 22/30] mmc: rockchip_sdhci: Gate clock for glitch free phase switching
2025-04-07 22:46 ` [PATCH v2 22/30] mmc: rockchip_sdhci: Gate clock for glitch free phase switching Jonas Karlman
@ 2025-04-08 3:23 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:23 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini, Peng Fan,
Jaehoon Chung
Cc: Yao Zi, Chukun Pan, u-boot
On 2025/4/8 06:46, Jonas Karlman wrote:
> Enable clock stopping to gate clock during phase code change to ensure
> glitch free phase switching in auto-tuning circuit. Fixes HS200 mode
> on RK3528.
>
> POST_CHANGE_DLY
> Time taken for phase switching and stable clock output.
> - Less than 4-cycle latency
>
> PRE_CHANGE_DLY
> Maximum Latency specification between transmit clock and receive clock.
> - Less than 4-cycle latency
>
> TUNE_CLK_STOP_EN
> Clock stopping control for Tuning and auto-tuning circuit. When enabled,
> clock gate control output is pulled low before changing phase select
> codes. This effectively stops the receive clock. Changing phase code
> when clocks are stopped ensures glitch free phase switching.
> - Clocks stopped during phase code change
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> v2: No change
> ---
> drivers/mmc/rockchip_sdhci.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
> index 2c54b8a942da..c0f986784366 100644
> --- a/drivers/mmc/rockchip_sdhci.c
> +++ b/drivers/mmc/rockchip_sdhci.c
> @@ -50,6 +50,10 @@
> #define DWCMSHC_EMMC_EMMC_CTRL 0x52c
> #define DWCMSHC_CARD_IS_EMMC BIT(0)
> #define DWCMSHC_ENHANCED_STROBE BIT(8)
> +#define DWCMSHC_EMMC_AT_CTRL 0x540
> +#define EMMC_AT_CTRL_TUNE_CLK_STOP_EN BIT(16)
> +#define EMMC_AT_CTRL_PRE_CHANGE_DLY 17
> +#define EMMC_AT_CTRL_POST_CHANGE_DLY 19
> #define DWCMSHC_EMMC_DLL_CTRL 0x800
> #define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
> #define DWCMSHC_EMMC_DLL_RXCLK 0x804
> @@ -326,6 +330,11 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host, u32 clock, bool enab
> udelay(1);
> sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
>
> + extra = 0x3 << EMMC_AT_CTRL_POST_CHANGE_DLY |
> + 0x3 << EMMC_AT_CTRL_PRE_CHANGE_DLY |
> + EMMC_AT_CTRL_TUNE_CLK_STOP_EN;
> + sdhci_writel(host, extra, DWCMSHC_EMMC_AT_CTRL);
> +
> /* Init DLL settings */
> extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
> DWCMSHC_EMMC_DLL_INC_VALUE << DWCMSHC_EMMC_DLL_INC |
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 23/30] rockchip: otp: Add support for RK3528
2025-04-07 22:46 ` [PATCH v2 23/30] rockchip: otp: Add support for RK3528 Jonas Karlman
@ 2025-04-08 3:23 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:23 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot
On 2025/4/8 06:46, Jonas Karlman wrote:
> Add support for the OTP controller in RK3528. The OTPC is similar to the
> OTPC in RK3568 and can use the same ops for reading OTP data.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> v2: New patch
> ---
> drivers/misc/rockchip-otp.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/misc/rockchip-otp.c b/drivers/misc/rockchip-otp.c
> index 2123c31038fc..b5597de39aca 100644
> --- a/drivers/misc/rockchip-otp.c
> +++ b/drivers/misc/rockchip-otp.c
> @@ -383,6 +383,10 @@ static const struct udevice_id rockchip_otp_ids[] = {
> .compatible = "rockchip,rk3308-otp",
> .data = (ulong)&px30_data,
> },
> + {
> + .compatible = "rockchip,rk3528-otp",
> + .data = (ulong)&rk3568_data,
> + },
> {
> .compatible = "rockchip,rk3568-otp",
> .data = (ulong)&rk3568_data,
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 24/30] adc: rockchip-saradc: Add support for RK3528
2025-04-07 22:46 ` [PATCH v2 24/30] adc: rockchip-saradc: " Jonas Karlman
@ 2025-04-08 3:24 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:24 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot
On 2025/4/8 06:46, Jonas Karlman wrote:
> The Successive Approximation ADC (SARADC) in RK3528 uses the v2
> controller and support:
> - 10-bit resolution
> - Up to 1MS/s sampling rate
> - 4 single-ended input channels
> - Current consumption: 0.5mA @ 1MS/s
>
> Add support for the 4 channels of 10-bit resolution supported by SARADC
> in RK3528.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> v2: New patch
> ---
> drivers/adc/rockchip-saradc.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/adc/rockchip-saradc.c b/drivers/adc/rockchip-saradc.c
> index 7cf9735f60d0..1515951403c9 100644
> --- a/drivers/adc/rockchip-saradc.c
> +++ b/drivers/adc/rockchip-saradc.c
> @@ -339,6 +339,14 @@ static const struct rockchip_saradc_data rk3399_saradc_data = {
> .stop = rockchip_saradc_stop_v1,
> };
>
> +static const struct rockchip_saradc_data rk3528_saradc_data = {
> + .num_bits = 10,
> + .num_channels = 4,
> + .clk_rate = 1000000,
> + .channel_data = rockchip_saradc_channel_data_v2,
> + .start_channel = rockchip_saradc_start_channel_v2,
> +};
> +
> static const struct rockchip_saradc_data rk3588_saradc_data = {
> .num_bits = 12,
> .num_channels = 8,
> @@ -354,6 +362,8 @@ static const struct udevice_id rockchip_saradc_ids[] = {
> .data = (ulong)&rk3066_tsadc_data },
> { .compatible = "rockchip,rk3399-saradc",
> .data = (ulong)&rk3399_saradc_data },
> + { .compatible = "rockchip,rk3528-saradc",
> + .data = (ulong)&rk3528_saradc_data },
> { .compatible = "rockchip,rk3588-saradc",
> .data = (ulong)&rk3588_saradc_data },
> { }
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 25/30] rng: rockchip: Add support for rkrng variant
2025-04-07 22:46 ` [PATCH v2 25/30] rng: rockchip: Add support for rkrng variant Jonas Karlman
@ 2025-04-08 3:24 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:24 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini,
Sughosh Ganu, Heinrich Schuchardt
Cc: Yao Zi, Chukun Pan, u-boot, Lin Jinhan
On 2025/4/8 06:46, Jonas Karlman wrote:
> From: Lin Jinhan <troy.lin@rock-chips.com>
>
> Add support for rkrng variant, used by e.g. RK3528 and RK3576.
>
> Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with minor
> adjustments for mainline.
>
> Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> v2: Rebase on "rockchip: Update rng compatible for RK356x and RK3588"
> ---
> drivers/rng/rockchip_rng.c | 73 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 73 insertions(+)
>
> diff --git a/drivers/rng/rockchip_rng.c b/drivers/rng/rockchip_rng.c
> index 6e4e3abf08c8..d854ea900442 100644
> --- a/drivers/rng/rockchip_rng.c
> +++ b/drivers/rng/rockchip_rng.c
> @@ -70,6 +70,27 @@
> #define TRNG_v1_VERSION_CODE 0x46BC
> /* end of TRNG V1 register define */
>
> +/* start of RKRNG register define */
> +#define RKRNG_CTRL 0x0010
> +#define RKRNG_CTRL_INST_REQ BIT(0)
> +#define RKRNG_CTRL_RESEED_REQ BIT(1)
> +#define RKRNG_CTRL_TEST_REQ BIT(2)
> +#define RKRNG_CTRL_SW_DRNG_REQ BIT(3)
> +#define RKRNG_CTRL_SW_TRNG_REQ BIT(4)
> +
> +#define RKRNG_STATE 0x0014
> +#define RKRNG_STATE_INST_ACK BIT(0)
> +#define RKRNG_STATE_RESEED_ACK BIT(1)
> +#define RKRNG_STATE_TEST_ACK BIT(2)
> +#define RKRNG_STATE_SW_DRNG_ACK BIT(3)
> +#define RKRNG_STATE_SW_TRNG_ACK BIT(4)
> +
> +/* DRNG_DATA_0 ~ DNG_DATA_7 */
> +#define RKRNG_DRNG_DATA_0 0x0070
> +#define RKRNG_DRNG_DATA_7 0x008C
> +
> +/* end of RKRNG register define */
> +
> #define RK_RNG_TIME_OUT 50000 /* max 50ms */
>
> #define trng_write(pdata, pos, val) writel(val, (pdata)->base + (pos))
> @@ -228,6 +249,49 @@ exit:
> return retval;
> }
>
> +static int rkrng_init(struct udevice *dev)
> +{
> + struct rk_rng_plat *pdata = dev_get_priv(dev);
> + u32 reg = 0;
> +
> + rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff);
> +
> + reg = trng_read(pdata, RKRNG_STATE);
> + trng_write(pdata, RKRNG_STATE, reg);
> +
> + return 0;
> +}
> +
> +static int rkrng_rng_read(struct udevice *dev, void *data, size_t len)
> +{
> + struct rk_rng_plat *pdata = dev_get_priv(dev);
> + u32 reg = 0;
> + int retval;
> +
> + if (len > RK_HW_RNG_MAX)
> + return -EINVAL;
> +
> + reg = RKRNG_CTRL_SW_DRNG_REQ;
> +
> + rk_clrsetreg(pdata->base + RKRNG_CTRL, 0xffff, reg);
> +
> + retval = readl_poll_timeout(pdata->base + RKRNG_STATE, reg,
> + (reg & RKRNG_STATE_SW_DRNG_ACK),
> + RK_RNG_TIME_OUT);
> + if (retval)
> + goto exit;
> +
> + trng_write(pdata, RKRNG_STATE, reg);
> +
> + rk_rng_read_regs(pdata->base + RKRNG_DRNG_DATA_0, data, len);
> +
> +exit:
> + /* close TRNG */
> + rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff);
> +
> + return retval;
> +}
> +
> static int rockchip_rng_read(struct udevice *dev, void *data, size_t len)
> {
> unsigned char *buf = data;
> @@ -295,6 +359,11 @@ static const struct rk_rng_soc_data rk_trngv1_soc_data = {
> .rk_rng_read = rk_trngv1_rng_read,
> };
>
> +static const struct rk_rng_soc_data rkrng_soc_data = {
> + .rk_rng_init = rkrng_init,
> + .rk_rng_read = rkrng_rng_read,
> +};
> +
> static const struct dm_rng_ops rockchip_rng_ops = {
> .read = rockchip_rng_read,
> };
> @@ -324,6 +393,10 @@ static const struct udevice_id rockchip_rng_match[] = {
> .compatible = "rockchip,rk3588-rng",
> .data = (ulong)&rk_trngv1_soc_data,
> },
> + {
> + .compatible = "rockchip,rkrng",
> + .data = (ulong)&rkrng_soc_data,
> + },
> {},
> };
>
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 26/30] phy: rockchip-inno-usb2: Add support for clkout_ctl_phy
2025-04-07 22:46 ` [PATCH v2 26/30] phy: rockchip-inno-usb2: Add support for clkout_ctl_phy Jonas Karlman
@ 2025-04-08 3:24 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:24 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot
On 2025/4/8 06:46, Jonas Karlman wrote:
> The 480m clk is controlled using regs in the PHY address space and not
> in the USB GRF address space on e.g. RK3528 and RK3506.
>
> Add a clkout_ctl_phy usb2phy_reg to handle enable/disable of the 480m
> clk on these SoCs.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> v2: New patch
> ---
> drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 43 ++++++++++++++-----
> 1 file changed, 33 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> index 43f6e020a6a0..f40a86bc9dae 100644
> --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> @@ -40,11 +40,13 @@ struct rockchip_usb2phy_port_cfg {
> struct rockchip_usb2phy_cfg {
> unsigned int reg;
> struct usb2phy_reg clkout_ctl;
> + struct usb2phy_reg clkout_ctl_phy;
> const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
> };
>
> struct rockchip_usb2phy {
> struct regmap *reg_base;
> + struct regmap *phy_base;
> struct clk phyclk;
> const struct rockchip_usb2phy_cfg *phy_cfg;
> };
> @@ -165,6 +167,22 @@ static struct phy_ops rockchip_usb2phy_ops = {
> .of_xlate = rockchip_usb2phy_of_xlate,
> };
>
> +static void rockchip_usb2phy_clkout_ctl(struct clk *clk, struct regmap **base,
> + const struct usb2phy_reg **clkout_ctl)
> +{
> + struct udevice *parent = dev_get_parent(clk->dev);
> + struct rockchip_usb2phy *priv = dev_get_priv(parent);
> + const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
> +
> + if (priv->phy_cfg->clkout_ctl_phy.enable) {
> + *base = priv->phy_base;
> + *clkout_ctl = &phy_cfg->clkout_ctl_phy;
> + } else {
> + *base = priv->reg_base;
> + *clkout_ctl = &phy_cfg->clkout_ctl;
> + }
> +}
> +
> /**
> * round_rate() - Adjust a rate to the exact rate a clock can provide.
> * @clk: The clock to manipulate.
> @@ -185,13 +203,14 @@ ulong rockchip_usb2phy_clk_round_rate(struct clk *clk, ulong rate)
> */
> int rockchip_usb2phy_clk_enable(struct clk *clk)
> {
> - struct udevice *parent = dev_get_parent(clk->dev);
> - struct rockchip_usb2phy *priv = dev_get_priv(parent);
> - const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
> + const struct usb2phy_reg *clkout_ctl;
> + struct regmap *base;
> +
> + rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);
>
> /* turn on 480m clk output if it is off */
> - if (!property_enabled(priv->reg_base, &phy_cfg->clkout_ctl)) {
> - property_enable(priv->reg_base, &phy_cfg->clkout_ctl, true);
> + if (!property_enabled(base, clkout_ctl)) {
> + property_enable(base, clkout_ctl, true);
>
> /* waiting for the clk become stable */
> usleep_range(1200, 1300);
> @@ -208,12 +227,13 @@ int rockchip_usb2phy_clk_enable(struct clk *clk)
> */
> int rockchip_usb2phy_clk_disable(struct clk *clk)
> {
> - struct udevice *parent = dev_get_parent(clk->dev);
> - struct rockchip_usb2phy *priv = dev_get_priv(parent);
> - const struct rockchip_usb2phy_cfg *phy_cfg = priv->phy_cfg;
> + const struct usb2phy_reg *clkout_ctl;
> + struct regmap *base;
> +
> + rockchip_usb2phy_clkout_ctl(clk, &base, &clkout_ctl);
>
> /* turn off 480m clk output */
> - property_enable(priv->reg_base, &phy_cfg->clkout_ctl, false);
> + property_enable(base, clkout_ctl, false);
>
> return 0;
> }
> @@ -281,7 +301,10 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
> return ret;
> }
>
> - return 0;
> + if (priv->phy_cfg->clkout_ctl_phy.enable)
> + ret = regmap_init_mem_index(dev_ofnode(dev), &priv->phy_base, 0);
> +
> + return ret;
> }
>
> static int rockchip_usb2phy_bind(struct udevice *dev)
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 27/30] phy: rockchip-inno-usb2: Add support for RK3528
2025-04-07 22:47 ` [PATCH v2 27/30] phy: rockchip-inno-usb2: Add support for RK3528 Jonas Karlman
@ 2025-04-08 3:24 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:24 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot
On 2025/4/8 06:47, Jonas Karlman wrote:
> Add support for the two USB2.0 PHYs use in the RK3528 SoC.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> v2: New patch
> ---
> drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 20 +++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> index f40a86bc9dae..88b33de1b2a0 100644
> --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> @@ -412,6 +412,22 @@ static const struct rockchip_usb2phy_cfg rk3399_usb2phy_cfgs[] = {
> { /* sentinel */ }
> };
>
> +static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
> + {
> + .reg = 0xffdf0000,
> + .clkout_ctl_phy = { 0x041c, 7, 2, 0, 0x27 },
> + .port_cfgs = {
> + [USB2PHY_PORT_OTG] = {
> + .phy_sus = { 0x004c, 1, 0, 2, 1 },
> + },
> + [USB2PHY_PORT_HOST] = {
> + .phy_sus = { 0x005c, 1, 0, 2, 1 },
> + }
> + },
> + },
> + { /* sentinel */ }
> +};
> +
> static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
> {
> .reg = 0xfe8a0000,
> @@ -493,6 +509,10 @@ static const struct udevice_id rockchip_usb2phy_ids[] = {
> .compatible = "rockchip,rk3399-usb2phy",
> .data = (ulong)&rk3399_usb2phy_cfgs,
> },
> + {
> + .compatible = "rockchip,rk3528-usb2phy",
> + .data = (ulong)&rk3528_phy_cfgs,
> + },
> {
> .compatible = "rockchip,rk3568-usb2phy",
> .data = (ulong)&rk3568_phy_cfgs,
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 28/30] net: dwc_eth_qos_rockchip: Add support for RK3528
2025-04-07 22:47 ` [PATCH v2 28/30] net: dwc_eth_qos_rockchip: " Jonas Karlman
@ 2025-04-08 3:24 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:24 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini,
Joe Hershberger, Ramon Fried
Cc: Yao Zi, Chukun Pan, u-boot
On 2025/4/8 06:47, Jonas Karlman wrote:
> Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC
> Ethernet QoS IP.
>
> Add initial support for the RK3528 GMAC variant.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> v2: New patch
> ---
> drivers/net/dwc_eth_qos.c | 4 +
> drivers/net/dwc_eth_qos_rockchip.c | 138 +++++++++++++++++++++++++++++
> 2 files changed, 142 insertions(+)
>
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> index b4ec3614696e..d4561784a6ec 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -1611,6 +1611,10 @@ static const struct udevice_id eqos_ids[] = {
> },
> #endif
> #if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP)
> + {
> + .compatible = "rockchip,rk3528-gmac",
> + .data = (ulong)&eqos_rockchip_config
> + },
> {
> .compatible = "rockchip,rk3568-gmac",
> .data = (ulong)&eqos_rockchip_config
> diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c
> index f3a0f63003ea..3a9c46a01ec3 100644
> --- a/drivers/net/dwc_eth_qos_rockchip.c
> +++ b/drivers/net/dwc_eth_qos_rockchip.c
> @@ -50,6 +50,132 @@ struct rockchip_platform_data {
> (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
> ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
>
> +#define RK3528_VO_GRF_GMAC_CON 0x0018
> +#define RK3528_VPU_GRF_GMAC_CON5 0x0018
> +#define RK3528_VPU_GRF_GMAC_CON6 0x001c
> +
> +#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
> +#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
> +#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
> +#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
> +
> +#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
> +#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
> +
> +#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
> +#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
> +#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
> +
> +#define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12)
> +#define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12)
> +
> +#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3)
> +#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3)
> +#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
> +#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
> +
> +#define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
> +#define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10))
> +#define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10))
> +
> +#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
> +#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
> +#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
> +#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9)
> +
> +static int rk3528_set_to_rgmii(struct udevice *dev,
> + int tx_delay, int rx_delay)
> +{
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + struct rockchip_platform_data *data = pdata->priv_pdata;
> +
> + regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5,
> + RK3528_GMAC1_PHY_INTF_SEL_RGMII);
> +
> + regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5,
> + DELAY_ENABLE(RK3528, tx_delay, rx_delay));
> +
> + regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON6,
> + RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
> + RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
> +
> + return 0;
> +}
> +
> +static int rk3528_set_to_rmii(struct udevice *dev)
> +{
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + struct rockchip_platform_data *data = pdata->priv_pdata;
> +
> + if (data->id == 1)
> + regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5,
> + RK3528_GMAC1_PHY_INTF_SEL_RMII);
> + else
> + regmap_write(data->grf, RK3528_VO_GRF_GMAC_CON,
> + RK3528_GMAC0_PHY_INTF_SEL_RMII |
> + RK3528_GMAC0_CLK_RMII_DIV2);
> +
> + return 0;
> +}
> +
> +static int rk3528_set_gmac_speed(struct udevice *dev)
> +{
> + struct eqos_priv *eqos = dev_get_priv(dev);
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + struct rockchip_platform_data *data = pdata->priv_pdata;
> + u32 val, reg;
> +
> + switch (eqos->phy->speed) {
> + case SPEED_10:
> + if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
> + val = data->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV20 :
> + RK3528_GMAC0_CLK_RMII_DIV20;
> + else
> + val = RK3528_GMAC1_CLK_RGMII_DIV50;
> + break;
> + case SPEED_100:
> + if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
> + val = data->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV2 :
> + RK3528_GMAC0_CLK_RMII_DIV2;
> + else
> + val = RK3528_GMAC1_CLK_RGMII_DIV5;
> + break;
> + case SPEED_1000:
> + if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
> + val = RK3528_GMAC1_CLK_RGMII_DIV1;
> + else
> + return -EINVAL;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + reg = data->id == 1 ? RK3528_VPU_GRF_GMAC_CON5 :
> + RK3528_VO_GRF_GMAC_CON;
> + regmap_write(data->grf, reg, val);
> +
> + return 0;
> +}
> +
> +static void rk3528_set_clock_selection(struct udevice *dev, bool enable)
> +{
> + struct eth_pdata *pdata = dev_get_plat(dev);
> + struct rockchip_platform_data *data = pdata->priv_pdata;
> + u32 val;
> +
> + if (data->id == 1) {
> + val = data->clock_input ? RK3528_GMAC1_CLK_SELECT_IO :
> + RK3528_GMAC1_CLK_SELECT_CRU;
> + val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
> + RK3528_GMAC1_CLK_RMII_GATE;
> + regmap_write(data->grf, RK3528_VPU_GRF_GMAC_CON5, val);
> + } else {
> + val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
> + RK3528_GMAC0_CLK_RMII_GATE;
> + regmap_write(data->grf, RK3528_VO_GRF_GMAC_CON, val);
> + }
> +}
> +
> #define RK3568_GRF_GMAC0_CON0 0x0380
> #define RK3568_GRF_GMAC0_CON1 0x0384
> #define RK3568_GRF_GMAC1_CON0 0x0388
> @@ -269,6 +395,18 @@ static void rk3588_set_clock_selection(struct udevice *dev, bool enable)
> }
>
> static const struct rk_gmac_ops rk_gmac_ops[] = {
> + {
> + .compatible = "rockchip,rk3528-gmac",
> + .set_to_rgmii = rk3528_set_to_rgmii,
> + .set_to_rmii = rk3528_set_to_rmii,
> + .set_gmac_speed = rk3528_set_gmac_speed,
> + .set_clock_selection = rk3528_set_clock_selection,
> + .regs = {
> + 0xffbd0000, /* gmac0 */
> + 0xffbe0000, /* gmac1 */
> + 0x0, /* sentinel */
> + },
> + },
> {
> .compatible = "rockchip,rk3568-gmac",
> .set_to_rgmii = rk3568_set_to_rgmii,
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 29/30] board: rockchip: Add minimal generic RK3528 board
2025-04-07 22:47 ` [PATCH v2 29/30] board: rockchip: Add minimal generic RK3528 board Jonas Karlman
@ 2025-04-08 3:24 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:24 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot
On 2025/4/8 06:47, Jonas Karlman wrote:
> Add a minimal generic RK3528 board that only have eMMC and SD-card
> enabled. This defconfig can be used to boot from eMMC or SD-card on most
> RK3528 boards that follow reference board design.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> Changes in v2:
> - Move sdhci node to main .dts-file
> - Enable meminfo cmd
>
> Tested on:
> - FriendlyElec NanoPi Zero2
> - Radxa ROCK 2A
> - Radxa ROCK 2F
> ---
> arch/arm/dts/rk3528-generic-u-boot.dtsi | 12 +++++++
> arch/arm/dts/rk3528-generic.dts | 31 ++++++++++++++++++
> arch/arm/mach-rockchip/rk3528/MAINTAINERS | 5 +++
> configs/generic-rk3528_defconfig | 40 +++++++++++++++++++++++
> doc/board/rockchip/rockchip.rst | 12 +++++++
> 5 files changed, 100 insertions(+)
> create mode 100644 arch/arm/dts/rk3528-generic-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3528-generic.dts
> create mode 100644 arch/arm/mach-rockchip/rk3528/MAINTAINERS
> create mode 100644 configs/generic-rk3528_defconfig
>
> diff --git a/arch/arm/dts/rk3528-generic-u-boot.dtsi b/arch/arm/dts/rk3528-generic-u-boot.dtsi
> new file mode 100644
> index 000000000000..cc830b514567
> --- /dev/null
> +++ b/arch/arm/dts/rk3528-generic-u-boot.dtsi
> @@ -0,0 +1,12 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +#include "rk3528-u-boot.dtsi"
> +
> +&sdmmc {
> + bus-width = <4>;
> + cap-sd-highspeed;
> + disable-wp;
> + no-mmc;
> + no-sdio;
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts
> new file mode 100644
> index 000000000000..792d3e04a4cb
> --- /dev/null
> +++ b/arch/arm/dts/rk3528-generic.dts
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Minimal generic DT for RK3528 with eMMC enabled
> + */
> +
> +/dts-v1/;
> +#include "rk3528.dtsi"
> +
> +/ {
> + model = "Generic RK3528";
> + compatible = "rockchip,rk3528";
> +
> + chosen {
> + stdout-path = "serial0:1500000n8";
> + };
> +};
> +
> +&sdhci {
> + bus-width = <8>;
> + cap-mmc-highspeed;
> + no-sd;
> + no-sdio;
> + non-removable;
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0m0_xfer>;
> + status = "okay";
> +};
> diff --git a/arch/arm/mach-rockchip/rk3528/MAINTAINERS b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
> new file mode 100644
> index 000000000000..cfdc92d770c1
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
> @@ -0,0 +1,5 @@
> +GENERIC-RK3528
> +M: Jonas Karlman <jonas@kwiboo.se>
> +S: Maintained
> +F: arch/arm/dts/rk3528-generic*
> +F: configs/generic-rk3528_defconfig
> diff --git a/configs/generic-rk3528_defconfig b/configs/generic-rk3528_defconfig
> new file mode 100644
> index 000000000000..e19c7bc4801d
> --- /dev/null
> +++ b/configs/generic-rk3528_defconfig
> @@ -0,0 +1,40 @@
> +CONFIG_ARM=y
> +CONFIG_SKIP_LOWLEVEL_INIT=y
> +CONFIG_COUNTER_FREQUENCY=24000000
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_DEFAULT_DEVICE_TREE="rk3528-generic"
> +CONFIG_ROCKCHIP_RK3528=y
> +CONFIG_SYS_LOAD_ADDR=0xc00800
> +CONFIG_DEBUG_UART_BASE=0xFF9F0000
> +CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_DEBUG_UART=y
> +# CONFIG_BOOTMETH_VBE is not set
> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-generic.dtb"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_SPL_MAX_SIZE=0x40000
> +CONFIG_SPL_PAD_TO=0x7f8000
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +CONFIG_CMD_MEMINFO=y
> +CONFIG_CMD_MEMINFO_MAP=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_MISC=y
> +CONFIG_CMD_MMC=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_RNG=y
> +# CONFIG_SPL_DOS_PARTITION is not set
> +# CONFIG_OF_UPSTREAM is not set
> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> +CONFIG_NO_NET=y
> +# CONFIG_ADC is not set
> +CONFIG_ROCKCHIP_GPIO=y
> +CONFIG_SUPPORT_EMMC_RPMB=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_SDMA=y
> +CONFIG_MMC_SDHCI_ROCKCHIP=y
> +CONFIG_BAUDRATE=1500000
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_SYS_NS16550_MEM32=y
> +CONFIG_ERRNO_STR=y
> diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
> index 5a029afae305..c636d33b47c1 100644
> --- a/doc/board/rockchip/rockchip.rst
> +++ b/doc/board/rockchip/rockchip.rst
> @@ -99,6 +99,9 @@ List of mainline supported Rockchip boards:
> - Rockchip Evb-RK3399 (evb_rk3399)
> - Theobroma Systems RK3399-Q7 SoM - Puma (puma_rk3399)
>
> +* rk3528
> + - Generic RK3528 (generic-rk3528)
> +
> * rk3566
> - Anbernic RGxx3 (anbernic-rgxx3-rk3566)
> - FriendlyElec NanoPi R3S (nanopi-r3s-rk3566)
> @@ -260,6 +263,15 @@ To build rk3399 boards:
> make evb-rk3399_defconfig
> make CROSS_COMPILE=aarch64-linux-gnu-
>
> +To build rk3528 boards:
> +
> +.. code-block:: bash
> +
> + export BL31=../rkbin/bin/rk35/rk3528_bl31_v1.18.elf
> + export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3528_ddr_1056MHz_v1.10.bin
> + make generic-rk3528_defconfig
> + make CROSS_COMPILE=aarch64-linux-gnu-
> +
> To build rk3568 boards:
>
> .. code-block:: bash
^ permalink raw reply [flat|nested] 61+ messages in thread
* Re: [PATCH v2 30/30] board: rockchip: Add Radxa E20C
2025-04-07 22:47 ` [PATCH v2 30/30] board: rockchip: Add Radxa E20C Jonas Karlman
@ 2025-04-08 3:25 ` Kever Yang
0 siblings, 0 replies; 61+ messages in thread
From: Kever Yang @ 2025-04-08 3:25 UTC (permalink / raw)
To: Jonas Karlman, Simon Glass, Philipp Tomsich, Tom Rini
Cc: Yao Zi, Chukun Pan, u-boot
On 2025/4/8 06:47, Jonas Karlman wrote:
> The Radxa E20C is an ultra-compact network computer with a RK3528A SoC
> that offers a wide range of networking capabilities.
>
> Features tested on a Radxa E20C v1.104:
> - SD-card boot
> - eMMC boot
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> Changes in v2:
> - Drop sdhci from board u-boot.dtsi
> - Update sdmmc node to latest mainline Linux patch
> - Enable options for DT nodes added to dts/upstream DT
>
> This also enables options for GMAC, PWM-regulators and USB 2.0. Features
> that have been tested but are currently missing the necessary DT nodes.
> ---
> arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi | 12 +++++
> arch/arm/mach-rockchip/rk3528/MAINTAINERS | 6 +++
> configs/radxa-e20c-rk3528_defconfig | 56 ++++++++++++++++++++++
> doc/board/rockchip/rockchip.rst | 1 +
> 4 files changed, 75 insertions(+)
> create mode 100644 arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
> create mode 100644 configs/radxa-e20c-rk3528_defconfig
>
> diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
> new file mode 100644
> index 000000000000..9c2f03a786cf
> --- /dev/null
> +++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi
> @@ -0,0 +1,12 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +#include "rk3528-u-boot.dtsi"
> +
> +&sdmmc {
> + bus-width = <4>;
> + cap-mmc-highspeed;
> + cap-sd-highspeed;
> + disable-wp;
> + vmmc-supply = <&vcc_3v3>;
> + status = "okay";
> +};
> diff --git a/arch/arm/mach-rockchip/rk3528/MAINTAINERS b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
> index cfdc92d770c1..f343f71cf7f6 100644
> --- a/arch/arm/mach-rockchip/rk3528/MAINTAINERS
> +++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS
> @@ -3,3 +3,9 @@ M: Jonas Karlman <jonas@kwiboo.se>
> S: Maintained
> F: arch/arm/dts/rk3528-generic*
> F: configs/generic-rk3528_defconfig
> +
> +RADXA-E20C
> +M: Jonas Karlman <jonas@kwiboo.se>
> +S: Maintained
> +F: arch/arm/dts/rk3528-radxa-e20c*
> +F: configs/radxa-e20c-rk3528_defconfig
> diff --git a/configs/radxa-e20c-rk3528_defconfig b/configs/radxa-e20c-rk3528_defconfig
> new file mode 100644
> index 000000000000..08f3a13af3b2
> --- /dev/null
> +++ b/configs/radxa-e20c-rk3528_defconfig
> @@ -0,0 +1,56 @@
> +CONFIG_ARM=y
> +CONFIG_SKIP_LOWLEVEL_INIT=y
> +CONFIG_COUNTER_FREQUENCY=24000000
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3528-radxa-e20c"
> +CONFIG_ROCKCHIP_RK3528=y
> +CONFIG_SYS_LOAD_ADDR=0xc00800
> +CONFIG_DEBUG_UART_BASE=0xFF9F0000
> +CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_DEBUG_UART=y
> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3528-radxa-e20c.dtb"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_SPL_MAX_SIZE=0x40000
> +CONFIG_SPL_PAD_TO=0x7f8000
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +CONFIG_CMD_MEMINFO=y
> +CONFIG_CMD_MEMINFO_MAP=y
> +CONFIG_CMD_ADC=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_MISC=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_USB=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_RNG=y
> +CONFIG_CMD_REGULATOR=y
> +# CONFIG_SPL_DOS_PARTITION is not set
> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> +CONFIG_BUTTON=y
> +CONFIG_BUTTON_ADC=y
> +CONFIG_BUTTON_GPIO=y
> +CONFIG_ROCKCHIP_GPIO=y
> +CONFIG_LED=y
> +CONFIG_LED_GPIO=y
> +CONFIG_SUPPORT_EMMC_RPMB=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_SDMA=y
> +CONFIG_MMC_SDHCI_ROCKCHIP=y
> +CONFIG_PHY_MOTORCOMM=y
> +CONFIG_PHY_REALTEK=y
> +CONFIG_DM_MDIO=y
> +CONFIG_DWC_ETH_QOS=y
> +CONFIG_DWC_ETH_QOS_ROCKCHIP=y
> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_REGULATOR_PWM=y
> +CONFIG_DM_REGULATOR_GPIO=y
> +CONFIG_PWM_ROCKCHIP=y
> +CONFIG_BAUDRATE=1500000
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_SYS_NS16550_MEM32=y
> +CONFIG_USB=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_ERRNO_STR=y
> diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
> index c636d33b47c1..f7d4f2a66860 100644
> --- a/doc/board/rockchip/rockchip.rst
> +++ b/doc/board/rockchip/rockchip.rst
> @@ -101,6 +101,7 @@ List of mainline supported Rockchip boards:
>
> * rk3528
> - Generic RK3528 (generic-rk3528)
> + - Radxa E20C (radxa-e20c-rk3528)
>
> * rk3566
> - Anbernic RGxx3 (anbernic-rgxx3-rk3566)
^ permalink raw reply [flat|nested] 61+ messages in thread
end of thread, other threads:[~2025-04-08 3:26 UTC | newest]
Thread overview: 61+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-04-07 22:46 [PATCH v2 00/30] rockchip: Add initial support for RK3528 Jonas Karlman
2025-04-07 22:46 ` [PATCH v2 01/30] dt-bindings: clock: Document clock and reset unit of RK3528 Jonas Karlman
2025-04-08 3:21 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 02/30] arm64: dts: rockchip: Add clock generators for RK3528 SoC Jonas Karlman
2025-04-08 3:21 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 03/30] arm64: dts: rockchip: Add UART clocks " Jonas Karlman
2025-04-08 3:21 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 04/30] arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528 Jonas Karlman
2025-04-08 3:21 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 05/30] arm64: dts: rockchip: Add rk3528 QoS register node Jonas Karlman
2025-04-08 3:21 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 06/30] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC Jonas Karlman
2025-04-08 3:21 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 07/30] arm64: dts: rockchip: Add SARADC node for RK3528 Jonas Karlman
2025-04-08 3:21 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 08/30] arm64: dts: rockchip: Add SDHCI controller " Jonas Karlman
2025-04-08 3:21 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 09/30] arm64: dts: rockchip: Add uart0 pinctrl to Radxa E20C Jonas Karlman
2025-04-08 3:22 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 10/30] arm64: dts: rockchip: Add leds node " Jonas Karlman
2025-04-08 3:22 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 11/30] arm64: dts: rockchip: Add user button " Jonas Karlman
2025-04-08 3:22 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 12/30] arm64: dts: rockchip: Add maskrom " Jonas Karlman
2025-04-08 3:22 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 13/30] arm64: dts: rockchip: Enable onboard eMMC on " Jonas Karlman
2025-04-08 3:22 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 14/30] rockchip: mkimage: Add support for RK3528 Jonas Karlman
2025-04-08 3:22 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 15/30] ram: rockchip: Add basic " Jonas Karlman
2025-04-08 3:22 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 16/30] clk: rockchip: Add " Jonas Karlman
2025-04-08 3:23 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 17/30] pinctrl: " Jonas Karlman
2025-04-08 3:23 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 18/30] arm: dts: rockchip: Add rk3528-u-boot.dtsi Jonas Karlman
2025-04-08 3:23 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 19/30] arch: arm: rockchip: Add initial support for RK3528 Jonas Karlman
2025-04-08 3:23 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 20/30] mmc: rockchip_sdhci: Extend variant configuration Jonas Karlman
2025-04-08 3:23 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 21/30] mmc: rockchip_sdhci: Add initial support for RK3528 Jonas Karlman
2025-04-08 3:23 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 22/30] mmc: rockchip_sdhci: Gate clock for glitch free phase switching Jonas Karlman
2025-04-08 3:23 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 23/30] rockchip: otp: Add support for RK3528 Jonas Karlman
2025-04-08 3:23 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 24/30] adc: rockchip-saradc: " Jonas Karlman
2025-04-08 3:24 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 25/30] rng: rockchip: Add support for rkrng variant Jonas Karlman
2025-04-08 3:24 ` Kever Yang
2025-04-07 22:46 ` [PATCH v2 26/30] phy: rockchip-inno-usb2: Add support for clkout_ctl_phy Jonas Karlman
2025-04-08 3:24 ` Kever Yang
2025-04-07 22:47 ` [PATCH v2 27/30] phy: rockchip-inno-usb2: Add support for RK3528 Jonas Karlman
2025-04-08 3:24 ` Kever Yang
2025-04-07 22:47 ` [PATCH v2 28/30] net: dwc_eth_qos_rockchip: " Jonas Karlman
2025-04-08 3:24 ` Kever Yang
2025-04-07 22:47 ` [PATCH v2 29/30] board: rockchip: Add minimal generic RK3528 board Jonas Karlman
2025-04-08 3:24 ` Kever Yang
2025-04-07 22:47 ` [PATCH v2 30/30] board: rockchip: Add Radxa E20C Jonas Karlman
2025-04-08 3:25 ` Kever Yang
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