[PATCH 0/2] zynqmp parallel memories support for Infineon Flash

[PATCH 0/2] zynqmp parallel memories support for Infineon Flash

[tkuw584924]

From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>

Some of Infineon SPI-NOR chips use vendor or device specific commands
which we need to take care for parallel memories configuration in zynqmp.

Tested with Infineon S25HS02GT flash and AMD EK-VMK180 board.

Takahiro Kuwano (2):
  spi: zynqmp_gqspi: Make WR_ANY_REG opcode not use striped access
  mtd: spi-nor-core: Rework spansion_sr_ready() for parallel memories
    support

 drivers/mtd/spi/spi-nor-core.c | 37 ++++++++++++++++++++++++++++++++--
 drivers/spi/zynqmp_gqspi.c     |  2 ++
 2 files changed, 37 insertions(+), 2 deletions(-)

-- 
2.34.1

[PATCH 1/2] spi: zynqmp_gqspi: Make WR_ANY_REG opcode not use striped access

[tkuw584924]

From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>

SPINOR_OP_WR_ANY_REG (0x71) opcode must not be performed in striped
access mode to write the same register value to two Flash devices in
parallel memory configuration. The opcde 0x71 is also used as Read
Configuration Register-2 (SPINOR_OP_RD_CR2). To distiguish it, data
direction needs to be checked.

The following commit is related to this patch.
217b0a28b6d ("spi: zynqmp_gqspi: Add parallel memories support in GQSPI driver")

Tested-by: Hiroyuki Saito <Hiroyuki.Saito2@infineon.com> 
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
---
 drivers/spi/zynqmp_gqspi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 2a095d0c58e..f47c3058942 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -841,6 +841,8 @@ static bool zynqmp_qspi_update_stripe(const struct spi_mem_op *op)
 		return false;
 	case SPINOR_OP_WRSR2:
 		return op->addr.nbytes != 0;
+	case SPINOR_OP_WR_ANY_REG:
+		return op->data.dir != SPI_MEM_DATA_OUT;
 	default:
 		return true;
 	}
-- 
2.34.1

[PATCH 2/2] mtd: spi-nor-core: Rework spansion_sr_ready() for parallel memories support

[tkuw584924]

From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>

spansion_sr_ready() needs to support parallel memories configuration,
that reads status register value from each devices and combines the
status bits, likewise read_sr() and read_fsr().

Introduce helper functions that perform RD_ANY_REG op with one-byte or
two-byte data length. And spansion_sr_ready() calls one of them
depending on HAS_PARALLEL flag.

The following commit is related to this patch.
92e0ae42b47 ("mtd: spi-nor: Add parallel memories support for read_sr and read_fsr")

Tested-by: Hiroyuki Saito <Hiroyuki.Saito2@infineon.com>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
---
 drivers/mtd/spi/spi-nor-core.c | 37 ++++++++++++++++++++++++++++++++--
 1 file changed, 35 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 6f352c5c0e2..c792a00e4bf 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -796,13 +796,46 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
  * Read status register 1 by using Read Any Register command to support multi
  * die package parts.
  */
+static int spansion_read_sr(struct spi_nor *nor, u32 addr_base, u8 dummy,
+			    u8 *sr)
+{
+	return spansion_read_any_reg(nor, addr_base + SPINOR_REG_CYPRESS_STR1V,
+				     dummy, sr);
+}
+
+static int spansion_read_sr_parallel(struct spi_nor *nor, u32 addr_base,
+				     u8 dummy, u8 *sr)
+{
+	struct spi_mem_op op =
+		SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 0),
+			   SPI_MEM_OP_ADDR(nor->addr_mode_nbytes, 0, 0),
+			   SPI_MEM_OP_DUMMY(dummy, 0),
+			   SPI_MEM_OP_DATA_IN(2, NULL, 0));
+	u8 buf[2];
+	int ret;
+
+	op.addr.val = addr_base + SPINOR_REG_CYPRESS_STR1V;
+	spi_nor_setup_op(nor, &op, nor->reg_proto);
+
+	ret = spi_nor_read_write_reg(nor, &op, buf);
+	if (ret)
+		return ret;
+
+	*sr = buf[0] | buf[1];
+
+	return 0;
+}
+
 static int spansion_sr_ready(struct spi_nor *nor, u32 addr_base, u8 dummy)
 {
-	u32 reg_addr = addr_base + SPINOR_REG_CYPRESS_STR1V;
 	u8 sr;
 	int ret;
 
-	ret = spansion_read_any_reg(nor, reg_addr, dummy, &sr);
+	if (nor->flags & SNOR_F_HAS_PARALLEL)
+		ret = spansion_read_sr_parallel(nor, addr_base, dummy, &sr);
+	else
+		ret = spansion_read_sr(nor, addr_base, dummy, &sr);
+
 	if (ret < 0)
 		return ret;
 
-- 
2.34.1

Re: [PATCH 2/2] mtd: spi-nor-core: Rework spansion_sr_ready() for parallel memories support

[Tudor Ambarus]

+ Marek,

Hi,

On 3/14/25 5:53 AM, tkuw584924@gmail.com wrote:
> spansion_sr_ready() needs to support parallel memories configuration,
> that reads status register value from each devices and combines the
> status bits, likewise read_sr() and read_fsr().

SNOR_F_HAS_PARALLEL describes 2 flashes that work in parallel mode. And
we hacked SPI NOR and used a single spi_nor object to handle both
flashes which is obviously wrong.

My 2c is that we shouldn't build on top of a crumbling foundation. Until
everything's moved on top of SPI NOR, I'd accept just fixes on this
subject, so no new support. Tom and Jagan to decide.

Cheers,
ta

Re: [PATCH 2/2] mtd: spi-nor-core: Rework spansion_sr_ready() for parallel memories support

[Tom Rini]

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On Fri, Mar 14, 2025 at 07:40:17AM +0000, Tudor Ambarus wrote:
> + Marek,
> 
> Hi,
> 
> On 3/14/25 5:53 AM, tkuw584924@gmail.com wrote:
> > spansion_sr_ready() needs to support parallel memories configuration,
> > that reads status register value from each devices and combines the
> > status bits, likewise read_sr() and read_fsr().
> 
> SNOR_F_HAS_PARALLEL describes 2 flashes that work in parallel mode. And
> we hacked SPI NOR and used a single spi_nor object to handle both
> flashes which is obviously wrong.
> 
> My 2c is that we shouldn't build on top of a crumbling foundation. Until
> everything's moved on top of SPI NOR, I'd accept just fixes on this
> subject, so no new support. Tom and Jagan to decide.

Yes, I believe I was expecting some patches to redo / rework what we
have in-tree currently.

-- 
Tom

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Re: [PATCH 2/2] mtd: spi-nor-core: Rework spansion_sr_ready() for parallel memories support

[Takahiro Kuwano]

On 3/14/2025 11:54 PM, Tom Rini wrote:
> On Fri, Mar 14, 2025 at 07:40:17AM +0000, Tudor Ambarus wrote:
>> + Marek,
>>
>> Hi,
>>
>> On 3/14/25 5:53 AM, tkuw584924@gmail.com wrote:
>>> spansion_sr_ready() needs to support parallel memories configuration,
>>> that reads status register value from each devices and combines the
>>> status bits, likewise read_sr() and read_fsr().
>>
>> SNOR_F_HAS_PARALLEL describes 2 flashes that work in parallel mode. And
>> we hacked SPI NOR and used a single spi_nor object to handle both
>> flashes which is obviously wrong.
>>
>> My 2c is that we shouldn't build on top of a crumbling foundation. Until
>> everything's moved on top of SPI NOR, I'd accept just fixes on this
>> subject, so no new support. Tom and Jagan to decide.
> 
> Yes, I believe I was expecting some patches to redo / rework what we
> have in-tree currently.
> 
Understood our current position and status, thanks!

Takahiro