[Qemu-arm] [PATCH 1/2] usb/ehci: Add SysBus EHCI device for Allwinner SoCs

[Qemu-arm] [PATCH 1/2] usb/ehci: Add SysBus EHCI device for Allwinner SoCs

[Icenowy Zheng]

It uses a register map like the one in Exynos SoCs.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 hw/usb/hcd-ehci-sysbus.c | 17 +++++++++++++++++
 hw/usb/hcd-ehci.h        |  1 +
 2 files changed, 18 insertions(+)

diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
index 6c20604d07..d99bb4abe7 100644
--- a/hw/usb/hcd-ehci-sysbus.c
+++ b/hw/usb/hcd-ehci-sysbus.c
@@ -218,6 +218,22 @@ static const TypeInfo ehci_fusbh200_type_info = {
     .class_init    = fusbh200_ehci_class_init,
 };
 
+static void ehci_allwinner_class_init(ObjectClass *oc, void *data)
+{
+    SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    sec->capsbase = 0x0;
+    sec->opregbase = 0x10;
+    set_bit(DEVICE_CATEGORY_USB, dc->categories);
+}
+
+static const TypeInfo ehci_allwinner_type_info = {
+    .name          = TYPE_ALLWINNER_EHCI,
+    .parent        = TYPE_SYS_BUS_EHCI,
+    .class_init    = ehci_allwinner_class_init,
+};
+
 static void ehci_sysbus_register_types(void)
 {
     type_register_static(&ehci_type_info);
@@ -225,6 +241,7 @@ static void ehci_sysbus_register_types(void)
     type_register_static(&ehci_exynos4210_type_info);
     type_register_static(&ehci_tegra2_type_info);
     type_register_static(&ehci_fusbh200_type_info);
+    type_register_static(&ehci_allwinner_type_info);
 }
 
 type_init(ehci_sysbus_register_types)
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
index 3fd7038658..89f3c7d922 100644
--- a/hw/usb/hcd-ehci.h
+++ b/hw/usb/hcd-ehci.h
@@ -343,6 +343,7 @@ typedef struct EHCIPCIState {
 #define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
 #define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
 #define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
+#define TYPE_ALLWINNER_EHCI "allwinner-ehci-usb"
 
 #define SYS_BUS_EHCI(obj) \
     OBJECT_CHECK(EHCISysBusState, (obj), TYPE_SYS_BUS_EHCI)
-- 
2.11.0

[Qemu-arm] [PATCH 2/2] arm: allwinner-a10: Add OHCI/EHCI

[Icenowy Zheng]

Add the Allwinner OHCI/EHCI controller modules to the SoC.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 hw/arm/allwinner-a10.c         | 6 ++++++
 include/hw/arm/allwinner-a10.h | 5 +++++
 2 files changed, 11 insertions(+)

diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index ca15d1c8cc..e3417ca2cf 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -46,6 +46,12 @@ static void aw_a10_init(Object *obj)
 
     object_initialize(&s->sata, sizeof(s->sata), TYPE_ALLWINNER_AHCI);
     qdev_set_parent_bus(DEVICE(&s->sata), sysbus_get_default());
+
+    sysbus_create_simple(TYPE_ALLWINNER_EHCI, AW_A10_EHCI0_BASE, s->irq[39]);
+    sysbus_create_simple(TYPE_ALLWINNER_EHCI, AW_A10_EHCI1_BASE, s->irq[40]);
+
+    sysbus_create_simple("sysbus-ohci", AW_A10_OHCI0_BASE, s->irq[64]);
+    sysbus_create_simple("sysbus-ohci", AW_A10_OHCI1_BASE, s->irq[65]);
 }
 
 static void aw_a10_realize(DeviceState *dev, Error **errp)
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index 6b32a99e21..1ea5f18b51 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -9,6 +9,7 @@
 #include "hw/net/allwinner_emac.h"
 #include "hw/ide/pci.h"
 #include "hw/ide/ahci.h"
+#include "hw/usb/hcd-ehci.h"
 
 #include "sysemu/sysemu.h"
 #include "exec/address-spaces.h"
@@ -19,6 +20,10 @@
 #define AW_A10_UART0_REG_BASE   0x01c28000
 #define AW_A10_EMAC_BASE        0x01c0b000
 #define AW_A10_SATA_BASE        0x01c18000
+#define AW_A10_EHCI0_BASE	0x01c14000
+#define AW_A10_EHCI1_BASE	0x01c1c000
+#define AW_A10_OHCI0_BASE	0x01c14400
+#define AW_A10_OHCI1_BASE	0x01c1c400
 
 #define AW_A10_SDRAM_BASE       0x40000000
 
-- 
2.11.0

Re: [Qemu-arm] [PATCH 1/2] usb/ehci: Add SysBus EHCI device for Allwinner SoCs

[Gerd Hoffmann]

On So, 2017-01-29 at 09:00 +0800, Icenowy Zheng wrote:
> It uses a register map like the one in Exynos SoCs.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>

I guess this goes through the arm queue?

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>

cheers,
  Gerd

Re: [Qemu-arm] [PATCH 1/2] usb/ehci: Add SysBus EHCI device for Allwinner SoCs

[Icenowy Zheng]

2017年1月30日 16:19于 Gerd Hoffmann <kraxel@redhat.com>写道：
>
> On So, 2017-01-29 at 09:00 +0800, Icenowy Zheng wrote: 
> > It uses a register map like the one in Exynos SoCs. 
> > 
> > Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> 
>
> I guess this goes through the arm queue? 

I don't know about the QEMU development process, sorry.

>
> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> 
>
> cheers, 
>   Gerd 
>

Re: [Qemu-arm] [PATCH 1/2] usb/ehci: Add SysBus EHCI device for Allwinner SoCs

[Gerd Hoffmann]

On Mo, 2017-01-30 at 21:59 +0800, Icenowy Zheng wrote:
> 2017年1月30日 16:19于 Gerd Hoffmann <kraxel@redhat.com>写道：
> >
> > On So, 2017-01-29 at 09:00 +0800, Icenowy Zheng wrote: 
> > > It uses a register map like the one in Exynos SoCs. 
> > > 
> > > Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> 
> >
> > I guess this goes through the arm queue? 
> 
> I don't know about the QEMU development process, sorry.

The question was for Peter who maintains the arm queue.

And as patch 2/2 (which clearly belongs to arm) depends on 1/2 it is
easier to just take both through the same queue even though 2/2 is a usb
patch.

cheers,
  Gerd