From: Arnd Bergmann <arnd@arndb.de>
To: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: linux-arm-kernel@lists.infradead.org,
Jingoo Han <jg1.han@samsung.com>,
"'Thomas Petazzoni'" <thomas.petazzoni@free-electrons.com>,
linux-samsung-soc@vger.kernel.org,
"'Siva Reddy Kallam'" <siva.kallam@samsung.com>,
"'Surendranath Gurivireddy Balla'" <suren.reddy@samsung.com>,
linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org,
"'Thierry Reding'" <thierry.reding@avionic-design.de>,
linux-kernel@vger.kernel.org,
"'Grant Likely'" <grant.likely@secretlab.ca>,
"'Kukjin Kim'" <kgene.kim@samsung.com>,
"'Thomas Abraham'" <thomas.abraham@linaro.org>,
"'Bjorn Helgaas'" <bhelgaas@google.com>,
"'Andrew Murray'" <andrew.murray@arm.com>
Subject: Re: [PATCH 6/6] ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC
Date: Fri, 7 Jun 2013 19:43:18 +0200 [thread overview]
Message-ID: <201306071943.18407.arnd@arndb.de> (raw)
In-Reply-To: <20130607162050.GA31895@obsidianresearch.com>
On Friday 07 June 2013, Jason Gunthorpe wrote:
> Sounds fair to me.
>
> But when we talk about multiple domains we don't mean a disjoint range
> bus bus numbers, as your other email shows:
>
> 00:00.0 PCI bridge: Samsung Electronics Co Ltd Device a549 (rev 01) (prog-if 00 [Normal decode])
> 10:00.0 PCI bridge: Samsung Electronics Co Ltd Device a549 (rev 01) (prog-if 00 [Normal decode])
>
> We mean multiple domains, it should look like this:
>
> 0000:00:00.0 PCI bridge: Samsung Electronics Co Ltd Device a549 (rev 01) (prog-if 00 [Normal decode])
> 0001:00:00.0 PCI bridge: Samsung Electronics Co Ltd Device a549 (rev 01) (prog-if 00 [Normal decode])
>
> ie lspci -D.
>
> Each domain gets a unique bus number range, config space, io range,
> etc. This is much clearer to everyone than trying to pretend there is
> only one domain when the HW is actually multi-domain.
Yes, absolutely. This means we also don't need a bus-range property in DT, since each
domain will allow all 255 buses.
Arnd
WARNING: multiple messages have this Message-ID (diff)
From: arnd@arndb.de (Arnd Bergmann)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 6/6] ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC
Date: Fri, 7 Jun 2013 19:43:18 +0200 [thread overview]
Message-ID: <201306071943.18407.arnd@arndb.de> (raw)
In-Reply-To: <20130607162050.GA31895@obsidianresearch.com>
On Friday 07 June 2013, Jason Gunthorpe wrote:
> Sounds fair to me.
>
> But when we talk about multiple domains we don't mean a disjoint range
> bus bus numbers, as your other email shows:
>
> 00:00.0 PCI bridge: Samsung Electronics Co Ltd Device a549 (rev 01) (prog-if 00 [Normal decode])
> 10:00.0 PCI bridge: Samsung Electronics Co Ltd Device a549 (rev 01) (prog-if 00 [Normal decode])
>
> We mean multiple domains, it should look like this:
>
> 0000:00:00.0 PCI bridge: Samsung Electronics Co Ltd Device a549 (rev 01) (prog-if 00 [Normal decode])
> 0001:00:00.0 PCI bridge: Samsung Electronics Co Ltd Device a549 (rev 01) (prog-if 00 [Normal decode])
>
> ie lspci -D.
>
> Each domain gets a unique bus number range, config space, io range,
> etc. This is much clearer to everyone than trying to pretend there is
> only one domain when the HW is actually multi-domain.
Yes, absolutely. This means we also don't need a bus-range property in DT, since each
domain will allow all 255 buses.
Arnd
next prev parent reply other threads:[~2013-06-07 17:43 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-03-23 4:04 [PATCH 1/6] of/pci: Provide support for parsing PCI DT ranges property Jingoo Han
2013-03-23 4:04 ` Jingoo Han
2013-03-23 4:05 ` [PATCH 2/6] of/pci: Add of_pci_parse_bus_range() function Jingoo Han
2013-03-23 4:05 ` Jingoo Han
2013-03-23 4:05 ` Jingoo Han
2013-03-23 4:06 ` [PATCH 3/6] pci: infrastructure to add drivers in drivers/pci/host Jingoo Han
2013-03-23 4:06 ` Jingoo Han
2013-03-23 4:07 ` [PATCH 4/6] pci: Add PCIe driver for Samsung Exynos Jingoo Han
2013-03-23 4:07 ` Jingoo Han
2013-03-23 4:07 ` Jingoo Han
2013-03-26 21:33 ` Rob Herring
2013-03-26 21:33 ` Rob Herring
2013-03-27 1:29 ` Jingoo Han
2013-03-27 1:29 ` Jingoo Han
2013-03-23 4:08 ` [PATCH 5/6] ARM: EXYNOS: Enable PCIe support for Exynos5440 Jingoo Han
2013-03-23 4:08 ` Jingoo Han
2013-03-23 4:09 ` [PATCH 6/6] ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC Jingoo Han
2013-03-23 4:09 ` Jingoo Han
2013-03-25 17:04 ` Jason Gunthorpe
2013-03-25 17:04 ` Jason Gunthorpe
2013-03-27 8:35 ` Jingoo Han
2013-03-27 8:35 ` Jingoo Han
2013-03-27 8:35 ` Jingoo Han
2013-03-27 16:13 ` Jason Gunthorpe
2013-03-27 16:13 ` Jason Gunthorpe
2013-04-08 9:08 ` Jingoo Han
2013-04-08 9:08 ` Jingoo Han
2013-04-08 9:08 ` Jingoo Han
2013-04-08 16:56 ` Jason Gunthorpe
2013-04-08 16:56 ` Jason Gunthorpe
2013-06-07 9:19 ` Jingoo Han
2013-06-07 9:19 ` Jingoo Han
2013-06-07 11:59 ` Arnd Bergmann
2013-06-07 11:59 ` Arnd Bergmann
2013-06-07 16:20 ` Jason Gunthorpe
2013-06-07 16:20 ` Jason Gunthorpe
2013-06-07 17:43 ` Arnd Bergmann [this message]
2013-06-07 17:43 ` Arnd Bergmann
2013-06-10 8:38 ` Jingoo Han
2013-06-10 8:38 ` Jingoo Han
2013-06-10 15:22 ` Arnd Bergmann
2013-06-10 15:22 ` Arnd Bergmann
2013-06-11 6:00 ` Jingoo Han
2013-06-11 6:00 ` Jingoo Han
2013-06-12 15:10 ` Arnd Bergmann
2013-06-12 15:10 ` Arnd Bergmann
2013-03-23 10:41 ` [PATCH 1/6] of/pci: Provide support for parsing PCI DT ranges property Russell King - ARM Linux
2013-03-23 10:41 ` Russell King - ARM Linux
2013-03-23 13:37 ` Thomas Petazzoni
2013-03-23 13:37 ` Thomas Petazzoni
2013-03-25 10:21 ` Andrew Murray
2013-03-25 10:21 ` Andrew Murray
2013-03-25 10:21 ` Andrew Murray
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