From: arnd@arndb.de (Arnd Bergmann)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/4] ARM: STi: add stid127 soc support
Date: Thu, 30 Jan 2014 19:39:08 +0100 [thread overview]
Message-ID: <201401301939.08302.arnd@arndb.de> (raw)
In-Reply-To: <201401301935.16463.arnd@arndb.de>
On Thursday 30 January 2014, Arnd Bergmann wrote:
> On Thursday 30 January 2014, Patrice CHOTARD wrote:
> > From: Alexandre TORGUE <alexandre.torgue@st.com>
> >
> > This patch adds support to STiD127 SoC.
> > The main adaptation is the L2 cache way size compare to STiH41x SoCs.
> >
> > Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
> > Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> > ---
> > arch/arm/mach-sti/board-dt.c | 6 ++++++
> > 1 file changed, 6 insertions(+)
>
> Wouldn't it be better to read this value from the l2 cache
> controller node? I'd assume there might be more SoCs that
> will need a similar change, so it's better to come up with
> a solution that doesn't involve changing the kernel every
> time.
Actually reading the code in this file shows that the L2 cache
initialization is the only nonstandard thing in there. We should
really find a way to get rid of the entire function.
Sorry if I missed the initial review, but can you explain
why this is needed to start with?
Arnd
WARNING: multiple messages have this Message-ID (diff)
From: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>,
kernel-F5mvAk5X5gdBDgjK7y7TUQ@public.gmane.org,
Srinivas Kandagatla
<srinivas.kandagatla-qxv4g6HH51o@public.gmane.org>,
Linus Walleij
<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Patrice CHOTARD <patrice.chotard-qxv4g6HH51o@public.gmane.org>,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Stuart Menefy <stuart.menefy-qxv4g6HH51o@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Grant Likely
<grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Giuseppe Cavallaro <peppe.cavallaro-qxv4g6HH51o@public.gmane.org>,
maxime.coquelin-qxv4g6HH51o@public.gmane.org,
alexandre.torgue-qxv4g6HH51o@public.gmane.org
Subject: Re: [PATCH 1/4] ARM: STi: add stid127 soc support
Date: Thu, 30 Jan 2014 19:39:08 +0100 [thread overview]
Message-ID: <201401301939.08302.arnd@arndb.de> (raw)
In-Reply-To: <201401301935.16463.arnd-r2nGTMty4D4@public.gmane.org>
On Thursday 30 January 2014, Arnd Bergmann wrote:
> On Thursday 30 January 2014, Patrice CHOTARD wrote:
> > From: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org>
> >
> > This patch adds support to STiD127 SoC.
> > The main adaptation is the L2 cache way size compare to STiH41x SoCs.
> >
> > Signed-off-by: alexandre torgue <alexandre.torgue-qxv4g6HH51o@public.gmane.org>
> > Signed-off-by: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
> > ---
> > arch/arm/mach-sti/board-dt.c | 6 ++++++
> > 1 file changed, 6 insertions(+)
>
> Wouldn't it be better to read this value from the l2 cache
> controller node? I'd assume there might be more SoCs that
> will need a similar change, so it's better to come up with
> a solution that doesn't involve changing the kernel every
> time.
Actually reading the code in this file shows that the L2 cache
initialization is the only nonstandard thing in there. We should
really find a way to get rid of the entire function.
Sorry if I missed the initial review, but can you explain
why this is needed to start with?
Arnd
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
WARNING: multiple messages have this Message-ID (diff)
From: Arnd Bergmann <arnd@arndb.de>
To: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org, Russell King <linux@arm.linux.org.uk>,
kernel@stlinux.com,
Srinivas Kandagatla <srinivas.kandagatla@st.com>,
Linus Walleij <linus.walleij@linaro.org>,
Patrice CHOTARD <patrice.chotard@st.com>,
linux-kernel@vger.kernel.org,
Stuart Menefy <stuart.menefy@st.com>,
Rob Herring <robh+dt@kernel.org>,
Grant Likely <grant.likely@linaro.org>,
Giuseppe Cavallaro <peppe.cavallaro@st.com>,
maxime.coquelin@st.com, alexandre.torgue@st.com
Subject: Re: [PATCH 1/4] ARM: STi: add stid127 soc support
Date: Thu, 30 Jan 2014 19:39:08 +0100 [thread overview]
Message-ID: <201401301939.08302.arnd@arndb.de> (raw)
In-Reply-To: <201401301935.16463.arnd@arndb.de>
On Thursday 30 January 2014, Arnd Bergmann wrote:
> On Thursday 30 January 2014, Patrice CHOTARD wrote:
> > From: Alexandre TORGUE <alexandre.torgue@st.com>
> >
> > This patch adds support to STiD127 SoC.
> > The main adaptation is the L2 cache way size compare to STiH41x SoCs.
> >
> > Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
> > Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
> > ---
> > arch/arm/mach-sti/board-dt.c | 6 ++++++
> > 1 file changed, 6 insertions(+)
>
> Wouldn't it be better to read this value from the l2 cache
> controller node? I'd assume there might be more SoCs that
> will need a similar change, so it's better to come up with
> a solution that doesn't involve changing the kernel every
> time.
Actually reading the code in this file shows that the L2 cache
initialization is the only nonstandard thing in there. We should
really find a way to get rid of the entire function.
Sorry if I missed the initial review, but can you explain
why this is needed to start with?
Arnd
next prev parent reply other threads:[~2014-01-30 18:39 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-30 14:55 [PATCH 0/4] ARM:sti: Add STiD127 platform and board support Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-30 14:55 ` [PATCH 1/4] ARM: STi: add stid127 soc support Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-30 18:35 ` Arnd Bergmann
2014-01-30 18:35 ` Arnd Bergmann
2014-01-30 18:35 ` Arnd Bergmann
2014-01-30 18:39 ` Arnd Bergmann [this message]
2014-01-30 18:39 ` Arnd Bergmann
2014-01-30 18:39 ` Arnd Bergmann
2014-01-31 12:27 ` srinivas kandagatla
2014-01-31 12:27 ` srinivas kandagatla
2014-01-31 12:27 ` srinivas kandagatla
2014-01-31 20:15 ` Arnd Bergmann
2014-01-31 20:15 ` Arnd Bergmann
2014-01-31 20:15 ` Arnd Bergmann
2014-02-03 8:33 ` Alexandre Torgue
2014-02-03 8:33 ` Alexandre Torgue
2014-02-03 8:33 ` Alexandre Torgue
2014-02-05 11:48 ` srinivas kandagatla
2014-02-05 11:48 ` srinivas kandagatla
2014-02-05 11:48 ` srinivas kandagatla
2014-02-06 16:46 ` Arnd Bergmann
2014-02-06 16:46 ` Arnd Bergmann
2014-02-06 16:46 ` Arnd Bergmann
2014-02-07 8:08 ` srinivas kandagatla
2014-02-07 8:08 ` srinivas kandagatla
2014-02-07 8:08 ` srinivas kandagatla
2014-02-27 12:23 ` Maxime Coquelin
2014-02-27 12:23 ` Maxime Coquelin
2014-02-27 12:23 ` Maxime Coquelin
2014-02-27 12:27 ` Patrice Chotard
2014-02-27 12:27 ` Patrice Chotard
2014-02-27 12:27 ` Patrice Chotard
2014-01-30 14:55 ` [PATCH 2/4] pinctrl: st: add stid127 support Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-31 12:30 ` srinivas kandagatla
2014-01-31 12:30 ` srinivas kandagatla
2014-01-31 12:30 ` srinivas kandagatla
2014-02-04 20:54 ` Linus Walleij
2014-02-04 20:54 ` Linus Walleij
2014-01-30 14:55 ` [PATCH 3/4] ARM: dts: Add support of STid127 Soc Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-31 12:50 ` srinivas kandagatla
2014-01-31 12:50 ` srinivas kandagatla
2014-01-31 12:50 ` srinivas kandagatla
2014-02-05 10:27 ` Patrice Chotard
2014-02-05 10:27 ` Patrice Chotard
2014-02-05 10:27 ` Patrice Chotard
2014-01-30 14:55 ` [PATCH 4/4] ARM: dts: add B2112 board support Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-31 12:51 ` srinivas kandagatla
2014-01-31 12:51 ` srinivas kandagatla
2014-01-31 12:51 ` srinivas kandagatla
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=201401301939.08302.arnd@arndb.de \
--to=arnd@arndb.de \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.