From: alexandre.torgue@st.com (Alexandre Torgue)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/4] ARM: STi: add stid127 soc support
Date: Mon, 3 Feb 2014 09:33:49 +0100 [thread overview]
Message-ID: <52EF546D.7070900@st.com> (raw)
In-Reply-To: <201401312115.33731.arnd@arndb.de>
On 01/31/2014 09:15 PM, Arnd Bergmann wrote:
> On Friday 31 January 2014, srinivas kandagatla wrote:
>
>>> Sorry if I missed the initial review, but can you explain
>>> why this is needed to start with?
>> On ST SoCs the default value for L2 AUX_CTRL register is 0x0, so we set
>> the way-size explicit here.
> Unfortunately, we keep going back and forth on the L2 cache controller
> setup between "it should work automatically" and "we don't want to
> have configuration data in DT", where my personal opinion is that
> the first one is more important here.
>
> Now, there are a couple of properties that are defined in
> Documentation/devicetree/bindings/arm/l2cc.txt to let some of the
> things get set up automatically already. Can you check which bits
> are missing there, if any? Are they better described as "configuration"
> or "hardware" settings?
Hi Arnd,
Thanks for remarks. I will a have a look on it, but unfortunately not
before 2 weeks.
Alex.
>
> Arnd
WARNING: multiple messages have this Message-ID (diff)
From: Alexandre Torgue <alexandre.torgue-qxv4g6HH51o@public.gmane.org>
To: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>,
srinivas kandagatla
<srinivas.kandagatla-qxv4g6HH51o@public.gmane.org>
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>,
kernel-F5mvAk5X5gdBDgjK7y7TUQ@public.gmane.org,
Linus Walleij
<linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Patrice CHOTARD <patrice.chotard-qxv4g6HH51o@public.gmane.org>,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Stuart Menefy <stuart.menefy-qxv4g6HH51o@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Grant Likely
<grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>,
Giuseppe Cavallaro <peppe.cavallaro-qxv4g6HH51o@public.gmane.org>,
maxime.coquelin-qxv4g6HH51o@public.gmane.org
Subject: Re: [PATCH 1/4] ARM: STi: add stid127 soc support
Date: Mon, 3 Feb 2014 09:33:49 +0100 [thread overview]
Message-ID: <52EF546D.7070900@st.com> (raw)
In-Reply-To: <201401312115.33731.arnd-r2nGTMty4D4@public.gmane.org>
On 01/31/2014 09:15 PM, Arnd Bergmann wrote:
> On Friday 31 January 2014, srinivas kandagatla wrote:
>
>>> Sorry if I missed the initial review, but can you explain
>>> why this is needed to start with?
>> On ST SoCs the default value for L2 AUX_CTRL register is 0x0, so we set
>> the way-size explicit here.
> Unfortunately, we keep going back and forth on the L2 cache controller
> setup between "it should work automatically" and "we don't want to
> have configuration data in DT", where my personal opinion is that
> the first one is more important here.
>
> Now, there are a couple of properties that are defined in
> Documentation/devicetree/bindings/arm/l2cc.txt to let some of the
> things get set up automatically already. Can you check which bits
> are missing there, if any? Are they better described as "configuration"
> or "hardware" settings?
Hi Arnd,
Thanks for remarks. I will a have a look on it, but unfortunately not
before 2 weeks.
Alex.
>
> Arnd
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WARNING: multiple messages have this Message-ID (diff)
From: Alexandre Torgue <alexandre.torgue@st.com>
To: Arnd Bergmann <arnd@arndb.de>,
srinivas kandagatla <srinivas.kandagatla@st.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>,
Russell King <linux@arm.linux.org.uk>, <kernel@stlinux.com>,
Linus Walleij <linus.walleij@linaro.org>,
Patrice CHOTARD <patrice.chotard@st.com>,
<linux-kernel@vger.kernel.org>,
Stuart Menefy <stuart.menefy@st.com>,
Rob Herring <robh+dt@kernel.org>,
Grant Likely <grant.likely@linaro.org>,
Giuseppe Cavallaro <peppe.cavallaro@st.com>,
<maxime.coquelin@st.com>
Subject: Re: [PATCH 1/4] ARM: STi: add stid127 soc support
Date: Mon, 3 Feb 2014 09:33:49 +0100 [thread overview]
Message-ID: <52EF546D.7070900@st.com> (raw)
In-Reply-To: <201401312115.33731.arnd@arndb.de>
On 01/31/2014 09:15 PM, Arnd Bergmann wrote:
> On Friday 31 January 2014, srinivas kandagatla wrote:
>
>>> Sorry if I missed the initial review, but can you explain
>>> why this is needed to start with?
>> On ST SoCs the default value for L2 AUX_CTRL register is 0x0, so we set
>> the way-size explicit here.
> Unfortunately, we keep going back and forth on the L2 cache controller
> setup between "it should work automatically" and "we don't want to
> have configuration data in DT", where my personal opinion is that
> the first one is more important here.
>
> Now, there are a couple of properties that are defined in
> Documentation/devicetree/bindings/arm/l2cc.txt to let some of the
> things get set up automatically already. Can you check which bits
> are missing there, if any? Are they better described as "configuration"
> or "hardware" settings?
Hi Arnd,
Thanks for remarks. I will a have a look on it, but unfortunately not
before 2 weeks.
Alex.
>
> Arnd
next prev parent reply other threads:[~2014-02-03 8:33 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-30 14:55 [PATCH 0/4] ARM:sti: Add STiD127 platform and board support Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-30 14:55 ` [PATCH 1/4] ARM: STi: add stid127 soc support Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-30 18:35 ` Arnd Bergmann
2014-01-30 18:35 ` Arnd Bergmann
2014-01-30 18:35 ` Arnd Bergmann
2014-01-30 18:39 ` Arnd Bergmann
2014-01-30 18:39 ` Arnd Bergmann
2014-01-30 18:39 ` Arnd Bergmann
2014-01-31 12:27 ` srinivas kandagatla
2014-01-31 12:27 ` srinivas kandagatla
2014-01-31 12:27 ` srinivas kandagatla
2014-01-31 20:15 ` Arnd Bergmann
2014-01-31 20:15 ` Arnd Bergmann
2014-01-31 20:15 ` Arnd Bergmann
2014-02-03 8:33 ` Alexandre Torgue [this message]
2014-02-03 8:33 ` Alexandre Torgue
2014-02-03 8:33 ` Alexandre Torgue
2014-02-05 11:48 ` srinivas kandagatla
2014-02-05 11:48 ` srinivas kandagatla
2014-02-05 11:48 ` srinivas kandagatla
2014-02-06 16:46 ` Arnd Bergmann
2014-02-06 16:46 ` Arnd Bergmann
2014-02-06 16:46 ` Arnd Bergmann
2014-02-07 8:08 ` srinivas kandagatla
2014-02-07 8:08 ` srinivas kandagatla
2014-02-07 8:08 ` srinivas kandagatla
2014-02-27 12:23 ` Maxime Coquelin
2014-02-27 12:23 ` Maxime Coquelin
2014-02-27 12:23 ` Maxime Coquelin
2014-02-27 12:27 ` Patrice Chotard
2014-02-27 12:27 ` Patrice Chotard
2014-02-27 12:27 ` Patrice Chotard
2014-01-30 14:55 ` [PATCH 2/4] pinctrl: st: add stid127 support Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-31 12:30 ` srinivas kandagatla
2014-01-31 12:30 ` srinivas kandagatla
2014-01-31 12:30 ` srinivas kandagatla
2014-02-04 20:54 ` Linus Walleij
2014-02-04 20:54 ` Linus Walleij
2014-01-30 14:55 ` [PATCH 3/4] ARM: dts: Add support of STid127 Soc Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-31 12:50 ` srinivas kandagatla
2014-01-31 12:50 ` srinivas kandagatla
2014-01-31 12:50 ` srinivas kandagatla
2014-02-05 10:27 ` Patrice Chotard
2014-02-05 10:27 ` Patrice Chotard
2014-02-05 10:27 ` Patrice Chotard
2014-01-30 14:55 ` [PATCH 4/4] ARM: dts: add B2112 board support Patrice CHOTARD
2014-01-30 14:55 ` Patrice CHOTARD
2014-01-31 12:51 ` srinivas kandagatla
2014-01-31 12:51 ` srinivas kandagatla
2014-01-31 12:51 ` srinivas kandagatla
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