[PATCH 00/10] drm/i915: Fix VLV/CHV unclaimed register errors

[PATCH 00/10] drm/i915: Fix VLV/CHV unclaimed register errors

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

There were two main causes for the VLV/CHV unclaimed register errors during
runtime PM transitons: dipslay irq setup and vlv_init_display_clock_gating().
This series reorganizes those things so that we only do them when the
disp2d power well is actually enabled.

Ville Syrjälä (10):
  drm/i915: Remove "VLV magic" from irq setup
  drm/i915: Fix up vlv/chv display irq setup
  drm/i915: Skip display irq setup if display irqs aren't flagged as
    enabled
  drm/i915: Move vlv/chv display irq code to a more logical place
  drm/i915: Clear display interrupt before enabling when turning on the
    power well
  drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall()
  drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq
    postinstall
  drm/i915: Move vlv_init_display_clock_gating() to the display power
    well
  drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()
  Revert "drm/i915: Limit the auto arming of mmio debugs on vlv/chv"

 drivers/gpu/drm/i915/i915_irq.c         | 217 +++++++++++---------------------
 drivers/gpu/drm/i915/intel_pm.c         |  15 ---
 drivers/gpu/drm/i915/intel_runtime_pm.c |  13 ++
 drivers/gpu/drm/i915/intel_uncore.c     |   9 --
 4 files changed, 89 insertions(+), 165 deletions(-)

-- 
2.7.4

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[PATCH 01/10] drm/i915: Remove "VLV magic" from irq setup

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

No clue what this is supposed to achieve. I think it's been there since
the very beginning, so presumably some kind of kludge for very early
silicon. Let's just throw it out.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 679f08c944ef..1d21ebfffd4d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3319,12 +3319,6 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	/* VLV magic */
-	I915_WRITE(VLV_IMR, 0);
-	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
-	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
-	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
-
 	gen5_gt_irq_reset(dev);
 
 	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
-- 
2.7.4

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Re: [PATCH 01/10] drm/i915: Remove "VLV magic" from irq setup

[Imre Deak]

On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> No clue what this is supposed to achieve. I think it's been there
> since
> the very beginning, so presumably some kind of kludge for very early
> silicon. Let's just throw it out.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 6 ------
>  1 file changed, 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 679f08c944ef..1d21ebfffd4d 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3319,12 +3319,6 @@ static void valleyview_irq_preinstall(struct
> drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	/* VLV magic */
> -	I915_WRITE(VLV_IMR, 0);
> -	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
> -	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
> -	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
> -

AFAICS this would also leave the ring interrupts unmasked before we
called ring->get_irq(), so at least the change is a fix for that. I
haven't found any explanation for the above either, so I guess the best
we can do at this point is to see if things continue to work without
it:

Reviewed-by: Imre Deak <imre.deak@intel.com>

>  	gen5_gt_irq_reset(dev);
>  
>  	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
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Re: [PATCH 01/10] drm/i915: Remove "VLV magic" from irq setup

[Ville Syrjälä]

On Mon, Apr 11, 2016 at 06:20:04PM +0300, Imre Deak wrote:
> On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > No clue what this is supposed to achieve. I think it's been there
> > since
> > the very beginning, so presumably some kind of kludge for very early
> > silicon. Let's just throw it out.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 6 ------
> >  1 file changed, 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 679f08c944ef..1d21ebfffd4d 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3319,12 +3319,6 @@ static void valleyview_irq_preinstall(struct
> > drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  
> > -	/* VLV magic */
> > -	I915_WRITE(VLV_IMR, 0);
> > -	I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
> > -	I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
> > -	I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
> > -
> 
> AFAICS this would also leave the ring interrupts unmasked before we
> called ring->get_irq(), so at least the change is a fix for that.

On a related note, in ringbuffer mode we don't actually make sure they're
masked. The execlist code has explicit ring IMR initialization.

> I
> haven't found any explanation for the above either, so I guess the best
> we can do at this point is to see if things continue to work without
> it:
> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> >  	gen5_gt_irq_reset(dev);
> >  
> >  	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);

-- 
Ville Syrjälä
Intel OTC
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[PATCH 02/10] drm/i915: Fix up vlv/chv display irq setup

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The vlv/chv display irq setup was a bit of mess after I ran out of steam
when working on it last. Fix it up so that we just have a _reset() and
_postinstall() hooks for the display irqs, and use those consistently.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 102 ++++++++++------------------------------
 1 file changed, 24 insertions(+), 78 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1d21ebfffd4d..a1239fedc086 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3306,13 +3306,15 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
 {
 	enum pipe pipe;
 
-	i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0);
+	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
 	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
 
 	for_each_pipe(dev_priv, pipe)
 		I915_WRITE(PIPESTAT(pipe), 0xffff);
 
 	GEN5_IRQ_RESET(VLV_);
+
+	dev_priv->irq_mask = ~0;
 }
 
 static void valleyview_irq_preinstall(struct drm_device *dev)
@@ -3323,7 +3325,9 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
 
 	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
 
+	spin_lock_irq(&dev_priv->irq_lock);
 	vlv_display_irq_reset(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
@@ -3398,7 +3402,9 @@ static void cherryview_irq_preinstall(struct drm_device *dev)
 
 	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
 
+	spin_lock_irq(&dev_priv->irq_lock);
 	vlv_display_irq_reset(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
 static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
@@ -3645,7 +3651,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
-static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
+static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
 {
 	u32 pipestat_mask;
 	u32 iir_mask;
@@ -3679,40 +3685,6 @@ static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
 	POSTING_READ(VLV_IMR);
 }
 
-static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
-{
-	u32 pipestat_mask;
-	u32 iir_mask;
-	enum pipe pipe;
-
-	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
-		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
-	if (IS_CHERRYVIEW(dev_priv))
-		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
-
-	dev_priv->irq_mask |= iir_mask;
-	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
-	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
-	I915_WRITE(VLV_IIR, iir_mask);
-	I915_WRITE(VLV_IIR, iir_mask);
-	POSTING_READ(VLV_IIR);
-
-	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
-			PIPE_CRC_DONE_INTERRUPT_STATUS;
-
-	i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
-	for_each_pipe(dev_priv, pipe)
-		i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
-
-	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
-			PIPE_FIFO_UNDERRUN_STATUS;
-
-	for_each_pipe(dev_priv, pipe)
-		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
-	POSTING_READ(PIPESTAT(PIPE_A));
-}
-
 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
 {
 	assert_spin_locked(&dev_priv->irq_lock);
@@ -3723,7 +3695,7 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
 	dev_priv->display_irqs_enabled = true;
 
 	if (intel_irqs_enabled(dev_priv))
-		valleyview_display_irqs_install(dev_priv);
+		vlv_display_irq_postinstall(dev_priv);
 }
 
 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
@@ -3736,36 +3708,14 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
 	dev_priv->display_irqs_enabled = false;
 
 	if (intel_irqs_enabled(dev_priv))
-		valleyview_display_irqs_uninstall(dev_priv);
+		vlv_display_irq_reset(dev_priv);
 }
 
-static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
-{
-	dev_priv->irq_mask = ~0;
-
-	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
-	POSTING_READ(PORT_HOTPLUG_EN);
-
-	I915_WRITE(VLV_IIR, 0xffffffff);
-	I915_WRITE(VLV_IIR, 0xffffffff);
-	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
-	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
-	POSTING_READ(VLV_IMR);
-
-	/* Interrupt setup is already guaranteed to be single-threaded, this is
-	 * just to make the assert_spin_locked check happy. */
-	spin_lock_irq(&dev_priv->irq_lock);
-	if (dev_priv->display_irqs_enabled)
-		valleyview_display_irqs_install(dev_priv);
-	spin_unlock_irq(&dev_priv->irq_lock);
-}
 
 static int valleyview_irq_postinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	vlv_display_irq_postinstall(dev_priv);
-
 	gen5_gt_irq_postinstall(dev);
 
 	/* ack & enable invalid PTE error interrupts */
@@ -3774,6 +3724,10 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
 	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
 #endif
 
+	spin_lock_irq(&dev_priv->irq_lock);
+	vlv_display_irq_postinstall(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
+
 	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
 
 	return 0;
@@ -3874,10 +3828,12 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	vlv_display_irq_postinstall(dev_priv);
-
 	gen8_gt_irq_postinstall(dev_priv);
 
+	spin_lock_irq(&dev_priv->irq_lock);
+	vlv_display_irq_postinstall(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
+
 	I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
 	POSTING_READ(GEN8_MASTER_IRQ);
 
@@ -3894,20 +3850,6 @@ static void gen8_irq_uninstall(struct drm_device *dev)
 	gen8_irq_reset(dev);
 }
 
-static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
-{
-	/* Interrupt setup is already guaranteed to be single-threaded, this is
-	 * just to make the assert_spin_locked check happy. */
-	spin_lock_irq(&dev_priv->irq_lock);
-	if (dev_priv->display_irqs_enabled)
-		valleyview_display_irqs_uninstall(dev_priv);
-	spin_unlock_irq(&dev_priv->irq_lock);
-
-	vlv_display_irq_reset(dev_priv);
-
-	dev_priv->irq_mask = ~0;
-}
-
 static void valleyview_irq_uninstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3921,7 +3863,9 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
 
 	I915_WRITE(HWSTAM, 0xffffffff);
 
-	vlv_display_irq_uninstall(dev_priv);
+	spin_lock_irq(&dev_priv->irq_lock);
+	vlv_display_irq_reset(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
 static void cherryview_irq_uninstall(struct drm_device *dev)
@@ -3938,7 +3882,9 @@ static void cherryview_irq_uninstall(struct drm_device *dev)
 
 	GEN5_IRQ_RESET(GEN8_PCU_);
 
-	vlv_display_irq_uninstall(dev_priv);
+	spin_lock_irq(&dev_priv->irq_lock);
+	vlv_display_irq_reset(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
 static void ironlake_irq_uninstall(struct drm_device *dev)
-- 
2.7.4

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Re: [PATCH 02/10] drm/i915: Fix up vlv/chv display irq setup

[Imre Deak]

On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The vlv/chv display irq setup was a bit of mess after I ran out of steam
> when working on it last. Fix it up so that we just have a _reset() and
> _postinstall() hooks for the display irqs, and use those consistently.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 102 ++++++++++------------------------------
>  1 file changed, 24 insertions(+), 78 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 1d21ebfffd4d..a1239fedc086 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3306,13 +3306,15 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
>  {
>  	enum pipe pipe;
>  
> -	i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0);
> +	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
>  	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
>  
>  	for_each_pipe(dev_priv, pipe)
>  		I915_WRITE(PIPESTAT(pipe), 0xffff);

Since vlv_display_irq_reset() will be used in place
of valleyview_display_irqs_uninstall()/i915_disable_pipestat()
we'll leave now stale bits in pipestat_irq_mask[pipe]. It's not a
problem since display_irqs_enabled effectively masks these bits, but
for consistency I'd clear them.

The same goes for clearing PIPE_FIFO_UNDERRUN_STATUS.

With that:
Reviewed-by: Imre Deak <imre.deak@intel.com>

>  
>  	GEN5_IRQ_RESET(VLV_);
> +
> +	dev_priv->irq_mask = ~0;
>  }



>  
>  static void valleyview_irq_preinstall(struct drm_device *dev)
> @@ -3323,7 +3325,9 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
>  
>  	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
>  
> +	spin_lock_irq(&dev_priv->irq_lock);
>  	vlv_display_irq_reset(dev_priv);
> +	spin_unlock_irq(&dev_priv->irq_lock);
>  }
>  
>  static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3398,7 +3402,9 @@ static void cherryview_irq_preinstall(struct drm_device *dev)
>  
>  	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
>  
> +	spin_lock_irq(&dev_priv->irq_lock);
>  	vlv_display_irq_reset(dev_priv);
> +	spin_unlock_irq(&dev_priv->irq_lock);
>  }
>  
>  static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
> @@ -3645,7 +3651,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
>  	return 0;
>  }
>  
> -static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
> +static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
>  {
>  	u32 pipestat_mask;
>  	u32 iir_mask;
> @@ -3679,40 +3685,6 @@ static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
>  	POSTING_READ(VLV_IMR);
>  }
>  
> -static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
> -{
> -	u32 pipestat_mask;
> -	u32 iir_mask;
> -	enum pipe pipe;
> -
> -	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
> -		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
> -		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
> -	if (IS_CHERRYVIEW(dev_priv))
> -		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
> -
> -	dev_priv->irq_mask |= iir_mask;
> -	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
> -	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
> -	I915_WRITE(VLV_IIR, iir_mask);
> -	I915_WRITE(VLV_IIR, iir_mask);
> -	POSTING_READ(VLV_IIR);
> -
> -	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
> -			PIPE_CRC_DONE_INTERRUPT_STATUS;
> -
> -	i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
> -	for_each_pipe(dev_priv, pipe)
> -		i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
> -
> -	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
> -			PIPE_FIFO_UNDERRUN_STATUS;
> -
> -	for_each_pipe(dev_priv, pipe)
> -		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
> -	POSTING_READ(PIPESTAT(PIPE_A));
> -}
> -
>  void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
>  {
>  	assert_spin_locked(&dev_priv->irq_lock);
> @@ -3723,7 +3695,7 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
>  	dev_priv->display_irqs_enabled = true;
>  
>  	if (intel_irqs_enabled(dev_priv))
> -		valleyview_display_irqs_install(dev_priv);
> +		vlv_display_irq_postinstall(dev_priv);
>  }
>  
>  void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
> @@ -3736,36 +3708,14 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
>  	dev_priv->display_irqs_enabled = false;
>  
>  	if (intel_irqs_enabled(dev_priv))
> -		valleyview_display_irqs_uninstall(dev_priv);
> +		vlv_display_irq_reset(dev_priv);
>  }
>  
> -static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
> -{
> -	dev_priv->irq_mask = ~0;
> -
> -	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
> -	POSTING_READ(PORT_HOTPLUG_EN);
> -
> -	I915_WRITE(VLV_IIR, 0xffffffff);
> -	I915_WRITE(VLV_IIR, 0xffffffff);
> -	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
> -	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
> -	POSTING_READ(VLV_IMR);
> -
> -	/* Interrupt setup is already guaranteed to be single-threaded, this is
> -	 * just to make the assert_spin_locked check happy. */
> -	spin_lock_irq(&dev_priv->irq_lock);
> -	if (dev_priv->display_irqs_enabled)
> -		valleyview_display_irqs_install(dev_priv);
> -	spin_unlock_irq(&dev_priv->irq_lock);
> -}
>  
>  static int valleyview_irq_postinstall(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	vlv_display_irq_postinstall(dev_priv);
> -
>  	gen5_gt_irq_postinstall(dev);
>  
>  	/* ack & enable invalid PTE error interrupts */
> @@ -3774,6 +3724,10 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
>  	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
>  #endif
>  
> +	spin_lock_irq(&dev_priv->irq_lock);
> +	vlv_display_irq_postinstall(dev_priv);
> +	spin_unlock_irq(&dev_priv->irq_lock);
> +
>  	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
>  
>  	return 0;
> @@ -3874,10 +3828,12 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	vlv_display_irq_postinstall(dev_priv);
> -
>  	gen8_gt_irq_postinstall(dev_priv);
>  
> +	spin_lock_irq(&dev_priv->irq_lock);
> +	vlv_display_irq_postinstall(dev_priv);
> +	spin_unlock_irq(&dev_priv->irq_lock);
> +
>  	I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
>  	POSTING_READ(GEN8_MASTER_IRQ);
>  
> @@ -3894,20 +3850,6 @@ static void gen8_irq_uninstall(struct drm_device *dev)
>  	gen8_irq_reset(dev);
>  }
>  
> -static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
> -{
> -	/* Interrupt setup is already guaranteed to be single-threaded, this is
> -	 * just to make the assert_spin_locked check happy. */
> -	spin_lock_irq(&dev_priv->irq_lock);
> -	if (dev_priv->display_irqs_enabled)
> -		valleyview_display_irqs_uninstall(dev_priv);
> -	spin_unlock_irq(&dev_priv->irq_lock);
> -
> -	vlv_display_irq_reset(dev_priv);
> -
> -	dev_priv->irq_mask = ~0;
> -}
> -
>  static void valleyview_irq_uninstall(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3921,7 +3863,9 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
>  
>  	I915_WRITE(HWSTAM, 0xffffffff);
>  
> -	vlv_display_irq_uninstall(dev_priv);
> +	spin_lock_irq(&dev_priv->irq_lock);
> +	vlv_display_irq_reset(dev_priv);
> +	spin_unlock_irq(&dev_priv->irq_lock);
>  }
>  
>  static void cherryview_irq_uninstall(struct drm_device *dev)
> @@ -3938,7 +3882,9 @@ static void cherryview_irq_uninstall(struct drm_device *dev)
>  
>  	GEN5_IRQ_RESET(GEN8_PCU_);
>  
> -	vlv_display_irq_uninstall(dev_priv);
> +	spin_lock_irq(&dev_priv->irq_lock);
> +	vlv_display_irq_reset(dev_priv);
> +	spin_unlock_irq(&dev_priv->irq_lock);
>  }
>  
>  static void ironlake_irq_uninstall(struct drm_device *dev)
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Re: [PATCH 02/10] drm/i915: Fix up vlv/chv display irq setup

[Ville Syrjälä]

On Mon, Apr 11, 2016 at 07:29:13PM +0300, Imre Deak wrote:
> On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The vlv/chv display irq setup was a bit of mess after I ran out of steam
> > when working on it last. Fix it up so that we just have a _reset() and
> > _postinstall() hooks for the display irqs, and use those consistently.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_irq.c | 102 ++++++++++------------------------------
> >  1 file changed, 24 insertions(+), 78 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 1d21ebfffd4d..a1239fedc086 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3306,13 +3306,15 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
> >  {
> >  	enum pipe pipe;
> >  
> > -	i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0);
> > +	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
> >  	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
> >  
> >  	for_each_pipe(dev_priv, pipe)
> >  		I915_WRITE(PIPESTAT(pipe), 0xffff);
> 
> Since vlv_display_irq_reset() will be used in place
> of valleyview_display_irqs_uninstall()/i915_disable_pipestat()
> we'll leave now stale bits in pipestat_irq_mask[pipe]. It's not a
> problem since display_irqs_enabled effectively masks these bits, but
> for consistency I'd clear them.

OTOH we can't mask PIPESTAT bits, so even if we clear them here, it's
very likely some of the bits will be set again by the time we actually
enable an interrupt.

In any case, I think I'll be posting a patch to clean up the PIPESTAT
clearing/disabling acrosss the board. It's a bit of a mess right now,
with each platform doing things slightly differently.

> 
> The same goes for clearing PIPE_FIFO_UNDERRUN_STATUS.
> 
> With that:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> >  
> >  	GEN5_IRQ_RESET(VLV_);
> > +
> > +	dev_priv->irq_mask = ~0;
> >  }
> 
> 
> 
> >  
> >  static void valleyview_irq_preinstall(struct drm_device *dev)
> > @@ -3323,7 +3325,9 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
> >  
> >  	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
> >  
> > +	spin_lock_irq(&dev_priv->irq_lock);
> >  	vlv_display_irq_reset(dev_priv);
> > +	spin_unlock_irq(&dev_priv->irq_lock);
> >  }
> >  
> >  static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3398,7 +3402,9 @@ static void cherryview_irq_preinstall(struct drm_device *dev)
> >  
> >  	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
> >  
> > +	spin_lock_irq(&dev_priv->irq_lock);
> >  	vlv_display_irq_reset(dev_priv);
> > +	spin_unlock_irq(&dev_priv->irq_lock);
> >  }
> >  
> >  static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
> > @@ -3645,7 +3651,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
> >  	return 0;
> >  }
> >  
> > -static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
> > +static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
> >  {
> >  	u32 pipestat_mask;
> >  	u32 iir_mask;
> > @@ -3679,40 +3685,6 @@ static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
> >  	POSTING_READ(VLV_IMR);
> >  }
> >  
> > -static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
> > -{
> > -	u32 pipestat_mask;
> > -	u32 iir_mask;
> > -	enum pipe pipe;
> > -
> > -	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
> > -		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
> > -		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
> > -	if (IS_CHERRYVIEW(dev_priv))
> > -		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
> > -
> > -	dev_priv->irq_mask |= iir_mask;
> > -	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
> > -	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
> > -	I915_WRITE(VLV_IIR, iir_mask);
> > -	I915_WRITE(VLV_IIR, iir_mask);
> > -	POSTING_READ(VLV_IIR);
> > -
> > -	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
> > -			PIPE_CRC_DONE_INTERRUPT_STATUS;
> > -
> > -	i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
> > -	for_each_pipe(dev_priv, pipe)
> > -		i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
> > -
> > -	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
> > -			PIPE_FIFO_UNDERRUN_STATUS;
> > -
> > -	for_each_pipe(dev_priv, pipe)
> > -		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
> > -	POSTING_READ(PIPESTAT(PIPE_A));
> > -}
> > -
> >  void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
> >  {
> >  	assert_spin_locked(&dev_priv->irq_lock);
> > @@ -3723,7 +3695,7 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
> >  	dev_priv->display_irqs_enabled = true;
> >  
> >  	if (intel_irqs_enabled(dev_priv))
> > -		valleyview_display_irqs_install(dev_priv);
> > +		vlv_display_irq_postinstall(dev_priv);
> >  }
> >  
> >  void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
> > @@ -3736,36 +3708,14 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
> >  	dev_priv->display_irqs_enabled = false;
> >  
> >  	if (intel_irqs_enabled(dev_priv))
> > -		valleyview_display_irqs_uninstall(dev_priv);
> > +		vlv_display_irq_reset(dev_priv);
> >  }
> >  
> > -static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
> > -{
> > -	dev_priv->irq_mask = ~0;
> > -
> > -	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
> > -	POSTING_READ(PORT_HOTPLUG_EN);
> > -
> > -	I915_WRITE(VLV_IIR, 0xffffffff);
> > -	I915_WRITE(VLV_IIR, 0xffffffff);
> > -	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
> > -	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
> > -	POSTING_READ(VLV_IMR);
> > -
> > -	/* Interrupt setup is already guaranteed to be single-threaded, this is
> > -	 * just to make the assert_spin_locked check happy. */
> > -	spin_lock_irq(&dev_priv->irq_lock);
> > -	if (dev_priv->display_irqs_enabled)
> > -		valleyview_display_irqs_install(dev_priv);
> > -	spin_unlock_irq(&dev_priv->irq_lock);
> > -}
> >  
> >  static int valleyview_irq_postinstall(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  
> > -	vlv_display_irq_postinstall(dev_priv);
> > -
> >  	gen5_gt_irq_postinstall(dev);
> >  
> >  	/* ack & enable invalid PTE error interrupts */
> > @@ -3774,6 +3724,10 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
> >  	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
> >  #endif
> >  
> > +	spin_lock_irq(&dev_priv->irq_lock);
> > +	vlv_display_irq_postinstall(dev_priv);
> > +	spin_unlock_irq(&dev_priv->irq_lock);
> > +
> >  	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
> >  
> >  	return 0;
> > @@ -3874,10 +3828,12 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  
> > -	vlv_display_irq_postinstall(dev_priv);
> > -
> >  	gen8_gt_irq_postinstall(dev_priv);
> >  
> > +	spin_lock_irq(&dev_priv->irq_lock);
> > +	vlv_display_irq_postinstall(dev_priv);
> > +	spin_unlock_irq(&dev_priv->irq_lock);
> > +
> >  	I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
> >  	POSTING_READ(GEN8_MASTER_IRQ);
> >  
> > @@ -3894,20 +3850,6 @@ static void gen8_irq_uninstall(struct drm_device *dev)
> >  	gen8_irq_reset(dev);
> >  }
> >  
> > -static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
> > -{
> > -	/* Interrupt setup is already guaranteed to be single-threaded, this is
> > -	 * just to make the assert_spin_locked check happy. */
> > -	spin_lock_irq(&dev_priv->irq_lock);
> > -	if (dev_priv->display_irqs_enabled)
> > -		valleyview_display_irqs_uninstall(dev_priv);
> > -	spin_unlock_irq(&dev_priv->irq_lock);
> > -
> > -	vlv_display_irq_reset(dev_priv);
> > -
> > -	dev_priv->irq_mask = ~0;
> > -}
> > -
> >  static void valleyview_irq_uninstall(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -3921,7 +3863,9 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
> >  
> >  	I915_WRITE(HWSTAM, 0xffffffff);
> >  
> > -	vlv_display_irq_uninstall(dev_priv);
> > +	spin_lock_irq(&dev_priv->irq_lock);
> > +	vlv_display_irq_reset(dev_priv);
> > +	spin_unlock_irq(&dev_priv->irq_lock);
> >  }
> >  
> >  static void cherryview_irq_uninstall(struct drm_device *dev)
> > @@ -3938,7 +3882,9 @@ static void cherryview_irq_uninstall(struct drm_device *dev)
> >  
> >  	GEN5_IRQ_RESET(GEN8_PCU_);
> >  
> > -	vlv_display_irq_uninstall(dev_priv);
> > +	spin_lock_irq(&dev_priv->irq_lock);
> > +	vlv_display_irq_reset(dev_priv);
> > +	spin_unlock_irq(&dev_priv->irq_lock);
> >  }
> >  
> >  static void ironlake_irq_uninstall(struct drm_device *dev)

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 02/10] drm/i915: Fix up vlv/chv display irq setup

[Imre Deak]

On ti, 2016-04-12 at 12:05 +0300, Ville Syrjälä wrote:
> On Mon, Apr 11, 2016 at 07:29:13PM +0300, Imre Deak wrote:
> > On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com
> > wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > The vlv/chv display irq setup was a bit of mess after I ran out
> > > of steam
> > > when working on it last. Fix it up so that we just have a
> > > _reset() and
> > > _postinstall() hooks for the display irqs, and use those
> > > consistently.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_irq.c | 102 ++++++++++--------------
> > > ----------------
> > >  1 file changed, 24 insertions(+), 78 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index 1d21ebfffd4d..a1239fedc086 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -3306,13 +3306,15 @@ static void vlv_display_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > >  {
> > >  	enum pipe pipe;
> > >  
> > > -	i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0);
> > > +	i915_hotplug_interrupt_update_locked(dev_priv,
> > > 0xffffffff, 0);
> > >  	I915_WRITE(PORT_HOTPLUG_STAT,
> > > I915_READ(PORT_HOTPLUG_STAT));
> > >  
> > >  	for_each_pipe(dev_priv, pipe)
> > >  		I915_WRITE(PIPESTAT(pipe), 0xffff);
> > 
> > Since vlv_display_irq_reset() will be used in place
> > of valleyview_display_irqs_uninstall()/i915_disable_pipestat()
> > we'll leave now stale bits in pipestat_irq_mask[pipe]. It's not a
> > problem since display_irqs_enabled effectively masks these bits,
> > but
> > for consistency I'd clear them.
> 
> OTOH we can't mask PIPESTAT bits, so even if we clear them here, it's
> very likely some of the bits will be set again by the time we
> actually
> enable an interrupt.
> 
> In any case, I think I'll be posting a patch to clean up the PIPESTAT
> clearing/disabling acrosss the board. It's a bit of a mess right now,
> with each platform doing things slightly differently.

Ok, you could add something about the above to the commit message. My
R-b applies in any case.

> > The same goes for clearing PIPE_FIFO_UNDERRUN_STATUS.
> > 
> > With that:
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> > 
> > >  
> > >  	GEN5_IRQ_RESET(VLV_);
> > > +
> > > +	dev_priv->irq_mask = ~0;
> > >  }
> > 
> > 
> > 
> > >  
> > >  static void valleyview_irq_preinstall(struct drm_device *dev)
> > > @@ -3323,7 +3325,9 @@ static void
> > > valleyview_irq_preinstall(struct drm_device *dev)
> > >  
> > >  	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
> > >  
> > > +	spin_lock_irq(&dev_priv->irq_lock);
> > >  	vlv_display_irq_reset(dev_priv);
> > > +	spin_unlock_irq(&dev_priv->irq_lock);
> > >  }
> > >  
> > >  static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
> > > @@ -3398,7 +3402,9 @@ static void
> > > cherryview_irq_preinstall(struct drm_device *dev)
> > >  
> > >  	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
> > >  
> > > +	spin_lock_irq(&dev_priv->irq_lock);
> > >  	vlv_display_irq_reset(dev_priv);
> > > +	spin_unlock_irq(&dev_priv->irq_lock);
> > >  }
> > >  
> > >  static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
> > > @@ -3645,7 +3651,7 @@ static int ironlake_irq_postinstall(struct
> > > drm_device *dev)
> > >  	return 0;
> > >  }
> > >  
> > > -static void valleyview_display_irqs_install(struct
> > > drm_i915_private *dev_priv)
> > > +static void vlv_display_irq_postinstall(struct drm_i915_private
> > > *dev_priv)
> > >  {
> > >  	u32 pipestat_mask;
> > >  	u32 iir_mask;
> > > @@ -3679,40 +3685,6 @@ static void
> > > valleyview_display_irqs_install(struct drm_i915_private
> > > *dev_priv)
> > >  	POSTING_READ(VLV_IMR);
> > >  }
> > >  
> > > -static void valleyview_display_irqs_uninstall(struct
> > > drm_i915_private *dev_priv)
> > > -{
> > > -	u32 pipestat_mask;
> > > -	u32 iir_mask;
> > > -	enum pipe pipe;
> > > -
> > > -	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
> > > -		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
> > > -		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
> > > -	if (IS_CHERRYVIEW(dev_priv))
> > > -		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
> > > -
> > > -	dev_priv->irq_mask |= iir_mask;
> > > -	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
> > > -	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
> > > -	I915_WRITE(VLV_IIR, iir_mask);
> > > -	I915_WRITE(VLV_IIR, iir_mask);
> > > -	POSTING_READ(VLV_IIR);
> > > -
> > > -	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
> > > -			PIPE_CRC_DONE_INTERRUPT_STATUS;
> > > -
> > > -	i915_disable_pipestat(dev_priv, PIPE_A,
> > > PIPE_GMBUS_INTERRUPT_STATUS);
> > > -	for_each_pipe(dev_priv, pipe)
> > > -		i915_disable_pipestat(dev_priv, pipe,
> > > pipestat_mask);
> > > -
> > > -	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
> > > -			PIPE_FIFO_UNDERRUN_STATUS;
> > > -
> > > -	for_each_pipe(dev_priv, pipe)
> > > -		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
> > > -	POSTING_READ(PIPESTAT(PIPE_A));
> > > -}
> > > -
> > >  void valleyview_enable_display_irqs(struct drm_i915_private
> > > *dev_priv)
> > >  {
> > >  	assert_spin_locked(&dev_priv->irq_lock);
> > > @@ -3723,7 +3695,7 @@ void valleyview_enable_display_irqs(struct
> > > drm_i915_private *dev_priv)
> > >  	dev_priv->display_irqs_enabled = true;
> > >  
> > >  	if (intel_irqs_enabled(dev_priv))
> > > -		valleyview_display_irqs_install(dev_priv);
> > > +		vlv_display_irq_postinstall(dev_priv);
> > >  }
> > >  
> > >  void valleyview_disable_display_irqs(struct drm_i915_private
> > > *dev_priv)
> > > @@ -3736,36 +3708,14 @@ void
> > > valleyview_disable_display_irqs(struct drm_i915_private
> > > *dev_priv)
> > >  	dev_priv->display_irqs_enabled = false;
> > >  
> > >  	if (intel_irqs_enabled(dev_priv))
> > > -		valleyview_display_irqs_uninstall(dev_priv);
> > > +		vlv_display_irq_reset(dev_priv);
> > >  }
> > >  
> > > -static void vlv_display_irq_postinstall(struct drm_i915_private
> > > *dev_priv)
> > > -{
> > > -	dev_priv->irq_mask = ~0;
> > > -
> > > -	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
> > > -	POSTING_READ(PORT_HOTPLUG_EN);
> > > -
> > > -	I915_WRITE(VLV_IIR, 0xffffffff);
> > > -	I915_WRITE(VLV_IIR, 0xffffffff);
> > > -	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
> > > -	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
> > > -	POSTING_READ(VLV_IMR);
> > > -
> > > -	/* Interrupt setup is already guaranteed to be single-
> > > threaded, this is
> > > -	 * just to make the assert_spin_locked check happy. */
> > > -	spin_lock_irq(&dev_priv->irq_lock);
> > > -	if (dev_priv->display_irqs_enabled)
> > > -		valleyview_display_irqs_install(dev_priv);
> > > -	spin_unlock_irq(&dev_priv->irq_lock);
> > > -}
> > >  
> > >  static int valleyview_irq_postinstall(struct drm_device *dev)
> > >  {
> > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > >  
> > > -	vlv_display_irq_postinstall(dev_priv);
> > > -
> > >  	gen5_gt_irq_postinstall(dev);
> > >  
> > >  	/* ack & enable invalid PTE error interrupts */
> > > @@ -3774,6 +3724,10 @@ static int
> > > valleyview_irq_postinstall(struct drm_device *dev)
> > >  	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
> > >  #endif
> > >  
> > > +	spin_lock_irq(&dev_priv->irq_lock);
> > > +	vlv_display_irq_postinstall(dev_priv);
> > > +	spin_unlock_irq(&dev_priv->irq_lock);
> > > +
> > >  	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
> > >  
> > >  	return 0;
> > > @@ -3874,10 +3828,12 @@ static int
> > > cherryview_irq_postinstall(struct drm_device *dev)
> > >  {
> > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > >  
> > > -	vlv_display_irq_postinstall(dev_priv);
> > > -
> > >  	gen8_gt_irq_postinstall(dev_priv);
> > >  
> > > +	spin_lock_irq(&dev_priv->irq_lock);
> > > +	vlv_display_irq_postinstall(dev_priv);
> > > +	spin_unlock_irq(&dev_priv->irq_lock);
> > > +
> > >  	I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
> > >  	POSTING_READ(GEN8_MASTER_IRQ);
> > >  
> > > @@ -3894,20 +3850,6 @@ static void gen8_irq_uninstall(struct
> > > drm_device *dev)
> > >  	gen8_irq_reset(dev);
> > >  }
> > >  
> > > -static void vlv_display_irq_uninstall(struct drm_i915_private
> > > *dev_priv)
> > > -{
> > > -	/* Interrupt setup is already guaranteed to be single-
> > > threaded, this is
> > > -	 * just to make the assert_spin_locked check happy. */
> > > -	spin_lock_irq(&dev_priv->irq_lock);
> > > -	if (dev_priv->display_irqs_enabled)
> > > -		valleyview_display_irqs_uninstall(dev_priv);
> > > -	spin_unlock_irq(&dev_priv->irq_lock);
> > > -
> > > -	vlv_display_irq_reset(dev_priv);
> > > -
> > > -	dev_priv->irq_mask = ~0;
> > > -}
> > > -
> > >  static void valleyview_irq_uninstall(struct drm_device *dev)
> > >  {
> > >  	struct drm_i915_private *dev_priv = dev->dev_private;
> > > @@ -3921,7 +3863,9 @@ static void valleyview_irq_uninstall(struct
> > > drm_device *dev)
> > >  
> > >  	I915_WRITE(HWSTAM, 0xffffffff);
> > >  
> > > -	vlv_display_irq_uninstall(dev_priv);
> > > +	spin_lock_irq(&dev_priv->irq_lock);
> > > +	vlv_display_irq_reset(dev_priv);
> > > +	spin_unlock_irq(&dev_priv->irq_lock);
> > >  }
> > >  
> > >  static void cherryview_irq_uninstall(struct drm_device *dev)
> > > @@ -3938,7 +3882,9 @@ static void cherryview_irq_uninstall(struct
> > > drm_device *dev)
> > >  
> > >  	GEN5_IRQ_RESET(GEN8_PCU_);
> > >  
> > > -	vlv_display_irq_uninstall(dev_priv);
> > > +	spin_lock_irq(&dev_priv->irq_lock);
> > > +	vlv_display_irq_reset(dev_priv);
> > > +	spin_unlock_irq(&dev_priv->irq_lock);
> > >  }
> > >  
> > >  static void ironlake_irq_uninstall(struct drm_device *dev)
> 
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[PATCH v2 02/10] drm/i915: Fix up vlv/chv display irq setup

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The vlv/chv display irq setup was a bit of mess after I ran out of steam
when working on it last. Fix it up so that we just have a _reset() and
_postinstall() hooks for the display irqs, and use those consistently.

v2: Clear out pipestat_irq_mask[] and PIPE_FIFO_UNDERRUN_STATUS in
    vlv_display_irq_reset() (Imre)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com> (v1)
---
 drivers/gpu/drm/i915/i915_irq.c | 109 +++++++++++-----------------------------
 1 file changed, 29 insertions(+), 80 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1d21ebfffd4d..0fcd8b24a1de 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3306,13 +3306,18 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
 {
 	enum pipe pipe;
 
-	i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0);
+	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
 	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
 
-	for_each_pipe(dev_priv, pipe)
-		I915_WRITE(PIPESTAT(pipe), 0xffff);
+	for_each_pipe(dev_priv, pipe) {
+		I915_WRITE(PIPESTAT(pipe),
+			   PIPE_FIFO_UNDERRUN_STATUS |
+			   PIPESTAT_INT_STATUS_MASK);
+		dev_priv->pipestat_irq_mask[pipe] = 0;
+	}
 
 	GEN5_IRQ_RESET(VLV_);
+	dev_priv->irq_mask = ~0;
 }
 
 static void valleyview_irq_preinstall(struct drm_device *dev)
@@ -3323,7 +3328,9 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
 
 	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
 
+	spin_lock_irq(&dev_priv->irq_lock);
 	vlv_display_irq_reset(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
@@ -3398,7 +3405,9 @@ static void cherryview_irq_preinstall(struct drm_device *dev)
 
 	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
 
+	spin_lock_irq(&dev_priv->irq_lock);
 	vlv_display_irq_reset(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
 static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
@@ -3645,7 +3654,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
-static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
+static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
 {
 	u32 pipestat_mask;
 	u32 iir_mask;
@@ -3679,40 +3688,6 @@ static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
 	POSTING_READ(VLV_IMR);
 }
 
-static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
-{
-	u32 pipestat_mask;
-	u32 iir_mask;
-	enum pipe pipe;
-
-	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
-		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
-	if (IS_CHERRYVIEW(dev_priv))
-		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
-
-	dev_priv->irq_mask |= iir_mask;
-	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
-	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
-	I915_WRITE(VLV_IIR, iir_mask);
-	I915_WRITE(VLV_IIR, iir_mask);
-	POSTING_READ(VLV_IIR);
-
-	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
-			PIPE_CRC_DONE_INTERRUPT_STATUS;
-
-	i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
-	for_each_pipe(dev_priv, pipe)
-		i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
-
-	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
-			PIPE_FIFO_UNDERRUN_STATUS;
-
-	for_each_pipe(dev_priv, pipe)
-		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
-	POSTING_READ(PIPESTAT(PIPE_A));
-}
-
 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
 {
 	assert_spin_locked(&dev_priv->irq_lock);
@@ -3723,7 +3698,7 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
 	dev_priv->display_irqs_enabled = true;
 
 	if (intel_irqs_enabled(dev_priv))
-		valleyview_display_irqs_install(dev_priv);
+		vlv_display_irq_postinstall(dev_priv);
 }
 
 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
@@ -3736,36 +3711,14 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
 	dev_priv->display_irqs_enabled = false;
 
 	if (intel_irqs_enabled(dev_priv))
-		valleyview_display_irqs_uninstall(dev_priv);
+		vlv_display_irq_reset(dev_priv);
 }
 
-static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
-{
-	dev_priv->irq_mask = ~0;
-
-	i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
-	POSTING_READ(PORT_HOTPLUG_EN);
-
-	I915_WRITE(VLV_IIR, 0xffffffff);
-	I915_WRITE(VLV_IIR, 0xffffffff);
-	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
-	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
-	POSTING_READ(VLV_IMR);
-
-	/* Interrupt setup is already guaranteed to be single-threaded, this is
-	 * just to make the assert_spin_locked check happy. */
-	spin_lock_irq(&dev_priv->irq_lock);
-	if (dev_priv->display_irqs_enabled)
-		valleyview_display_irqs_install(dev_priv);
-	spin_unlock_irq(&dev_priv->irq_lock);
-}
 
 static int valleyview_irq_postinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	vlv_display_irq_postinstall(dev_priv);
-
 	gen5_gt_irq_postinstall(dev);
 
 	/* ack & enable invalid PTE error interrupts */
@@ -3774,6 +3727,10 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
 	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
 #endif
 
+	spin_lock_irq(&dev_priv->irq_lock);
+	vlv_display_irq_postinstall(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
+
 	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
 
 	return 0;
@@ -3874,10 +3831,12 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	vlv_display_irq_postinstall(dev_priv);
-
 	gen8_gt_irq_postinstall(dev_priv);
 
+	spin_lock_irq(&dev_priv->irq_lock);
+	vlv_display_irq_postinstall(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
+
 	I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
 	POSTING_READ(GEN8_MASTER_IRQ);
 
@@ -3894,20 +3853,6 @@ static void gen8_irq_uninstall(struct drm_device *dev)
 	gen8_irq_reset(dev);
 }
 
-static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
-{
-	/* Interrupt setup is already guaranteed to be single-threaded, this is
-	 * just to make the assert_spin_locked check happy. */
-	spin_lock_irq(&dev_priv->irq_lock);
-	if (dev_priv->display_irqs_enabled)
-		valleyview_display_irqs_uninstall(dev_priv);
-	spin_unlock_irq(&dev_priv->irq_lock);
-
-	vlv_display_irq_reset(dev_priv);
-
-	dev_priv->irq_mask = ~0;
-}
-
 static void valleyview_irq_uninstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3921,7 +3866,9 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
 
 	I915_WRITE(HWSTAM, 0xffffffff);
 
-	vlv_display_irq_uninstall(dev_priv);
+	spin_lock_irq(&dev_priv->irq_lock);
+	vlv_display_irq_reset(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
 static void cherryview_irq_uninstall(struct drm_device *dev)
@@ -3938,7 +3885,9 @@ static void cherryview_irq_uninstall(struct drm_device *dev)
 
 	GEN5_IRQ_RESET(GEN8_PCU_);
 
-	vlv_display_irq_uninstall(dev_priv);
+	spin_lock_irq(&dev_priv->irq_lock);
+	vlv_display_irq_reset(dev_priv);
+	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
 static void ironlake_irq_uninstall(struct drm_device *dev)
-- 
2.7.4

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[PATCH 03/10] drm/i915: Skip display irq setup if display irqs aren't flagged as enabled

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

During runtime PM we'll be reinitializing interrupt support from the
ground up. However since the display power well will be off at that
time, well end up with a ton of unclaimed register accesses from the
display irq setup. Since we turned off the power well already before
runtime suspend, we've flagged display irqs as disabled during runtime
PM transitions. So we can just check that flag to see if we should do
skip display irqs during irq setup.

During driver load display irqs will be flagged as enabled since we've
turned on the power well already, however the power well code will have
skipped the display irq setup since irq support as a whole wasn't yet
enabled when the power well was enabled. So we'll want to do the display
irq setup in that case.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94164
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index a1239fedc086..5c6511a5a74b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3326,7 +3326,8 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
 	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
 
 	spin_lock_irq(&dev_priv->irq_lock);
-	vlv_display_irq_reset(dev_priv);
+	if (dev_priv->display_irqs_enabled)
+		vlv_display_irq_reset(dev_priv);
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
@@ -3403,7 +3404,8 @@ static void cherryview_irq_preinstall(struct drm_device *dev)
 	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
 
 	spin_lock_irq(&dev_priv->irq_lock);
-	vlv_display_irq_reset(dev_priv);
+	if (dev_priv->display_irqs_enabled)
+		vlv_display_irq_reset(dev_priv);
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
@@ -3725,7 +3727,8 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
 #endif
 
 	spin_lock_irq(&dev_priv->irq_lock);
-	vlv_display_irq_postinstall(dev_priv);
+	if (dev_priv->display_irqs_enabled)
+		vlv_display_irq_postinstall(dev_priv);
 	spin_unlock_irq(&dev_priv->irq_lock);
 
 	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
@@ -3831,7 +3834,8 @@ static int cherryview_irq_postinstall(struct drm_device *dev)
 	gen8_gt_irq_postinstall(dev_priv);
 
 	spin_lock_irq(&dev_priv->irq_lock);
-	vlv_display_irq_postinstall(dev_priv);
+	if (dev_priv->display_irqs_enabled)
+		vlv_display_irq_postinstall(dev_priv);
 	spin_unlock_irq(&dev_priv->irq_lock);
 
 	I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
@@ -3864,7 +3868,8 @@ static void valleyview_irq_uninstall(struct drm_device *dev)
 	I915_WRITE(HWSTAM, 0xffffffff);
 
 	spin_lock_irq(&dev_priv->irq_lock);
-	vlv_display_irq_reset(dev_priv);
+	if (dev_priv->display_irqs_enabled)
+		vlv_display_irq_reset(dev_priv);
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
@@ -3883,7 +3888,8 @@ static void cherryview_irq_uninstall(struct drm_device *dev)
 	GEN5_IRQ_RESET(GEN8_PCU_);
 
 	spin_lock_irq(&dev_priv->irq_lock);
-	vlv_display_irq_reset(dev_priv);
+	if (dev_priv->display_irqs_enabled)
+		vlv_display_irq_reset(dev_priv);
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
-- 
2.7.4

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Re: [PATCH 03/10] drm/i915: Skip display irq setup if display irqs aren't flagged as enabled

[Imre Deak]

On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> During runtime PM we'll be reinitializing interrupt support from the
> ground up. However since the display power well will be off at that
> time, well end up with a ton of unclaimed register accesses from the
> display irq setup. Since we turned off the power well already before
> runtime suspend, we've flagged display irqs as disabled during runtime
> PM transitions. So we can just check that flag to see if we should do
> skip display irqs during irq setup.
> 
> During driver load display irqs will be flagged as enabled since we've
> turned on the power well already, however the power well code will have
> skipped the display irq setup since irq support as a whole wasn't yet
> enabled when the power well was enabled. So we'll want to do the display
> irq setup in that case.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94164
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 18 ++++++++++++------
>  1 file changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index a1239fedc086..5c6511a5a74b 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3326,7 +3326,8 @@ static void valleyview_irq_preinstall(struct
> drm_device *dev)
>  	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
>  
>  	spin_lock_irq(&dev_priv->irq_lock);
> -	vlv_display_irq_reset(dev_priv);
> +	if (dev_priv->display_irqs_enabled)
> +		vlv_display_irq_reset(dev_priv);
>  	spin_unlock_irq(&dev_priv->irq_lock);
>  }
>  
> @@ -3403,7 +3404,8 @@ static void cherryview_irq_preinstall(struct
> drm_device *dev)
>  	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
>  
>  	spin_lock_irq(&dev_priv->irq_lock);
> -	vlv_display_irq_reset(dev_priv);
> +	if (dev_priv->display_irqs_enabled)
> +		vlv_display_irq_reset(dev_priv);
>  	spin_unlock_irq(&dev_priv->irq_lock);
>  }
>  
> @@ -3725,7 +3727,8 @@ static int valleyview_irq_postinstall(struct
> drm_device *dev)
>  #endif
>  
>  	spin_lock_irq(&dev_priv->irq_lock);
> -	vlv_display_irq_postinstall(dev_priv);
> +	if (dev_priv->display_irqs_enabled)
> +		vlv_display_irq_postinstall(dev_priv);
>  	spin_unlock_irq(&dev_priv->irq_lock);
>  
>  	I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
> @@ -3831,7 +3834,8 @@ static int cherryview_irq_postinstall(struct
> drm_device *dev)
>  	gen8_gt_irq_postinstall(dev_priv);
>  
>  	spin_lock_irq(&dev_priv->irq_lock);
> -	vlv_display_irq_postinstall(dev_priv);
> +	if (dev_priv->display_irqs_enabled)
> +		vlv_display_irq_postinstall(dev_priv);
>  	spin_unlock_irq(&dev_priv->irq_lock);
>  
>  	I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
> @@ -3864,7 +3868,8 @@ static void valleyview_irq_uninstall(struct
> drm_device *dev)
>  	I915_WRITE(HWSTAM, 0xffffffff);
>  
>  	spin_lock_irq(&dev_priv->irq_lock);
> -	vlv_display_irq_reset(dev_priv);
> +	if (dev_priv->display_irqs_enabled)
> +		vlv_display_irq_reset(dev_priv);
>  	spin_unlock_irq(&dev_priv->irq_lock);
>  }
>  
> @@ -3883,7 +3888,8 @@ static void cherryview_irq_uninstall(struct
> drm_device *dev)
>  	GEN5_IRQ_RESET(GEN8_PCU_);
>  
>  	spin_lock_irq(&dev_priv->irq_lock);
> -	vlv_display_irq_reset(dev_priv);
> +	if (dev_priv->display_irqs_enabled)
> +		vlv_display_irq_reset(dev_priv);
>  	spin_unlock_irq(&dev_priv->irq_lock);
>  }
>  
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[PATCH 04/10] drm/i915: Move vlv/chv display irq code to a more logical place

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reshuffle the code a bit to move the vlv/chv display irq functions away
from the main irq hooks, next to the other sub (de,gt,etc.) hooks.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 98 ++++++++++++++++++++---------------------
 1 file changed, 49 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5c6511a5a74b..c119610e2d57 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3285,6 +3285,55 @@ static void gen5_gt_irq_reset(struct drm_device *dev)
 		GEN5_IRQ_RESET(GEN6_PM);
 }
 
+static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
+{
+	enum pipe pipe;
+
+	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
+	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
+
+	for_each_pipe(dev_priv, pipe)
+		I915_WRITE(PIPESTAT(pipe), 0xffff);
+
+	GEN5_IRQ_RESET(VLV_);
+
+	dev_priv->irq_mask = ~0;
+}
+
+static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+	u32 pipestat_mask;
+	u32 iir_mask;
+	enum pipe pipe;
+
+	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
+			PIPE_FIFO_UNDERRUN_STATUS;
+
+	for_each_pipe(dev_priv, pipe)
+		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
+	POSTING_READ(PIPESTAT(PIPE_A));
+
+	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
+			PIPE_CRC_DONE_INTERRUPT_STATUS;
+
+	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
+	for_each_pipe(dev_priv, pipe)
+		i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
+
+	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
+		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
+	if (IS_CHERRYVIEW(dev_priv))
+		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
+	dev_priv->irq_mask &= ~iir_mask;
+
+	I915_WRITE(VLV_IIR, iir_mask);
+	I915_WRITE(VLV_IIR, iir_mask);
+	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
+	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
+	POSTING_READ(VLV_IMR);
+}
+
 /* drm_dma.h hooks
 */
 static void ironlake_irq_reset(struct drm_device *dev)
@@ -3302,21 +3351,6 @@ static void ironlake_irq_reset(struct drm_device *dev)
 	ibx_irq_reset(dev);
 }
 
-static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
-{
-	enum pipe pipe;
-
-	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
-	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
-
-	for_each_pipe(dev_priv, pipe)
-		I915_WRITE(PIPESTAT(pipe), 0xffff);
-
-	GEN5_IRQ_RESET(VLV_);
-
-	dev_priv->irq_mask = ~0;
-}
-
 static void valleyview_irq_preinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3653,40 +3687,6 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
-static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
-{
-	u32 pipestat_mask;
-	u32 iir_mask;
-	enum pipe pipe;
-
-	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
-			PIPE_FIFO_UNDERRUN_STATUS;
-
-	for_each_pipe(dev_priv, pipe)
-		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
-	POSTING_READ(PIPESTAT(PIPE_A));
-
-	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
-			PIPE_CRC_DONE_INTERRUPT_STATUS;
-
-	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
-	for_each_pipe(dev_priv, pipe)
-		      i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
-
-	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
-		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
-	if (IS_CHERRYVIEW(dev_priv))
-		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
-	dev_priv->irq_mask &= ~iir_mask;
-
-	I915_WRITE(VLV_IIR, iir_mask);
-	I915_WRITE(VLV_IIR, iir_mask);
-	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
-	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
-	POSTING_READ(VLV_IMR);
-}
-
 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
 {
 	assert_spin_locked(&dev_priv->irq_lock);
-- 
2.7.4

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Re: [PATCH 04/10] drm/i915: Move vlv/chv display irq code to a more logical place

[Imre Deak]

On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reshuffle the code a bit to move the vlv/chv display irq functions
> away
> from the main irq hooks, next to the other sub (de,gt,etc.) hooks.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 98 ++++++++++++++++++++-----------
> ----------
>  1 file changed, 49 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 5c6511a5a74b..c119610e2d57 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3285,6 +3285,55 @@ static void gen5_gt_irq_reset(struct
> drm_device *dev)
>  		GEN5_IRQ_RESET(GEN6_PM);
>  }
>  
> +static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
> +{
> +	enum pipe pipe;
> +
> +	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff,
> 0);
> +	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
> +
> +	for_each_pipe(dev_priv, pipe)
> +		I915_WRITE(PIPESTAT(pipe), 0xffff);
> +
> +	GEN5_IRQ_RESET(VLV_);
> +
> +	dev_priv->irq_mask = ~0;
> +}
> +
> +static void vlv_display_irq_postinstall(struct drm_i915_private
> *dev_priv)
> +{
> +	u32 pipestat_mask;
> +	u32 iir_mask;
> +	enum pipe pipe;
> +
> +	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
> +			PIPE_FIFO_UNDERRUN_STATUS;
> +
> +	for_each_pipe(dev_priv, pipe)
> +		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
> +	POSTING_READ(PIPESTAT(PIPE_A));
> +
> +	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
> +			PIPE_CRC_DONE_INTERRUPT_STATUS;
> +
> +	i915_enable_pipestat(dev_priv, PIPE_A,
> PIPE_GMBUS_INTERRUPT_STATUS);
> +	for_each_pipe(dev_priv, pipe)
> +		i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
> +
> +	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
> +		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
> +		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
> +	if (IS_CHERRYVIEW(dev_priv))
> +		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
> +	dev_priv->irq_mask &= ~iir_mask;
> +
> +	I915_WRITE(VLV_IIR, iir_mask);
> +	I915_WRITE(VLV_IIR, iir_mask);
> +	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
> +	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
> +	POSTING_READ(VLV_IMR);
> +}
> +
>  /* drm_dma.h hooks
>  */
>  static void ironlake_irq_reset(struct drm_device *dev)
> @@ -3302,21 +3351,6 @@ static void ironlake_irq_reset(struct
> drm_device *dev)
>  	ibx_irq_reset(dev);
>  }
>  
> -static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
> -{
> -	enum pipe pipe;
> -
> -	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff,
> 0);
> -	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
> -
> -	for_each_pipe(dev_priv, pipe)
> -		I915_WRITE(PIPESTAT(pipe), 0xffff);
> -
> -	GEN5_IRQ_RESET(VLV_);
> -
> -	dev_priv->irq_mask = ~0;
> -}
> -
>  static void valleyview_irq_preinstall(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3653,40 +3687,6 @@ static int ironlake_irq_postinstall(struct
> drm_device *dev)
>  	return 0;
>  }
>  
> -static void vlv_display_irq_postinstall(struct drm_i915_private
> *dev_priv)
> -{
> -	u32 pipestat_mask;
> -	u32 iir_mask;
> -	enum pipe pipe;
> -
> -	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
> -			PIPE_FIFO_UNDERRUN_STATUS;
> -
> -	for_each_pipe(dev_priv, pipe)
> -		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
> -	POSTING_READ(PIPESTAT(PIPE_A));
> -
> -	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
> -			PIPE_CRC_DONE_INTERRUPT_STATUS;
> -
> -	i915_enable_pipestat(dev_priv, PIPE_A,
> PIPE_GMBUS_INTERRUPT_STATUS);
> -	for_each_pipe(dev_priv, pipe)
> -		      i915_enable_pipestat(dev_priv, pipe,
> pipestat_mask);
> -
> -	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
> -		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
> -		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
> -	if (IS_CHERRYVIEW(dev_priv))
> -		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
> -	dev_priv->irq_mask &= ~iir_mask;
> -
> -	I915_WRITE(VLV_IIR, iir_mask);
> -	I915_WRITE(VLV_IIR, iir_mask);
> -	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
> -	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
> -	POSTING_READ(VLV_IMR);
> -}
> -
>  void valleyview_enable_display_irqs(struct drm_i915_private
> *dev_priv)
>  {
>  	assert_spin_locked(&dev_priv->irq_lock);
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[PATCH v2 04/10] drm/i915: Move vlv/chv display irq code to a more logical place

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reshuffle the code a bit to move the vlv/chv display irq functions away
from the main irq hooks, next to the other sub (de,gt,etc.) hooks.

v2: Rebased due to changes in vlv_display_irq_reset()

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com> (v1)
---
 drivers/gpu/drm/i915/i915_irq.c | 102 ++++++++++++++++++++--------------------
 1 file changed, 51 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 68981aee35b7..6885c0d12167 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3285,23 +3285,6 @@ static void gen5_gt_irq_reset(struct drm_device *dev)
 		GEN5_IRQ_RESET(GEN6_PM);
 }
 
-/* drm_dma.h hooks
-*/
-static void ironlake_irq_reset(struct drm_device *dev)
-{
-	struct drm_i915_private *dev_priv = dev->dev_private;
-
-	I915_WRITE(HWSTAM, 0xffffffff);
-
-	GEN5_IRQ_RESET(DE);
-	if (IS_GEN7(dev))
-		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
-
-	gen5_gt_irq_reset(dev);
-
-	ibx_irq_reset(dev);
-}
-
 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
 {
 	enum pipe pipe;
@@ -3320,6 +3303,57 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
 	dev_priv->irq_mask = ~0;
 }
 
+static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+	u32 pipestat_mask;
+	u32 iir_mask;
+	enum pipe pipe;
+
+	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
+			PIPE_FIFO_UNDERRUN_STATUS;
+
+	for_each_pipe(dev_priv, pipe)
+		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
+	POSTING_READ(PIPESTAT(PIPE_A));
+
+	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
+			PIPE_CRC_DONE_INTERRUPT_STATUS;
+
+	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
+	for_each_pipe(dev_priv, pipe)
+		i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
+
+	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
+		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
+	if (IS_CHERRYVIEW(dev_priv))
+		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
+	dev_priv->irq_mask &= ~iir_mask;
+
+	I915_WRITE(VLV_IIR, iir_mask);
+	I915_WRITE(VLV_IIR, iir_mask);
+	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
+	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
+	POSTING_READ(VLV_IMR);
+}
+
+/* drm_dma.h hooks
+*/
+static void ironlake_irq_reset(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	I915_WRITE(HWSTAM, 0xffffffff);
+
+	GEN5_IRQ_RESET(DE);
+	if (IS_GEN7(dev))
+		I915_WRITE(GEN7_ERR_INT, 0xffffffff);
+
+	gen5_gt_irq_reset(dev);
+
+	ibx_irq_reset(dev);
+}
+
 static void valleyview_irq_preinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3656,40 +3690,6 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
-static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
-{
-	u32 pipestat_mask;
-	u32 iir_mask;
-	enum pipe pipe;
-
-	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
-			PIPE_FIFO_UNDERRUN_STATUS;
-
-	for_each_pipe(dev_priv, pipe)
-		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
-	POSTING_READ(PIPESTAT(PIPE_A));
-
-	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
-			PIPE_CRC_DONE_INTERRUPT_STATUS;
-
-	i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
-	for_each_pipe(dev_priv, pipe)
-		      i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
-
-	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
-		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
-	if (IS_CHERRYVIEW(dev_priv))
-		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
-	dev_priv->irq_mask &= ~iir_mask;
-
-	I915_WRITE(VLV_IIR, iir_mask);
-	I915_WRITE(VLV_IIR, iir_mask);
-	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
-	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
-	POSTING_READ(VLV_IMR);
-}
-
 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
 {
 	assert_spin_locked(&dev_priv->irq_lock);
-- 
2.7.4

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[PATCH 05/10] drm/i915: Clear display interrupt before enabling when turning on the power well

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

For a bit of extra paranoia make sure the display irqs are all cleared
before we enabled them when turning on the power well. This should
really be the case already since the power well was off which resets
everything.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c119610e2d57..678c6b86862e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3306,13 +3306,6 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
 	u32 iir_mask;
 	enum pipe pipe;
 
-	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
-			PIPE_FIFO_UNDERRUN_STATUS;
-
-	for_each_pipe(dev_priv, pipe)
-		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
-	POSTING_READ(PIPESTAT(PIPE_A));
-
 	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
 			PIPE_CRC_DONE_INTERRUPT_STATUS;
 
@@ -3696,8 +3689,10 @@ void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
 
 	dev_priv->display_irqs_enabled = true;
 
-	if (intel_irqs_enabled(dev_priv))
+	if (intel_irqs_enabled(dev_priv)) {
+		vlv_display_irq_reset(dev_priv);
 		vlv_display_irq_postinstall(dev_priv);
+	}
 }
 
 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
-- 
2.7.4

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Re: [PATCH 05/10] drm/i915: Clear display interrupt before enabling when turning on the power well

[Imre Deak]

On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> For a bit of extra paranoia make sure the display irqs are all
> cleared
> before we enabled them when turning on the power well. This should
> really be the case already since the power well was off which resets
> everything.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 11 +++--------
>  1 file changed, 3 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index c119610e2d57..678c6b86862e 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3306,13 +3306,6 @@ static void vlv_display_irq_postinstall(struct
> drm_i915_private *dev_priv)
>  	u32 iir_mask;
>  	enum pipe pipe;
>  
> -	pipestat_mask = PIPESTAT_INT_STATUS_MASK |
> -			PIPE_FIFO_UNDERRUN_STATUS;
> -
> -	for_each_pipe(dev_priv, pipe)
> -		I915_WRITE(PIPESTAT(pipe), pipestat_mask);
> -	POSTING_READ(PIPESTAT(PIPE_A));
> -
>  	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
>  			PIPE_CRC_DONE_INTERRUPT_STATUS;
>  
> @@ -3696,8 +3689,10 @@ void valleyview_enable_display_irqs(struct
> drm_i915_private *dev_priv)
>  
>  	dev_priv->display_irqs_enabled = true;
>  
> -	if (intel_irqs_enabled(dev_priv))
> +	if (intel_irqs_enabled(dev_priv)) {
> +		vlv_display_irq_reset(dev_priv);
>  		vlv_display_irq_postinstall(dev_priv);
> +	}
>  }
>  
>  void valleyview_disable_display_irqs(struct drm_i915_private
> *dev_priv)
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[PATCH 06/10] drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Replace the hand rolled IMR/IER setup in vlv_display_irq_postinstall()
with GEN5_IRQ_INIT(). Also rename the iir_mask to enable_mask to avoid
consusion since we no longer deal with IIR here.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 20 ++++++++------------
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 678c6b86862e..f6815e47d8de 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3303,7 +3303,7 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
 {
 	u32 pipestat_mask;
-	u32 iir_mask;
+	u32 enable_mask;
 	enum pipe pipe;
 
 	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
@@ -3313,18 +3313,14 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
 	for_each_pipe(dev_priv, pipe)
 		i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
 
-	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
-		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
-		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
+	enable_mask = I915_DISPLAY_PORT_INTERRUPT |
+		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
+		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
 	if (IS_CHERRYVIEW(dev_priv))
-		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
-	dev_priv->irq_mask &= ~iir_mask;
-
-	I915_WRITE(VLV_IIR, iir_mask);
-	I915_WRITE(VLV_IIR, iir_mask);
-	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
-	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
-	POSTING_READ(VLV_IMR);
+		enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
+	dev_priv->irq_mask = ~enable_mask;
+
+	GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
 }
 
 /* drm_dma.h hooks
-- 
2.7.4

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Re: [PATCH 06/10] drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall()

[Imre Deak]

On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Replace the hand rolled IMR/IER setup in
> vlv_display_irq_postinstall()
> with GEN5_IRQ_INIT(). Also rename the iir_mask to enable_mask to
> avoid
> consusion since we no longer deal with IIR here.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 20 ++++++++------------
>  1 file changed, 8 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 678c6b86862e..f6815e47d8de 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3303,7 +3303,7 @@ static void vlv_display_irq_reset(struct
> drm_i915_private *dev_priv)
>  static void vlv_display_irq_postinstall(struct drm_i915_private
> *dev_priv)
>  {
>  	u32 pipestat_mask;
> -	u32 iir_mask;
> +	u32 enable_mask;
>  	enum pipe pipe;
>  
>  	pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
> @@ -3313,18 +3313,14 @@ static void
> vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
>  	for_each_pipe(dev_priv, pipe)
>  		i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
>  
> -	iir_mask = I915_DISPLAY_PORT_INTERRUPT |
> -		   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
> -		   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
> +	enable_mask = I915_DISPLAY_PORT_INTERRUPT |
> +		I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
> +		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
>  	if (IS_CHERRYVIEW(dev_priv))
> -		iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
> -	dev_priv->irq_mask &= ~iir_mask;
> -
> -	I915_WRITE(VLV_IIR, iir_mask);
> -	I915_WRITE(VLV_IIR, iir_mask);
> -	I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
> -	I915_WRITE(VLV_IMR, dev_priv->irq_mask);
> -	POSTING_READ(VLV_IMR);
> +		enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
> +	dev_priv->irq_mask = ~enable_mask;
> +
> +	GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
>  }
>  
>  /* drm_dma.h hooks
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[PATCH 07/10] drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq postinstall

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We expect vlv_display_irq_reset() to have been called prior to
vlv_display_irq_postinstall() so let's WARN if that isn't the case.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f6815e47d8de..872f93dc68ff 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3318,6 +3318,9 @@ static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
 		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
 	if (IS_CHERRYVIEW(dev_priv))
 		enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
+
+	WARN_ON(dev_priv->irq_mask != ~0);
+
 	dev_priv->irq_mask = ~enable_mask;
 
 	GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
-- 
2.7.4

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Re: [PATCH 07/10] drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq postinstall

[Imre Deak]

On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We expect vlv_display_irq_reset() to have been called prior to
> vlv_display_irq_postinstall() so let's WARN if that isn't the case.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index f6815e47d8de..872f93dc68ff 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3318,6 +3318,9 @@ static void vlv_display_irq_postinstall(struct
> drm_i915_private *dev_priv)
>  		I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
>  	if (IS_CHERRYVIEW(dev_priv))
>  		enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
> +
> +	WARN_ON(dev_priv->irq_mask != ~0);
> +
>  	dev_priv->irq_mask = ~enable_mask;
>  
>  	GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
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[PATCH 08/10] drm/i915: Move vlv_init_display_clock_gating() to the display power well

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The registers frobbed by vlv_init_display_clock_gating() libve inside
the disp2d power well, so frobbing them while the power well is down
results in unclaimed register access warning (and of course the values
won't stick). Let's do this setup after we know the power well is
enabled.

It's also worth noting that DSPCLK_GATE_D and CBR1_VLV lose their state
when the power well goes down, but fortunately the values we've been
writing are actually the reset defaults.

MI_ARB_VLV actually retains its value even if the power well was turned
off, we just can't access it while the power well is down.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94164
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c         | 15 ---------------
 drivers/gpu/drm/i915/intel_runtime_pm.c | 13 +++++++++++++
 2 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 43b24a1f5ee6..c80d044fe082 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6882,23 +6882,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
 	gen6_check_mch_setup(dev);
 }
 
-static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
-{
-	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
-
-	/*
-	 * Disable trickle feed and enable pnd deadline calculation
-	 */
-	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
-	I915_WRITE(CBR1_VLV, 0);
-}
-
 static void valleyview_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	vlv_init_display_clock_gating(dev_priv);
-
 	/* WaDisableEarlyCull:vlv */
 	I915_WRITE(_3D_CHICKEN3,
 		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
@@ -6981,8 +6968,6 @@ static void cherryview_init_clock_gating(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	vlv_init_display_clock_gating(dev_priv);
-
 	/* WaVSRefCountFullforceMissDisable:chv */
 	/* WaDSRefCountFullforceMissDisable:chv */
 	I915_WRITE(GEN7_FF_THREAD_MODE,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 80e8bd4b43b5..8f9797f17991 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -900,6 +900,17 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 	return enabled;
 }
 
+static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
+{
+	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
+
+	/*
+	 * Disable trickle feed and enable pnd deadline calculation
+	 */
+	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
+	I915_WRITE(CBR1_VLV, 0);
+}
+
 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 {
 	enum pipe pipe;
@@ -922,6 +933,8 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 		I915_WRITE(DPLL(pipe), val);
 	}
 
+	vlv_init_display_clock_gating(dev_priv);
+
 	spin_lock_irq(&dev_priv->irq_lock);
 	valleyview_enable_display_irqs(dev_priv);
 	spin_unlock_irq(&dev_priv->irq_lock);
-- 
2.7.4

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Re: [PATCH 08/10] drm/i915: Move vlv_init_display_clock_gating() to the display power well

[Imre Deak]

On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The registers frobbed by vlv_init_display_clock_gating() libve inside
> the disp2d power well, so frobbing them while the power well is down
> results in unclaimed register access warning (and of course the
> values
> won't stick). Let's do this setup after we know the power well is
> enabled.
> 
> It's also worth noting that DSPCLK_GATE_D and CBR1_VLV lose their
> state
> when the power well goes down, but fortunately the values we've been
> writing are actually the reset defaults.
> 
> MI_ARB_VLV actually retains its value even if the power well was
> turned
> off, we just can't access it while the power well is down.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94164
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

The spec doesn't say anything about backing power wells, I assume you
checked this manually by reading the regs out while the power well was 
off. Looks ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c         | 15 ---------------
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 13 +++++++++++++
>  2 files changed, 13 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 43b24a1f5ee6..c80d044fe082 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6882,23 +6882,10 @@ static void
> ivybridge_init_clock_gating(struct drm_device *dev)
>  	gen6_check_mch_setup(dev);
>  }
>  
> -static void vlv_init_display_clock_gating(struct drm_i915_private
> *dev_priv)
> -{
> -	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> -
> -	/*
> -	 * Disable trickle feed and enable pnd deadline calculation
> -	 */
> -	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> -	I915_WRITE(CBR1_VLV, 0);
> -}
> -
>  static void valleyview_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	vlv_init_display_clock_gating(dev_priv);
> -
>  	/* WaDisableEarlyCull:vlv */
>  	I915_WRITE(_3D_CHICKEN3,
>  		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_
> CULL));
> @@ -6981,8 +6968,6 @@ static void cherryview_init_clock_gating(struct
> drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	vlv_init_display_clock_gating(dev_priv);
> -
>  	/* WaVSRefCountFullforceMissDisable:chv */
>  	/* WaDSRefCountFullforceMissDisable:chv */
>  	I915_WRITE(GEN7_FF_THREAD_MODE,
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 80e8bd4b43b5..8f9797f17991 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -900,6 +900,17 @@ static bool vlv_power_well_enabled(struct
> drm_i915_private *dev_priv,
>  	return enabled;
>  }
>  
> +static void vlv_init_display_clock_gating(struct drm_i915_private
> *dev_priv)
> +{
> +	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> +
> +	/*
> +	 * Disable trickle feed and enable pnd deadline calculation
> +	 */
> +	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> +	I915_WRITE(CBR1_VLV, 0);
> +}
> +
>  static void vlv_display_power_well_init(struct drm_i915_private
> *dev_priv)
>  {
>  	enum pipe pipe;
> @@ -922,6 +933,8 @@ static void vlv_display_power_well_init(struct
> drm_i915_private *dev_priv)
>  		I915_WRITE(DPLL(pipe), val);
>  	}
>  
> +	vlv_init_display_clock_gating(dev_priv);
> +
>  	spin_lock_irq(&dev_priv->irq_lock);
>  	valleyview_enable_display_irqs(dev_priv);
>  	spin_unlock_irq(&dev_priv->irq_lock);
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Re: [PATCH 08/10] drm/i915: Move vlv_init_display_clock_gating() to the display power well

[Ville Syrjälä]

On Tue, Apr 12, 2016 at 01:25:07PM +0300, Imre Deak wrote:
> On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The registers frobbed by vlv_init_display_clock_gating() libve inside
> > the disp2d power well, so frobbing them while the power well is down
> > results in unclaimed register access warning (and of course the
> > values
> > won't stick). Let's do this setup after we know the power well is
> > enabled.
> > 
> > It's also worth noting that DSPCLK_GATE_D and CBR1_VLV lose their
> > state
> > when the power well goes down, but fortunately the values we've been
> > writing are actually the reset defaults.
> > 
> > MI_ARB_VLV actually retains its value even if the power well was
> > turned
> > off, we just can't access it while the power well is down.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94164
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The spec doesn't say anything about backing power wells, I assume you
> checked this manually by reading the regs out while the power well was 
> off.

Yep.

> Looks ok:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c         | 15 ---------------
> >  drivers/gpu/drm/i915/intel_runtime_pm.c | 13 +++++++++++++
> >  2 files changed, 13 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 43b24a1f5ee6..c80d044fe082 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6882,23 +6882,10 @@ static void
> > ivybridge_init_clock_gating(struct drm_device *dev)
> >  	gen6_check_mch_setup(dev);
> >  }
> >  
> > -static void vlv_init_display_clock_gating(struct drm_i915_private
> > *dev_priv)
> > -{
> > -	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> > -
> > -	/*
> > -	 * Disable trickle feed and enable pnd deadline calculation
> > -	 */
> > -	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> > -	I915_WRITE(CBR1_VLV, 0);
> > -}
> > -
> >  static void valleyview_init_clock_gating(struct drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  
> > -	vlv_init_display_clock_gating(dev_priv);
> > -
> >  	/* WaDisableEarlyCull:vlv */
> >  	I915_WRITE(_3D_CHICKEN3,
> >  		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_
> > CULL));
> > @@ -6981,8 +6968,6 @@ static void cherryview_init_clock_gating(struct
> > drm_device *dev)
> >  {
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  
> > -	vlv_init_display_clock_gating(dev_priv);
> > -
> >  	/* WaVSRefCountFullforceMissDisable:chv */
> >  	/* WaDSRefCountFullforceMissDisable:chv */
> >  	I915_WRITE(GEN7_FF_THREAD_MODE,
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 80e8bd4b43b5..8f9797f17991 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -900,6 +900,17 @@ static bool vlv_power_well_enabled(struct
> > drm_i915_private *dev_priv,
> >  	return enabled;
> >  }
> >  
> > +static void vlv_init_display_clock_gating(struct drm_i915_private
> > *dev_priv)
> > +{
> > +	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
> > +
> > +	/*
> > +	 * Disable trickle feed and enable pnd deadline calculation
> > +	 */
> > +	I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> > +	I915_WRITE(CBR1_VLV, 0);
> > +}
> > +
> >  static void vlv_display_power_well_init(struct drm_i915_private
> > *dev_priv)
> >  {
> >  	enum pipe pipe;
> > @@ -922,6 +933,8 @@ static void vlv_display_power_well_init(struct
> > drm_i915_private *dev_priv)
> >  		I915_WRITE(DPLL(pipe), val);
> >  	}
> >  
> > +	vlv_init_display_clock_gating(dev_priv);
> > +
> >  	spin_lock_irq(&dev_priv->irq_lock);
> >  	valleyview_enable_display_irqs(dev_priv);
> >  	spin_unlock_irq(&dev_priv->irq_lock);

-- 
Ville Syrjälä
Intel OTC
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[PATCH 09/10] drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

DPINVGTT lives inside the disp2d power well so we can't frob it unless
we know the power well is active. Let's this stuff into
vlv_display_irq_reset() which is only called at the right times so that
we don't get unclaimed register access errors.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94164
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 15 +++++----------
 1 file changed, 5 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 872f93dc68ff..d60c0e53f929 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3289,6 +3289,11 @@ static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
 {
 	enum pipe pipe;
 
+	if (IS_CHERRYVIEW(dev_priv))
+		I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
+	else
+		I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
+
 	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
 	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
 
@@ -3349,8 +3354,6 @@ static void valleyview_irq_preinstall(struct drm_device *dev)
 
 	gen5_gt_irq_reset(dev);
 
-	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
-
 	spin_lock_irq(&dev_priv->irq_lock);
 	if (dev_priv->display_irqs_enabled)
 		vlv_display_irq_reset(dev_priv);
@@ -3427,8 +3430,6 @@ static void cherryview_irq_preinstall(struct drm_device *dev)
 
 	GEN5_IRQ_RESET(GEN8_PCU_);
 
-	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
-
 	spin_lock_irq(&dev_priv->irq_lock);
 	if (dev_priv->display_irqs_enabled)
 		vlv_display_irq_reset(dev_priv);
@@ -3714,12 +3715,6 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
 
 	gen5_gt_irq_postinstall(dev);
 
-	/* ack & enable invalid PTE error interrupts */
-#if 0 /* FIXME: add support to irq handler for checking these bits */
-	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
-	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
-#endif
-
 	spin_lock_irq(&dev_priv->irq_lock);
 	if (dev_priv->display_irqs_enabled)
 		vlv_display_irq_postinstall(dev_priv);
-- 
2.7.4

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Re: [PATCH 09/10] drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()

[Imre Deak]

On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> DPINVGTT lives inside the disp2d power well so we can't frob it unless
> we know the power well is active. Let's this stuff into
> vlv_display_irq_reset() which is only called at the right times so that
> we don't get unclaimed register access errors.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94164
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_irq.c | 15 +++++----------
>  1 file changed, 5 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 872f93dc68ff..d60c0e53f929 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3289,6 +3289,11 @@ static void vlv_display_irq_reset(struct
> drm_i915_private *dev_priv)
>  {
>  	enum pipe pipe;
>  
> +	if (IS_CHERRYVIEW(dev_priv))
> +		I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
> +	else
> +		I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
> +
>  	i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff,
> 0);
>  	I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
>  
> @@ -3349,8 +3354,6 @@ static void valleyview_irq_preinstall(struct
> drm_device *dev)
>  
>  	gen5_gt_irq_reset(dev);
>  
> -	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
> -
>  	spin_lock_irq(&dev_priv->irq_lock);
>  	if (dev_priv->display_irqs_enabled)
>  		vlv_display_irq_reset(dev_priv);
> @@ -3427,8 +3430,6 @@ static void cherryview_irq_preinstall(struct
> drm_device *dev)
>  
>  	GEN5_IRQ_RESET(GEN8_PCU_);
>  
> -	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
> -
>  	spin_lock_irq(&dev_priv->irq_lock);
>  	if (dev_priv->display_irqs_enabled)
>  		vlv_display_irq_reset(dev_priv);
> @@ -3714,12 +3715,6 @@ static int valleyview_irq_postinstall(struct
> drm_device *dev)
>  
>  	gen5_gt_irq_postinstall(dev);
>  
> -	/* ack & enable invalid PTE error interrupts */
> -#if 0 /* FIXME: add support to irq handler for checking these bits
> */
> -	I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
> -	I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
> -#endif
> -
>  	spin_lock_irq(&dev_priv->irq_lock);
>  	if (dev_priv->display_irqs_enabled)
>  		vlv_display_irq_postinstall(dev_priv);
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[PATCH 10/10] Revert "drm/i915: Limit the auto arming of mmio debugs on vlv/chv"

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Enable the unclaimd register detection stuff on vlv/chv since we've now
fixed the known problems during suspend.

This reverts commit c81eeea6c14b212016104f4256c65f93ad230a86.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index ac2ac07b505b..2f7fb7d169b8 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -633,15 +633,6 @@ __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
 		      const bool read,
 		      const bool before)
 {
-	/* XXX. We limit the auto arming traces for mmio
-	 * debugs on these platforms. There are just too many
-	 * revealed by these and CI/Bat suffers from the noise.
-	 * Please fix and then re-enable the automatic traces.
-	 */
-	if (i915.mmio_debug < 2 &&
-	    (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
-		return;
-
 	if (WARN(check_for_unclaimed_mmio(dev_priv),
 		 "Unclaimed register detected %s %s register 0x%x\n",
 		 before ? "before" : "after",
-- 
2.7.4

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Re: [PATCH 10/10] Revert "drm/i915: Limit the auto arming of mmio debugs on vlv/chv"

[Imre Deak]

On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Enable the unclaimd register detection stuff on vlv/chv since we've
> now
> fixed the known problems during suspend.
> 
> This reverts commit c81eeea6c14b212016104f4256c65f93ad230a86.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_uncore.c | 9 ---------
>  1 file changed, 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index ac2ac07b505b..2f7fb7d169b8 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -633,15 +633,6 @@ __unclaimed_reg_debug(struct drm_i915_private
> *dev_priv,
>  		      const bool read,
>  		      const bool before)
>  {
> -	/* XXX. We limit the auto arming traces for mmio
> -	 * debugs on these platforms. There are just too many
> -	 * revealed by these and CI/Bat suffers from the noise.
> -	 * Please fix and then re-enable the automatic traces.
> -	 */
> -	if (i915.mmio_debug < 2 &&
> -	    (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
> -		return;
> -
>  	if (WARN(check_for_unclaimed_mmio(dev_priv),
>  		 "Unclaimed register detected %s %s register
> 0x%x\n",
>  		 before ? "before" : "after",
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Re: [PATCH 10/10] Revert "drm/i915: Limit the auto arming of mmio debugs on vlv/chv"

[Ville Syrjälä]

On Tue, Apr 12, 2016 at 03:04:10PM +0300, Imre Deak wrote:
> On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Enable the unclaimd register detection stuff on vlv/chv since we've
> > now
> > fixed the known problems during suspend.
> > 
> > This reverts commit c81eeea6c14b212016104f4256c65f93ad230a86.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Entire series pushed to dinq. Thanks for the reviews.

> 
> > ---
> >  drivers/gpu/drm/i915/intel_uncore.c | 9 ---------
> >  1 file changed, 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> > b/drivers/gpu/drm/i915/intel_uncore.c
> > index ac2ac07b505b..2f7fb7d169b8 100644
> > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > @@ -633,15 +633,6 @@ __unclaimed_reg_debug(struct drm_i915_private
> > *dev_priv,
> >  		      const bool read,
> >  		      const bool before)
> >  {
> > -	/* XXX. We limit the auto arming traces for mmio
> > -	 * debugs on these platforms. There are just too many
> > -	 * revealed by these and CI/Bat suffers from the noise.
> > -	 * Please fix and then re-enable the automatic traces.
> > -	 */
> > -	if (i915.mmio_debug < 2 &&
> > -	    (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
> > -		return;
> > -
> >  	if (WARN(check_for_unclaimed_mmio(dev_priv),
> >  		 "Unclaimed register detected %s %s register
> > 0x%x\n",
> >  		 before ? "before" : "after",

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 10/10] Revert "drm/i915: Limit the auto arming of mmio debugs on vlv/chv"

[Chris Wilson]

On Tue, Apr 12, 2016 at 08:08:01PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 12, 2016 at 03:04:10PM +0300, Imre Deak wrote:
> > On ma, 2016-04-11 at 16:56 +0300, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Enable the unclaimd register detection stuff on vlv/chv since we've
> > > now
> > > fixed the known problems during suspend.
> > > 
> > > This reverts commit c81eeea6c14b212016104f4256c65f93ad230a86.
> > > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> 
> Entire series pushed to dinq. Thanks for the reviews.

Nice work on getting mmio_debug out of its little rats nest!
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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✗ Fi.CI.BAT: failure for drm/i915: Fix VLV/CHV unclaimed register errors

[Patchwork]

== Series Details ==

Series: drm/i915: Fix VLV/CHV unclaimed register errors
URL   : https://patchwork.freedesktop.org/series/5531/
State : failure

== Summary ==

Series 5531v1 drm/i915: Fix VLV/CHV unclaimed register errors
http://patchwork.freedesktop.org/api/1.0/series/5531/revisions/1/mbox/

Test gem_busy:
        Subgroup basic-blt:
                pass       -> INCOMPLETE (snb-dellxps)
        Subgroup basic-render:
                skip       -> PASS       (hsw-gt2)
Test gem_ctx_param_basic:
        Subgroup invalid-ctx-get:
                pass       -> DMESG-WARN (bsw-nuc-2)
        Subgroup non-root-set:
                pass       -> DMESG-WARN (bsw-nuc-2)
Test gem_exec_basic:
        Subgroup gtt-bsd:
                pass       -> SKIP       (bsw-nuc-2)
Test gem_mmap_gtt:
        Subgroup basic-small-copy-xy:
                pass       -> DMESG-WARN (bsw-nuc-2)
        Subgroup basic-write-no-prefault:
                pass       -> DMESG-WARN (bsw-nuc-2)
Test gem_storedw_loop:
        Subgroup basic-render:
                pass       -> SKIP       (bsw-nuc-2)
Test gem_tiled_fence_blits:
        Subgroup basic:
                pass       -> DMESG-FAIL (bsw-nuc-2)
Test kms_addfb_basic:
        Subgroup no-handle:
                pass       -> DMESG-WARN (bsw-nuc-2)
Test kms_flip:
        Subgroup basic-flip-vs-modeset:
                dmesg-warn -> PASS       (ilk-hp8440p) UNSTABLE
Test kms_force_connector_basic:
        Subgroup force-edid:
                pass       -> SKIP       (ivb-t430s)
Test kms_pipe_crc_basic:
        Subgroup read-crc-pipe-a-frame-sequence:
                pass       -> SKIP       (hsw-brixbox)
        Subgroup suspend-read-crc-pipe-c:
                pass       -> DMESG-FAIL (bsw-nuc-2)
Test pm_rpm:
        Subgroup basic-pci-d3-state:
                pass       -> DMESG-WARN (bsw-nuc-2)
        Subgroup basic-rte:
                dmesg-warn -> PASS       (bsw-nuc-2)

bdw-ultra        total:202  pass:179  dwarn:0   dfail:0   fail:0   skip:23 
bsw-nuc-2        total:201  pass:152  dwarn:6   dfail:2   fail:0   skip:41 
byt-nuc          total:201  pass:163  dwarn:0   dfail:0   fail:0   skip:38 
hsw-brixbox      total:202  pass:177  dwarn:0   dfail:0   fail:0   skip:25 
hsw-gt2          total:202  pass:183  dwarn:0   dfail:0   fail:0   skip:19 
ilk-hp8440p      total:202  pass:134  dwarn:0   dfail:0   fail:0   skip:68 
ivb-t430s        total:202  pass:173  dwarn:0   dfail:0   fail:0   skip:29 
skl-i7k-2        total:202  pass:177  dwarn:0   dfail:0   fail:0   skip:25 
skl-nuci5        total:202  pass:191  dwarn:0   dfail:0   fail:0   skip:11 
snb-dellxps      total:99   pass:78   dwarn:0   dfail:0   fail:0   skip:20 
snb-x220t        total:202  pass:164  dwarn:0   dfail:0   fail:1   skip:37 

Results at /archive/results/CI_IGT_test/Patchwork_1862/

75635547cc623acbbe3941b93264e8cbb4686d29 drm-intel-nightly: 2016y-04m-11d-11h-18m-04s UTC integration manifest
95404e98fda24cf0dfeabe00ee7804eea06d18d0 Revert "drm/i915: Limit the auto arming of mmio debugs on vlv/chv"
fc295dfee66f06591567d612d44dd2eb58850cc7 drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()
35066da8bb1da5efe15530768c0b52eabec0c503 drm/i915: Move vlv_init_display_clock_gating() to the display power well
64ef8c05a4977c1213f4661ca550d598bca16729 drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq postinstall
fd065544c0dd09a7bb0333b89970baeb0cf19094 drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall()
c853feb33c049e8e68ec528c4d637d879cefb4bb drm/i915: Clear display interrupt before enabling when turning on the power well
87f3206fa3c5c221d0ae8663838626a8c7943c7d drm/i915: Move vlv/chv display irq code to a more logical place
1d4460e646432e31608f44579d015f0208b80657 drm/i915: Skip display irq setup if display irqs aren't flagged as enabled
a0d1632e07bd77ac39a6121c262d2a612d08df0e drm/i915: Fix up vlv/chv display irq setup
6ed27b693027247102533f20c7b00af2f4f0265f drm/i915: Remove "VLV magic" from irq setup

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Re: ✗ Fi.CI.BAT: failure for drm/i915: Fix VLV/CHV unclaimed register errors

[Ville Syrjälä]

On Mon, Apr 11, 2016 at 02:30:51PM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Fix VLV/CHV unclaimed register errors
> URL   : https://patchwork.freedesktop.org/series/5531/
> State : failure
> 
> == Summary ==
> 
> Series 5531v1 drm/i915: Fix VLV/CHV unclaimed register errors
> http://patchwork.freedesktop.org/api/1.0/series/5531/revisions/1/mbox/
> 
> Test gem_busy:
>         Subgroup basic-blt:
>                 pass       -> INCOMPLETE (snb-dellxps)

Machine died?

Last lines in the log:
[  219.031203] kms_flip: exiting, ret=0
[  219.031690] [drm:connected_sink_compute_bpp] [CONNECTOR:35:HDMI-A-1] checking for sink bpp constrains
[  219.031692] [drm:connected_sink_compute_bpp] clamping display bpp (was 36) to EDID reported max of 24
[  219.031695] [drm:intel_hdmi_compute_config] picking bpc to 8 for HDMI output
[  219.031696] [drm:intel_hdmi_compute_config] forcing pipe bpc to 24 for HDMI
[  219.031698] [drm:ironlake_check_fdi_lanes] checking fdi config on pipe A, lanes 2
[  219.031700] [drm:intel_modeset_pipe_config] hw max bpp: 36, pipe bpp: 24, dithering: 0
[  219.031702] [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff880128230008 for pipe A
[  219.031703] [drm:intel_dump_pipe_config] cpu_transcoder: A
[  219.031704] [drm:intel_dump_pipe_config] pipe bpp: 24, dithering: 0
[  219.031706] [drm:intel_dump_pipe_config] fdi/pch: 1, lanes: 2, gmch_m: 6920601, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
[  219.031708] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[  219.031709] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[  219.031711] [drm:intel_dump_pipe_config] audio: 1, infoframes: 1
[  219.031712] [drm:intel_dump_pipe_config] requested mode:
[  219.031714] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[  219.031715] [drm:intel_dump_pipe_config] adjusted mode:
[  219.031718] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
[  219.031720] [drm:intel_dump_crtc_timings] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
[  219.031721] [drm:intel_dump_pipe_config] port clock: 148500
[  219.031722] [drm:intel_dump_pipe_config] pipe src size: 1920x1080
[  219.031724] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
[  219.031725] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[  219.031726] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[  219.031727] [drm:intel_dump_pipe_config] ips: 0
[  

>         Subgroup basic-render:
>                 skip       -> PASS       (hsw-gt2)
> Test gem_ctx_param_basic:
>         Subgroup invalid-ctx-get:
>                 pass       -> DMESG-WARN (bsw-nuc-2)
>         Subgroup non-root-set:
>                 pass       -> DMESG-WARN (bsw-nuc-2)
> Test gem_exec_basic:
>         Subgroup gtt-bsd:
>                 pass       -> SKIP       (bsw-nuc-2)
> Test gem_mmap_gtt:
>         Subgroup basic-small-copy-xy:
>                 pass       -> DMESG-WARN (bsw-nuc-2)
>         Subgroup basic-write-no-prefault:
>                 pass       -> DMESG-WARN (bsw-nuc-2)
> Test gem_storedw_loop:
>         Subgroup basic-render:
>                 pass       -> SKIP       (bsw-nuc-2)
> Test gem_tiled_fence_blits:
>         Subgroup basic:
>                 pass       -> DMESG-FAIL (bsw-nuc-2)
> Test kms_addfb_basic:
>         Subgroup no-handle:
>                 pass       -> DMESG-WARN (bsw-nuc-2)
> Test kms_flip:
>         Subgroup basic-flip-vs-modeset:
>                 dmesg-warn -> PASS       (ilk-hp8440p) UNSTABLE
> Test kms_force_connector_basic:
>         Subgroup force-edid:
>                 pass       -> SKIP       (ivb-t430s)
> Test kms_pipe_crc_basic:
>         Subgroup read-crc-pipe-a-frame-sequence:
>                 pass       -> SKIP       (hsw-brixbox)
>         Subgroup suspend-read-crc-pipe-c:
>                 pass       -> DMESG-FAIL (bsw-nuc-2)
> Test pm_rpm:
>         Subgroup basic-pci-d3-state:
>                 pass       -> DMESG-WARN (bsw-nuc-2)
>         Subgroup basic-rte:
>                 dmesg-warn -> PASS       (bsw-nuc-2)

[  452.682257] WARNING: CPU: 1 PID: 6456 at drivers/gpu/drm/drm_irq.c:1323 drm_wait_one_vblank+0x150/0x1a0
[  452.682273] vblank wait timed out on crtc 2

[  477.071090] [drm:i915_set_reset_status [i915]] *ERROR* gpu hanging too fast, banning!
[  477.082011] drm/i915: Resetting chip after gpu hang
[  483.074746] [drm:i915_set_reset_status [i915]] *ERROR* gpu hanging too fast, banning!
[  483.080771] drm/i915: Resetting chip after gpu hang

BSW is generally unhappy about interrupts. I'll post some fixes soon, I hope.

> 
> bdw-ultra        total:202  pass:179  dwarn:0   dfail:0   fail:0   skip:23 
> bsw-nuc-2        total:201  pass:152  dwarn:6   dfail:2   fail:0   skip:41 
> byt-nuc          total:201  pass:163  dwarn:0   dfail:0   fail:0   skip:38 
> hsw-brixbox      total:202  pass:177  dwarn:0   dfail:0   fail:0   skip:25 
> hsw-gt2          total:202  pass:183  dwarn:0   dfail:0   fail:0   skip:19 
> ilk-hp8440p      total:202  pass:134  dwarn:0   dfail:0   fail:0   skip:68 
> ivb-t430s        total:202  pass:173  dwarn:0   dfail:0   fail:0   skip:29 
> skl-i7k-2        total:202  pass:177  dwarn:0   dfail:0   fail:0   skip:25 
> skl-nuci5        total:202  pass:191  dwarn:0   dfail:0   fail:0   skip:11 
> snb-dellxps      total:99   pass:78   dwarn:0   dfail:0   fail:0   skip:20 
> snb-x220t        total:202  pass:164  dwarn:0   dfail:0   fail:1   skip:37 
> 
> Results at /archive/results/CI_IGT_test/Patchwork_1862/
> 
> 75635547cc623acbbe3941b93264e8cbb4686d29 drm-intel-nightly: 2016y-04m-11d-11h-18m-04s UTC integration manifest
> 95404e98fda24cf0dfeabe00ee7804eea06d18d0 Revert "drm/i915: Limit the auto arming of mmio debugs on vlv/chv"
> fc295dfee66f06591567d612d44dd2eb58850cc7 drm/i915: Move DPINVGTT setup to vlv_display_irq_reset()
> 35066da8bb1da5efe15530768c0b52eabec0c503 drm/i915: Move vlv_init_display_clock_gating() to the display power well
> 64ef8c05a4977c1213f4661ca550d598bca16729 drm/i915: Warn if irq_mask isn't ~0 during vlv/cvh display irq postinstall
> fd065544c0dd09a7bb0333b89970baeb0cf19094 drm/i915: Use GEN5_IRQ_INIT() in vlv_display_irq_postinstall()
> c853feb33c049e8e68ec528c4d637d879cefb4bb drm/i915: Clear display interrupt before enabling when turning on the power well
> 87f3206fa3c5c221d0ae8663838626a8c7943c7d drm/i915: Move vlv/chv display irq code to a more logical place
> 1d4460e646432e31608f44579d015f0208b80657 drm/i915: Skip display irq setup if display irqs aren't flagged as enabled
> a0d1632e07bd77ac39a6121c262d2a612d08df0e drm/i915: Fix up vlv/chv display irq setup
> 6ed27b693027247102533f20c7b00af2f4f0265f drm/i915: Remove "VLV magic" from irq setup

-- 
Ville Syrjälä
Intel OTC
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