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From: "Daniel P. Berrangé" <berrange@redhat.com>
To: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Eduardo Habkost <ehabkost@redhat.com>,
	kvm@vger.kernel.org,
	Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
	qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net
Subject: Re: [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit
Date: Tue, 5 Jun 2018 15:04:53 +0100	[thread overview]
Message-ID: <20180605140453.GL32286@redhat.com> (raw)
In-Reply-To: <caa3376a-252b-0a85-1a63-d2a6a911739c@amd.com>

On Tue, Jun 05, 2018 at 08:31:41AM -0500, Tom Lendacky wrote:
> On 6/4/2018 3:07 PM, Eduardo Habkost wrote:
> > On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote:
> >> AMD future CPUs expose _two_ ways to utilize the Intel equivalant
> >> of the Speculative Store Bypass Disable. The first is via
> >> the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second
> >> is via the SPEC_CTRL MSR (0x48). The document titled:
> >> 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf
> >>
> >> gives priority of SPEC CTRL MSR over the VIRT SPEC CTRL MSR.
> >>
> >> A copy of this document is available at
> >>       https://bugzilla.kernel.org/show_bug.cgi?id=199889
> >>
> >> Anyhow, this means that on future AMD CPUs there will be  _two_ ways to
> >> deal with SSBD.
> > 
> > Does anybody know if there are AMD CPUs where virt-ssbd won't
> > work and would require amd-ssbd to mitigate vulnerabilities?
> 
> The idea behind virt-ssbd was to provide an architectural method for
> a guest to do SSBD when amd-ssbd isn't present.  The amd-ssbd feature
> will use SPEC_CTRL which is intended to not be intercepted and
> will be fast.  The use of virt-ssbd will always be intercepted and
> therefore will not be as fast.  So a guest should be presented with
> amd-ssbd, if available, in preference to virt-ssbd.

Thanks, that's useful info.

Can you say whether amd-ssbd is going to become available for existing
CPUs via microcode updates, or will it only be present in future CPUs ?

> > Also, do we have kernel arch/x86/kvm/cpuid.c patches, already?
> > I prefer to add new CPUID flag names only after the flag name is
> > already agreed upon on the kernel side.
> > 
> > 
> >>
> >> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
> >> ---
> >>  target/i386/cpu.c | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> >> index 52d334a..f91990c 100644
> >> --- a/target/i386/cpu.c
> >> +++ b/target/i386/cpu.c
> >> @@ -490,7 +490,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
> >>              "ibpb", NULL, NULL, NULL,
> >>              NULL, NULL, NULL, NULL,
> >>              NULL, NULL, NULL, NULL,
> >> -            NULL, "virt-ssbd", NULL, NULL,
> >> +            "amd-ssbd", "virt-ssbd", NULL, NULL,
> >>              NULL, NULL, NULL, NULL,
> >>          },
> >>          .cpuid_eax = 0x80000008,

Regards,
Daniel
-- 
|: https://berrange.com      -o-    https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org         -o-            https://fstop138.berrange.com :|
|: https://entangle-photo.org    -o-    https://www.instagram.com/dberrange :|

WARNING: multiple messages have this Message-ID (diff)
From: "Daniel P. Berrangé" <berrange@redhat.com>
To: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Eduardo Habkost <ehabkost@redhat.com>,
	Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
	pbonzini@redhat.com, qemu-devel@nongnu.org, kvm@vger.kernel.org,
	rth@twiddle.net
Subject: Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit
Date: Tue, 5 Jun 2018 15:04:53 +0100	[thread overview]
Message-ID: <20180605140453.GL32286@redhat.com> (raw)
In-Reply-To: <caa3376a-252b-0a85-1a63-d2a6a911739c@amd.com>

On Tue, Jun 05, 2018 at 08:31:41AM -0500, Tom Lendacky wrote:
> On 6/4/2018 3:07 PM, Eduardo Habkost wrote:
> > On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote:
> >> AMD future CPUs expose _two_ ways to utilize the Intel equivalant
> >> of the Speculative Store Bypass Disable. The first is via
> >> the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second
> >> is via the SPEC_CTRL MSR (0x48). The document titled:
> >> 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf
> >>
> >> gives priority of SPEC CTRL MSR over the VIRT SPEC CTRL MSR.
> >>
> >> A copy of this document is available at
> >>       https://bugzilla.kernel.org/show_bug.cgi?id=199889
> >>
> >> Anyhow, this means that on future AMD CPUs there will be  _two_ ways to
> >> deal with SSBD.
> > 
> > Does anybody know if there are AMD CPUs where virt-ssbd won't
> > work and would require amd-ssbd to mitigate vulnerabilities?
> 
> The idea behind virt-ssbd was to provide an architectural method for
> a guest to do SSBD when amd-ssbd isn't present.  The amd-ssbd feature
> will use SPEC_CTRL which is intended to not be intercepted and
> will be fast.  The use of virt-ssbd will always be intercepted and
> therefore will not be as fast.  So a guest should be presented with
> amd-ssbd, if available, in preference to virt-ssbd.

Thanks, that's useful info.

Can you say whether amd-ssbd is going to become available for existing
CPUs via microcode updates, or will it only be present in future CPUs ?

> > Also, do we have kernel arch/x86/kvm/cpuid.c patches, already?
> > I prefer to add new CPUID flag names only after the flag name is
> > already agreed upon on the kernel side.
> > 
> > 
> >>
> >> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
> >> ---
> >>  target/i386/cpu.c | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> >> index 52d334a..f91990c 100644
> >> --- a/target/i386/cpu.c
> >> +++ b/target/i386/cpu.c
> >> @@ -490,7 +490,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
> >>              "ibpb", NULL, NULL, NULL,
> >>              NULL, NULL, NULL, NULL,
> >>              NULL, NULL, NULL, NULL,
> >> -            NULL, "virt-ssbd", NULL, NULL,
> >> +            "amd-ssbd", "virt-ssbd", NULL, NULL,
> >>              NULL, NULL, NULL, NULL,
> >>          },
> >>          .cpuid_eax = 0x80000008,

Regards,
Daniel
-- 
|: https://berrange.com      -o-    https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org         -o-            https://fstop138.berrange.com :|
|: https://entangle-photo.org    -o-    https://www.instagram.com/dberrange :|

  reply	other threads:[~2018-06-05 14:04 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-01 14:59 [PATCH v1] AMD SSB bits Konrad Rzeszutek Wilk
2018-06-01 14:59 ` [PATCH v1 1/3] x86/bugs: Add AMD's variant of SSB_NO Konrad Rzeszutek Wilk
2018-06-06 12:15   ` [tip:x86/pti] " tip-bot for Konrad Rzeszutek Wilk
2018-06-01 14:59 ` [PATCH v1 2/3] x86/bugs: Add AMD's SPEC_CTRL MSR usage Konrad Rzeszutek Wilk
2018-06-02  1:04   ` Tom Lendacky
2018-06-04 20:20     ` Konrad Rzeszutek Wilk
2018-06-04 20:43       ` Tom Lendacky
2018-06-04 20:54         ` Konrad Rzeszutek Wilk
2018-06-06 12:16   ` [tip:x86/pti] " tip-bot for Konrad Rzeszutek Wilk
2018-06-01 14:59 ` [PATCH v1 3/3] x86/bugs: Switch the selection of mitigation from CPU vendor to CPU features Konrad Rzeszutek Wilk
2018-06-06 12:16   ` [tip:x86/pti] " tip-bot for Konrad Rzeszutek Wilk
2018-06-08 21:30   ` [PATCH v1 3/3] " Tom Lendacky
2018-06-11 14:01     ` Konrad Rzeszutek Wilk
2018-06-12 14:38       ` Tom Lendacky
2018-06-15 18:57         ` Thomas Gleixner
2018-06-15 19:38           ` Konrad Rzeszutek Wilk
2018-06-01 15:38 ` [PATCH QEMU] Patches for new AMD CPU bits Konrad Rzeszutek Wilk
2018-06-01 15:38   ` [Qemu-devel] " Konrad Rzeszutek Wilk
2018-06-01 15:38   ` [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit Konrad Rzeszutek Wilk
2018-06-01 15:38     ` [Qemu-devel] " Konrad Rzeszutek Wilk
2018-06-04  8:54     ` Daniel P. Berrangé
2018-06-04  8:54       ` [Qemu-devel] " Daniel P. Berrangé
2018-06-04 20:20       ` Konrad Rzeszutek Wilk
2018-06-04 20:20         ` [Qemu-devel] " Konrad Rzeszutek Wilk
2018-06-04 20:07     ` Eduardo Habkost
2018-06-04 20:07       ` [Qemu-devel] " Eduardo Habkost
2018-06-04 20:22       ` Konrad Rzeszutek Wilk
2018-06-04 20:22         ` [Qemu-devel] " Konrad Rzeszutek Wilk
2018-06-04 21:15         ` Eduardo Habkost
2018-06-04 21:15           ` [Qemu-devel] " Eduardo Habkost
2018-06-05 21:40           ` Konrad Rzeszutek Wilk
2018-06-05 21:40             ` [Qemu-devel] " Konrad Rzeszutek Wilk
2018-06-13 10:19         ` Daniel P. Berrangé
2018-06-13 10:19           ` [Qemu-devel] " Daniel P. Berrangé
2018-06-13 16:09           ` Konrad Rzeszutek Wilk
2018-06-13 16:09             ` [Qemu-devel] " Konrad Rzeszutek Wilk
2018-06-13 16:21             ` Daniel P. Berrangé
2018-06-13 16:21               ` [Qemu-devel] " Daniel P. Berrangé
2018-06-13 16:34               ` Konrad Rzeszutek Wilk
2018-06-13 16:34                 ` [Qemu-devel] " Konrad Rzeszutek Wilk
2018-06-13 16:39                 ` Daniel P. Berrangé
2018-06-13 16:39                   ` [Qemu-devel] " Daniel P. Berrangé
2018-06-13 16:56                   ` Eduardo Habkost
2018-06-13 16:56                     ` [Qemu-devel] " Eduardo Habkost
2018-06-05 13:31       ` Tom Lendacky
2018-06-05 13:31         ` [Qemu-devel] " Tom Lendacky
2018-06-05 14:04         ` Daniel P. Berrangé [this message]
2018-06-05 14:04           ` Daniel P. Berrangé
2018-06-06 14:20         ` Daniel P. Berrangé
2018-06-06 14:20           ` [Qemu-devel] " Daniel P. Berrangé
2018-06-08 21:22           ` Tom Lendacky
2018-06-08 21:22             ` [Qemu-devel] " Tom Lendacky
2018-06-01 15:38   ` [PATCH 2/2] i386: Define AMD's no SSB mitigation needed Konrad Rzeszutek Wilk
2018-06-01 15:38     ` [Qemu-devel] " Konrad Rzeszutek Wilk
2018-06-13 21:38   ` [PATCH QEMU] Patches for new AMD CPU bits Eduardo Habkost
2018-06-13 21:38     ` [Qemu-devel] " Eduardo Habkost
2018-06-05 13:23 ` [PATCH v1] AMD SSB bits Tom Lendacky
2018-06-05 20:56   ` Konrad Rzeszutek Wilk

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