From: Eduardo Habkost <ehabkost@redhat.com>
To: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: pbonzini@redhat.com, qemu-devel@nongnu.org, kvm@vger.kernel.org,
rth@twiddle.net
Subject: Re: [PATCH QEMU] Patches for new AMD CPU bits.
Date: Wed, 13 Jun 2018 18:38:58 -0300 [thread overview]
Message-ID: <20180613213858.GI24764@localhost.localdomain> (raw)
In-Reply-To: <20180601153809.15259-1-konrad.wilk@oracle.com>
On Fri, Jun 01, 2018 at 11:38:07AM -0400, Konrad Rzeszutek Wilk wrote:
> Hi!
>
>
> I was reading the AMD whitepaper on SSBD and noticed that they have added
> two new bits in the 8000_0008 CPUID. EBX:
> 1) Bit[26] - similar to Intel's SSB_NO not needed anymore.
> 2) Bit[24] - use SPEC_CTRL MSR (0x48) instead of VIRT SPEC_CTRL MSR
> (0xC001_011f).
>
> See 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf
> A copy of this document is available at
> https://bugzilla.kernel.org/show_bug.cgi?id=199889
>
> These two patches along with the kernel ones allow us to expose those
> two bits to the guest.
Queued on x86-next, thanks!
--
Eduardo
WARNING: multiple messages have this Message-ID (diff)
From: Eduardo Habkost <ehabkost@redhat.com>
To: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: kvm@vger.kernel.org, qemu-devel@nongnu.org, pbonzini@redhat.com,
rth@twiddle.net
Subject: Re: [Qemu-devel] [PATCH QEMU] Patches for new AMD CPU bits.
Date: Wed, 13 Jun 2018 18:38:58 -0300 [thread overview]
Message-ID: <20180613213858.GI24764@localhost.localdomain> (raw)
In-Reply-To: <20180601153809.15259-1-konrad.wilk@oracle.com>
On Fri, Jun 01, 2018 at 11:38:07AM -0400, Konrad Rzeszutek Wilk wrote:
> Hi!
>
>
> I was reading the AMD whitepaper on SSBD and noticed that they have added
> two new bits in the 8000_0008 CPUID. EBX:
> 1) Bit[26] - similar to Intel's SSB_NO not needed anymore.
> 2) Bit[24] - use SPEC_CTRL MSR (0x48) instead of VIRT SPEC_CTRL MSR
> (0xC001_011f).
>
> See 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf
> A copy of this document is available at
> https://bugzilla.kernel.org/show_bug.cgi?id=199889
>
> These two patches along with the kernel ones allow us to expose those
> two bits to the guest.
Queued on x86-next, thanks!
--
Eduardo
next prev parent reply other threads:[~2018-06-13 21:38 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-01 14:59 [PATCH v1] AMD SSB bits Konrad Rzeszutek Wilk
2018-06-01 14:59 ` [PATCH v1 1/3] x86/bugs: Add AMD's variant of SSB_NO Konrad Rzeszutek Wilk
2018-06-06 12:15 ` [tip:x86/pti] " tip-bot for Konrad Rzeszutek Wilk
2018-06-01 14:59 ` [PATCH v1 2/3] x86/bugs: Add AMD's SPEC_CTRL MSR usage Konrad Rzeszutek Wilk
2018-06-02 1:04 ` Tom Lendacky
2018-06-04 20:20 ` Konrad Rzeszutek Wilk
2018-06-04 20:43 ` Tom Lendacky
2018-06-04 20:54 ` Konrad Rzeszutek Wilk
2018-06-06 12:16 ` [tip:x86/pti] " tip-bot for Konrad Rzeszutek Wilk
2018-06-01 14:59 ` [PATCH v1 3/3] x86/bugs: Switch the selection of mitigation from CPU vendor to CPU features Konrad Rzeszutek Wilk
2018-06-06 12:16 ` [tip:x86/pti] " tip-bot for Konrad Rzeszutek Wilk
2018-06-08 21:30 ` [PATCH v1 3/3] " Tom Lendacky
2018-06-11 14:01 ` Konrad Rzeszutek Wilk
2018-06-12 14:38 ` Tom Lendacky
2018-06-15 18:57 ` Thomas Gleixner
2018-06-15 19:38 ` Konrad Rzeszutek Wilk
2018-06-01 15:38 ` [PATCH QEMU] Patches for new AMD CPU bits Konrad Rzeszutek Wilk
2018-06-01 15:38 ` [Qemu-devel] " Konrad Rzeszutek Wilk
2018-06-01 15:38 ` [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit Konrad Rzeszutek Wilk
2018-06-01 15:38 ` [Qemu-devel] " Konrad Rzeszutek Wilk
2018-06-04 8:54 ` Daniel P. Berrangé
2018-06-04 8:54 ` [Qemu-devel] " Daniel P. Berrangé
2018-06-04 20:20 ` Konrad Rzeszutek Wilk
2018-06-04 20:20 ` [Qemu-devel] " Konrad Rzeszutek Wilk
2018-06-04 20:07 ` Eduardo Habkost
2018-06-04 20:07 ` [Qemu-devel] " Eduardo Habkost
2018-06-04 20:22 ` Konrad Rzeszutek Wilk
2018-06-04 20:22 ` [Qemu-devel] " Konrad Rzeszutek Wilk
2018-06-04 21:15 ` Eduardo Habkost
2018-06-04 21:15 ` [Qemu-devel] " Eduardo Habkost
2018-06-05 21:40 ` Konrad Rzeszutek Wilk
2018-06-05 21:40 ` [Qemu-devel] " Konrad Rzeszutek Wilk
2018-06-13 10:19 ` Daniel P. Berrangé
2018-06-13 10:19 ` [Qemu-devel] " Daniel P. Berrangé
2018-06-13 16:09 ` Konrad Rzeszutek Wilk
2018-06-13 16:09 ` [Qemu-devel] " Konrad Rzeszutek Wilk
2018-06-13 16:21 ` Daniel P. Berrangé
2018-06-13 16:21 ` [Qemu-devel] " Daniel P. Berrangé
2018-06-13 16:34 ` Konrad Rzeszutek Wilk
2018-06-13 16:34 ` [Qemu-devel] " Konrad Rzeszutek Wilk
2018-06-13 16:39 ` Daniel P. Berrangé
2018-06-13 16:39 ` [Qemu-devel] " Daniel P. Berrangé
2018-06-13 16:56 ` Eduardo Habkost
2018-06-13 16:56 ` [Qemu-devel] " Eduardo Habkost
2018-06-05 13:31 ` Tom Lendacky
2018-06-05 13:31 ` [Qemu-devel] " Tom Lendacky
2018-06-05 14:04 ` Daniel P. Berrangé
2018-06-05 14:04 ` [Qemu-devel] " Daniel P. Berrangé
2018-06-06 14:20 ` Daniel P. Berrangé
2018-06-06 14:20 ` [Qemu-devel] " Daniel P. Berrangé
2018-06-08 21:22 ` Tom Lendacky
2018-06-08 21:22 ` [Qemu-devel] " Tom Lendacky
2018-06-01 15:38 ` [PATCH 2/2] i386: Define AMD's no SSB mitigation needed Konrad Rzeszutek Wilk
2018-06-01 15:38 ` [Qemu-devel] " Konrad Rzeszutek Wilk
2018-06-13 21:38 ` Eduardo Habkost [this message]
2018-06-13 21:38 ` [Qemu-devel] [PATCH QEMU] Patches for new AMD CPU bits Eduardo Habkost
2018-06-05 13:23 ` [PATCH v1] AMD SSB bits Tom Lendacky
2018-06-05 20:56 ` Konrad Rzeszutek Wilk
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