From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
dri-devel@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v2 03/15] drm/i915: add I915_BO_ALLOC_GPU_ONLY
Date: Thu, 10 Feb 2022 12:13:01 +0000 [thread overview]
Message-ID: <20220210121313.701004-4-matthew.auld@intel.com> (raw)
In-Reply-To: <20220210121313.701004-1-matthew.auld@intel.com>
If the user doesn't require CPU access for the buffer, then
ALLOC_GPU_ONLY should be used, in order to prioritise allocating in the
non-mappable portion of LMEM, on devices with small BAR.
v2(Thomas):
- The BO_ALLOC_TOPDOWN naming here is poor, since this is pure lies on
systems that don't even have small BAR. A better name is GPU_ONLY,
which is accurate regardless of the configuration.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 17 ++++++++++++-----
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 3 +++
drivers/gpu/drm/i915/gem/i915_gem_region.c | 5 +++++
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 13 ++++++++++---
drivers/gpu/drm/i915/gt/intel_gt.c | 4 +++-
drivers/gpu/drm/i915/i915_vma.c | 3 +++
drivers/gpu/drm/i915/intel_region_ttm.c | 11 ++++++++---
drivers/gpu/drm/i915/selftests/mock_region.c | 7 +------
8 files changed, 45 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0098a32490f0..fd54eb8f4826 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -319,16 +319,23 @@ struct drm_i915_gem_object {
#define I915_BO_ALLOC_PM_VOLATILE BIT(4)
/* Object needs to be restored early using memcpy during resume */
#define I915_BO_ALLOC_PM_EARLY BIT(5)
+/*
+ * Object is likely never accessed by the CPU. This will prioritise the BO to be
+ * allocated in the non-mappable portion of lmem. This is merely a hint, and if
+ * dealing with userspace objects the CPU fault handler is free to ignore this.
+ */
+#define I915_BO_ALLOC_GPU_ONLY BIT(6)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
I915_BO_ALLOC_USER | \
I915_BO_ALLOC_PM_VOLATILE | \
- I915_BO_ALLOC_PM_EARLY)
-#define I915_BO_READONLY BIT(6)
-#define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
-#define I915_BO_PROTECTED BIT(8)
-#define I915_BO_WAS_BOUND_BIT 9
+ I915_BO_ALLOC_PM_EARLY | \
+ I915_BO_ALLOC_GPU_ONLY)
+#define I915_BO_READONLY BIT(7)
+#define I915_TILING_QUIRK_BIT 8 /* unknown swizzling; do not release! */
+#define I915_BO_PROTECTED BIT(9)
+#define I915_BO_WAS_BOUND_BIT 10
/**
* @mem_flags - Mutable placement-related flags
*
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 060fe29f5929..a4d8dc163691 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -356,6 +356,9 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
!i915_gem_object_has_iomem(obj))
return ERR_PTR(-ENXIO);
+ if (WARN_ON_ONCE(obj->flags & I915_BO_ALLOC_GPU_ONLY))
+ return ERR_PTR(-EINVAL);
+
assert_object_held(obj);
pinned = !(type & I915_MAP_OVERRIDE);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index a4350227e9ae..873d52f872c5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -45,6 +45,11 @@ i915_gem_object_create_region(struct intel_memory_region *mem,
GEM_BUG_ON(flags & ~I915_BO_ALLOC_FLAGS);
+ if (WARN_ON_ONCE(flags & I915_BO_ALLOC_GPU_ONLY &&
+ (flags & I915_BO_ALLOC_CPU_CLEAR ||
+ flags & I915_BO_ALLOC_PM_EARLY)))
+ return ERR_PTR(-EINVAL);
+
if (!mem)
return ERR_PTR(-ENODEV);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 41e94d09e742..36e77fcf2ef9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -127,10 +127,14 @@ i915_ttm_place_from_region(const struct intel_memory_region *mr,
place->mem_type = intel_region_to_ttm_type(mr);
if (flags & I915_BO_ALLOC_CONTIGUOUS)
- place->flags = TTM_PL_FLAG_CONTIGUOUS;
+ place->flags |= TTM_PL_FLAG_CONTIGUOUS;
if (mr->io_size && mr->io_size < mr->total) {
- place->fpfn = 0;
- place->lpfn = mr->io_size >> PAGE_SHIFT;
+ if (flags & I915_BO_ALLOC_GPU_ONLY) {
+ place->flags |= TTM_PL_FLAG_TOPDOWN;
+ } else {
+ place->fpfn = 0;
+ place->lpfn = mr->io_size >> PAGE_SHIFT;
+ }
}
}
@@ -888,6 +892,9 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
if (!obj)
return VM_FAULT_SIGBUS;
+ if (obj->flags & I915_BO_ALLOC_GPU_ONLY)
+ return -EINVAL;
+
/* Sanity check that we allow writing into this object */
if (unlikely(i915_gem_object_is_readonly(obj) &&
area->vm_flags & VM_WRITE))
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index e6f6bf7c3926..4f35c51fdb52 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -457,7 +457,9 @@ static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
struct i915_vma *vma;
int ret;
- obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);
+ obj = i915_gem_object_create_lmem(i915, size,
+ I915_BO_ALLOC_VOLATILE |
+ I915_BO_ALLOC_GPU_ONLY);
if (IS_ERR(obj))
obj = i915_gem_object_create_stolen(i915, size);
if (IS_ERR(obj))
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 845cd88f8313..3322a0651a17 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -540,6 +540,9 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
void __iomem *ptr;
int err;
+ if (WARN_ON_ONCE(vma->obj->flags & I915_BO_ALLOC_GPU_ONLY))
+ return IO_ERR_PTR(-EINVAL);
+
if (!i915_gem_object_is_lmem(vma->obj)) {
if (GEM_WARN_ON(!i915_vma_is_map_and_fenceable(vma))) {
err = -ENODEV;
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c b/drivers/gpu/drm/i915/intel_region_ttm.c
index 4689192d5e8d..c055029c7a70 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -199,13 +199,18 @@ intel_region_ttm_resource_alloc(struct intel_memory_region *mem,
struct ttm_resource *res;
int ret;
+ if (flags & I915_BO_ALLOC_CONTIGUOUS)
+ place.flags |= TTM_PL_FLAG_CONTIGUOUS;
if (mem->io_size && mem->io_size < mem->total) {
- place.fpfn = 0;
- place.lpfn = mem->io_size >> PAGE_SHIFT;
+ if (flags & I915_BO_ALLOC_GPU_ONLY) {
+ place.flags |= TTM_PL_FLAG_TOPDOWN;
+ } else {
+ place.fpfn = 0;
+ place.lpfn = mem->io_size >> PAGE_SHIFT;
+ }
}
mock_bo.base.size = size;
- place.flags = flags;
ret = man->func->alloc(man, &mock_bo, &place, &res);
if (ret == -ENOSPC)
diff --git a/drivers/gpu/drm/i915/selftests/mock_region.c b/drivers/gpu/drm/i915/selftests/mock_region.c
index 467eeae6d5f0..f64325491f35 100644
--- a/drivers/gpu/drm/i915/selftests/mock_region.c
+++ b/drivers/gpu/drm/i915/selftests/mock_region.c
@@ -22,17 +22,12 @@ static void mock_region_put_pages(struct drm_i915_gem_object *obj,
static int mock_region_get_pages(struct drm_i915_gem_object *obj)
{
- unsigned int flags;
struct sg_table *pages;
int err;
- flags = 0;
- if (obj->flags & I915_BO_ALLOC_CONTIGUOUS)
- flags |= TTM_PL_FLAG_CONTIGUOUS;
-
obj->mm.res = intel_region_ttm_resource_alloc(obj->mm.region,
obj->base.size,
- flags);
+ obj->flags);
if (IS_ERR(obj->mm.res))
return PTR_ERR(obj->mm.res);
--
2.34.1
WARNING: multiple messages have this Message-ID (diff)
From: Matthew Auld <matthew.auld@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
dri-devel@lists.freedesktop.org
Subject: [PATCH v2 03/15] drm/i915: add I915_BO_ALLOC_GPU_ONLY
Date: Thu, 10 Feb 2022 12:13:01 +0000 [thread overview]
Message-ID: <20220210121313.701004-4-matthew.auld@intel.com> (raw)
In-Reply-To: <20220210121313.701004-1-matthew.auld@intel.com>
If the user doesn't require CPU access for the buffer, then
ALLOC_GPU_ONLY should be used, in order to prioritise allocating in the
non-mappable portion of LMEM, on devices with small BAR.
v2(Thomas):
- The BO_ALLOC_TOPDOWN naming here is poor, since this is pure lies on
systems that don't even have small BAR. A better name is GPU_ONLY,
which is accurate regardless of the configuration.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 17 ++++++++++++-----
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 3 +++
drivers/gpu/drm/i915/gem/i915_gem_region.c | 5 +++++
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 13 ++++++++++---
drivers/gpu/drm/i915/gt/intel_gt.c | 4 +++-
drivers/gpu/drm/i915/i915_vma.c | 3 +++
drivers/gpu/drm/i915/intel_region_ttm.c | 11 ++++++++---
drivers/gpu/drm/i915/selftests/mock_region.c | 7 +------
8 files changed, 45 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0098a32490f0..fd54eb8f4826 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -319,16 +319,23 @@ struct drm_i915_gem_object {
#define I915_BO_ALLOC_PM_VOLATILE BIT(4)
/* Object needs to be restored early using memcpy during resume */
#define I915_BO_ALLOC_PM_EARLY BIT(5)
+/*
+ * Object is likely never accessed by the CPU. This will prioritise the BO to be
+ * allocated in the non-mappable portion of lmem. This is merely a hint, and if
+ * dealing with userspace objects the CPU fault handler is free to ignore this.
+ */
+#define I915_BO_ALLOC_GPU_ONLY BIT(6)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
I915_BO_ALLOC_USER | \
I915_BO_ALLOC_PM_VOLATILE | \
- I915_BO_ALLOC_PM_EARLY)
-#define I915_BO_READONLY BIT(6)
-#define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
-#define I915_BO_PROTECTED BIT(8)
-#define I915_BO_WAS_BOUND_BIT 9
+ I915_BO_ALLOC_PM_EARLY | \
+ I915_BO_ALLOC_GPU_ONLY)
+#define I915_BO_READONLY BIT(7)
+#define I915_TILING_QUIRK_BIT 8 /* unknown swizzling; do not release! */
+#define I915_BO_PROTECTED BIT(9)
+#define I915_BO_WAS_BOUND_BIT 10
/**
* @mem_flags - Mutable placement-related flags
*
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 060fe29f5929..a4d8dc163691 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -356,6 +356,9 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
!i915_gem_object_has_iomem(obj))
return ERR_PTR(-ENXIO);
+ if (WARN_ON_ONCE(obj->flags & I915_BO_ALLOC_GPU_ONLY))
+ return ERR_PTR(-EINVAL);
+
assert_object_held(obj);
pinned = !(type & I915_MAP_OVERRIDE);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index a4350227e9ae..873d52f872c5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -45,6 +45,11 @@ i915_gem_object_create_region(struct intel_memory_region *mem,
GEM_BUG_ON(flags & ~I915_BO_ALLOC_FLAGS);
+ if (WARN_ON_ONCE(flags & I915_BO_ALLOC_GPU_ONLY &&
+ (flags & I915_BO_ALLOC_CPU_CLEAR ||
+ flags & I915_BO_ALLOC_PM_EARLY)))
+ return ERR_PTR(-EINVAL);
+
if (!mem)
return ERR_PTR(-ENODEV);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 41e94d09e742..36e77fcf2ef9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -127,10 +127,14 @@ i915_ttm_place_from_region(const struct intel_memory_region *mr,
place->mem_type = intel_region_to_ttm_type(mr);
if (flags & I915_BO_ALLOC_CONTIGUOUS)
- place->flags = TTM_PL_FLAG_CONTIGUOUS;
+ place->flags |= TTM_PL_FLAG_CONTIGUOUS;
if (mr->io_size && mr->io_size < mr->total) {
- place->fpfn = 0;
- place->lpfn = mr->io_size >> PAGE_SHIFT;
+ if (flags & I915_BO_ALLOC_GPU_ONLY) {
+ place->flags |= TTM_PL_FLAG_TOPDOWN;
+ } else {
+ place->fpfn = 0;
+ place->lpfn = mr->io_size >> PAGE_SHIFT;
+ }
}
}
@@ -888,6 +892,9 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
if (!obj)
return VM_FAULT_SIGBUS;
+ if (obj->flags & I915_BO_ALLOC_GPU_ONLY)
+ return -EINVAL;
+
/* Sanity check that we allow writing into this object */
if (unlikely(i915_gem_object_is_readonly(obj) &&
area->vm_flags & VM_WRITE))
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index e6f6bf7c3926..4f35c51fdb52 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -457,7 +457,9 @@ static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
struct i915_vma *vma;
int ret;
- obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);
+ obj = i915_gem_object_create_lmem(i915, size,
+ I915_BO_ALLOC_VOLATILE |
+ I915_BO_ALLOC_GPU_ONLY);
if (IS_ERR(obj))
obj = i915_gem_object_create_stolen(i915, size);
if (IS_ERR(obj))
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 845cd88f8313..3322a0651a17 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -540,6 +540,9 @@ void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
void __iomem *ptr;
int err;
+ if (WARN_ON_ONCE(vma->obj->flags & I915_BO_ALLOC_GPU_ONLY))
+ return IO_ERR_PTR(-EINVAL);
+
if (!i915_gem_object_is_lmem(vma->obj)) {
if (GEM_WARN_ON(!i915_vma_is_map_and_fenceable(vma))) {
err = -ENODEV;
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c b/drivers/gpu/drm/i915/intel_region_ttm.c
index 4689192d5e8d..c055029c7a70 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -199,13 +199,18 @@ intel_region_ttm_resource_alloc(struct intel_memory_region *mem,
struct ttm_resource *res;
int ret;
+ if (flags & I915_BO_ALLOC_CONTIGUOUS)
+ place.flags |= TTM_PL_FLAG_CONTIGUOUS;
if (mem->io_size && mem->io_size < mem->total) {
- place.fpfn = 0;
- place.lpfn = mem->io_size >> PAGE_SHIFT;
+ if (flags & I915_BO_ALLOC_GPU_ONLY) {
+ place.flags |= TTM_PL_FLAG_TOPDOWN;
+ } else {
+ place.fpfn = 0;
+ place.lpfn = mem->io_size >> PAGE_SHIFT;
+ }
}
mock_bo.base.size = size;
- place.flags = flags;
ret = man->func->alloc(man, &mock_bo, &place, &res);
if (ret == -ENOSPC)
diff --git a/drivers/gpu/drm/i915/selftests/mock_region.c b/drivers/gpu/drm/i915/selftests/mock_region.c
index 467eeae6d5f0..f64325491f35 100644
--- a/drivers/gpu/drm/i915/selftests/mock_region.c
+++ b/drivers/gpu/drm/i915/selftests/mock_region.c
@@ -22,17 +22,12 @@ static void mock_region_put_pages(struct drm_i915_gem_object *obj,
static int mock_region_get_pages(struct drm_i915_gem_object *obj)
{
- unsigned int flags;
struct sg_table *pages;
int err;
- flags = 0;
- if (obj->flags & I915_BO_ALLOC_CONTIGUOUS)
- flags |= TTM_PL_FLAG_CONTIGUOUS;
-
obj->mm.res = intel_region_ttm_resource_alloc(obj->mm.region,
obj->base.size,
- flags);
+ obj->flags);
if (IS_ERR(obj->mm.res))
return PTR_ERR(obj->mm.res);
--
2.34.1
next prev parent reply other threads:[~2022-02-10 12:16 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-10 12:12 [Intel-gfx] [PATCH v2 00/15] Initial support for small BAR recovery Matthew Auld
2022-02-10 12:12 ` Matthew Auld
2022-02-10 12:12 ` [Intel-gfx] [PATCH v2 01/15] drm/i915: add io_size plumbing Matthew Auld
2022-02-10 12:12 ` Matthew Auld
2022-02-10 12:13 ` [Intel-gfx] [PATCH v2 02/15] drm/i915/ttm: require mappable by default Matthew Auld
2022-02-10 12:13 ` Matthew Auld
2022-02-11 9:20 ` [Intel-gfx] " Thomas Hellström
2022-02-11 9:20 ` Thomas Hellström
2022-02-10 12:13 ` Matthew Auld [this message]
2022-02-10 12:13 ` [PATCH v2 03/15] drm/i915: add I915_BO_ALLOC_GPU_ONLY Matthew Auld
2022-02-11 9:23 ` [Intel-gfx] " Thomas Hellström
2022-02-11 9:23 ` Thomas Hellström
2022-02-10 12:13 ` [Intel-gfx] [PATCH v2 04/15] drm/i915/buddy: track available visible size Matthew Auld
2022-02-10 12:13 ` Matthew Auld
2022-02-11 9:25 ` [Intel-gfx] " Thomas Hellström
2022-02-11 9:25 ` Thomas Hellström
2022-02-10 12:13 ` [Intel-gfx] [PATCH v2 05/15] drm/i915/buddy: adjust res->start Matthew Auld
2022-02-10 12:13 ` Matthew Auld
2022-02-10 12:13 ` [Intel-gfx] [PATCH v2 06/15] drm/i915/buddy: tweak 2big check Matthew Auld
2022-02-10 12:13 ` Matthew Auld
2022-02-10 12:13 ` [Intel-gfx] [PATCH v2 07/15] drm/i915/selftests: mock test io_size Matthew Auld
2022-02-10 12:13 ` Matthew Auld
2022-02-10 12:13 ` [Intel-gfx] [PATCH v2 08/15] drm/i915/ttm: make eviction mappable aware Matthew Auld
2022-02-10 12:13 ` Matthew Auld
2022-02-10 12:13 ` [Intel-gfx] [PATCH v2 09/15] drm/i915/ttm: mappable migration on fault Matthew Auld
2022-02-10 12:13 ` Matthew Auld
2022-02-10 12:13 ` [Intel-gfx] [PATCH v2 10/15] drm/i915/selftests: exercise mmap migration Matthew Auld
2022-02-10 12:13 ` Matthew Auld
2022-02-11 9:36 ` [Intel-gfx] " Thomas Hellström
2022-02-11 9:36 ` Thomas Hellström
2022-02-10 12:13 ` [Intel-gfx] [PATCH v2 11/15] drm/i915/selftests: handle allocation failures Matthew Auld
2022-02-10 12:13 ` Matthew Auld
2022-02-11 9:37 ` [Intel-gfx] " Thomas Hellström
2022-02-11 9:37 ` Thomas Hellström
2022-02-10 12:13 ` [Intel-gfx] [PATCH v2 12/15] drm/i915/create: apply ALLOC_GPU_ONLY by default Matthew Auld
2022-02-10 12:13 ` Matthew Auld
2022-02-11 9:49 ` [Intel-gfx] " Thomas Hellström
2022-02-11 9:49 ` Thomas Hellström
2022-02-11 9:52 ` [Intel-gfx] " Matthew Auld
2022-02-11 9:55 ` Thomas Hellström
2022-02-11 10:00 ` Matthew Auld
2022-02-11 10:14 ` Thomas Hellström
2022-02-10 12:13 ` [Intel-gfx] [PATCH v2 13/15] drm/i915/uapi: add NEEDS_CPU_ACCESS hint Matthew Auld
2022-02-10 12:13 ` Matthew Auld
2022-02-11 9:59 ` [Intel-gfx] " Thomas Hellström
2022-02-11 9:59 ` Thomas Hellström
2022-02-10 12:13 ` [Intel-gfx] [PATCH v2 14/15] drm/i915/uapi: forbid ALLOC_GPU_ONLY for error capture Matthew Auld
2022-02-10 12:13 ` Matthew Auld
2022-02-11 10:06 ` [Intel-gfx] " Thomas Hellström
2022-02-11 10:06 ` Thomas Hellström
2022-02-10 12:13 ` [Intel-gfx] [PATCH v2 15/15] drm/i915/lmem: don't treat small BAR as an error Matthew Auld
2022-02-10 12:13 ` Matthew Auld
2022-02-11 10:08 ` [Intel-gfx] " Thomas Hellström
2022-02-11 10:08 ` Thomas Hellström
2022-02-10 14:40 ` [Intel-gfx] [PATCH v2 00/15] Initial support for small BAR recovery Das, Nirmoy
2022-02-10 15:24 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Initial support for small BAR recovery (rev3) Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220210121313.701004-4-matthew.auld@intel.com \
--to=matthew.auld@intel.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=intel-gfx@lists.freedesktop.org \
--cc=thomas.hellstrom@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.