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From: Jisheng Zhang <jszhang@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PATCH v3 8/8] riscv: defconfig: enable T-HEAD SoC
Date: Sun, 18 Jun 2023 00:15:29 +0800	[thread overview]
Message-ID: <20230617161529.2092-9-jszhang@kernel.org> (raw)
In-Reply-To: <20230617161529.2092-1-jszhang@kernel.org>

Enable T-HEAD SoC config in defconfig to allow the default
upstream kernel to boot on Sipeed Lichee Pi 4A board.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Guo Ren <guoren@kernel.org>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index d98d6e90b2b8..109e4b5b003c 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -27,6 +27,7 @@ CONFIG_EXPERT=y
 CONFIG_PROFILING=y
 CONFIG_SOC_MICROCHIP_POLARFIRE=y
 CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_THEAD=y
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_ARCH_SUNXI=y
-- 
2.40.0


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http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Palmer Dabbelt <palmer@rivosinc.com>
Subject: [PATCH v3 8/8] riscv: defconfig: enable T-HEAD SoC
Date: Sun, 18 Jun 2023 00:15:29 +0800	[thread overview]
Message-ID: <20230617161529.2092-9-jszhang@kernel.org> (raw)
In-Reply-To: <20230617161529.2092-1-jszhang@kernel.org>

Enable T-HEAD SoC config in defconfig to allow the default
upstream kernel to boot on Sipeed Lichee Pi 4A board.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Guo Ren <guoren@kernel.org>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index d98d6e90b2b8..109e4b5b003c 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -27,6 +27,7 @@ CONFIG_EXPERT=y
 CONFIG_PROFILING=y
 CONFIG_SOC_MICROCHIP_POLARFIRE=y
 CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_THEAD=y
 CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_ARCH_SUNXI=y
-- 
2.40.0


  parent reply	other threads:[~2023-06-17 16:27 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-17 16:15 [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 1/8] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Jisheng Zhang
2023-06-17 16:15   ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 2/8] dt-bindings: timer: Add T-HEAD TH1520 clint Jisheng Zhang
2023-06-17 16:15   ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 3/8] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Jisheng Zhang
2023-06-17 16:15   ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 4/8] riscv: Add the T-HEAD SoC family Kconfig option Jisheng Zhang
2023-06-17 16:15   ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 5/8] riscv: dts: add initial T-HEAD TH1520 SoC device tree Jisheng Zhang
2023-06-17 16:15   ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 6/8] riscv: dts: thead: add sipeed Lichee Pi 4A board " Jisheng Zhang
2023-06-17 16:15   ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 7/8] MAINTAINERS: add entry for T-HEAD RISC-V SoC Jisheng Zhang
2023-06-17 16:15   ` Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang [this message]
2023-06-17 16:15   ` [PATCH v3 8/8] riscv: defconfig: enable T-HEAD SoC Jisheng Zhang
2023-06-17 17:02 ` [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Conor Dooley
2023-06-17 17:02   ` Conor Dooley
2023-06-18 16:14   ` Jisheng Zhang
2023-06-18 16:14     ` Jisheng Zhang
2023-06-17 18:20 ` Conor Dooley
2023-06-17 18:20   ` Conor Dooley
2023-06-18 16:25   ` Jisheng Zhang
2023-06-18 16:25     ` Jisheng Zhang
2023-06-18 21:01     ` Conor Dooley
2023-06-18 21:01       ` Conor Dooley
2023-06-20 22:52     ` Conor Dooley
2023-06-20 22:52       ` Conor Dooley
2023-06-20 22:55       ` Conor Dooley
2023-06-20 22:55         ` Conor Dooley
2023-07-25  7:38 ` Xi Ruoyao
2023-07-25  7:38   ` Xi Ruoyao
2023-07-25  7:52   ` Conor Dooley
2023-07-25  7:52     ` Conor Dooley
2023-07-25  8:10     ` Conor Dooley
2023-07-25  8:10       ` Conor Dooley
2023-07-25 14:32       ` Drew Fustini
2023-07-25 14:32         ` Drew Fustini
2023-07-25  8:26     ` Xi Ruoyao
2023-07-25  8:26       ` Xi Ruoyao
2023-07-25 14:58     ` Jisheng Zhang
2023-07-25 14:58       ` Jisheng Zhang
2023-07-26 12:48       ` Xi Ruoyao
2023-07-26 12:48         ` Xi Ruoyao
2023-07-26 15:00         ` Jisheng Zhang
2023-07-26 15:00           ` Jisheng Zhang
2023-07-27  0:14           ` Xi Ruoyao
2023-07-27  0:14             ` Xi Ruoyao
2023-07-27  0:54             ` Xi Ruoyao
2023-07-27  0:54               ` Xi Ruoyao
2023-07-27  9:18               ` Xi Ruoyao
2023-07-27  9:18                 ` Xi Ruoyao
2023-07-27 16:11               ` Jisheng Zhang
2023-07-27 16:11                 ` Jisheng Zhang
2023-07-27 16:29                 ` Xi Ruoyao
2023-07-27 16:29                   ` Xi Ruoyao
2023-07-28  7:04                   ` Drew Fustini
2023-07-28  7:04                     ` Drew Fustini
2023-07-28  7:40                     ` Xi Ruoyao
2023-07-28  7:40                       ` Xi Ruoyao
2023-07-28 10:05                       ` Xi Ruoyao
2023-07-28 10:05                         ` Xi Ruoyao
2023-07-28 10:23                         ` Emil Renner Berthing
2023-07-28 10:23                           ` Emil Renner Berthing
2023-07-28 17:53                           ` Drew Fustini
2023-07-28 17:53                             ` Drew Fustini
2023-07-29  7:11                             ` Xi Ruoyao
2023-07-29  7:11                               ` Xi Ruoyao
2023-07-28  0:11               ` Drew Fustini
2023-07-28  0:11                 ` Drew Fustini
2023-08-11 17:39 ` Drew Fustini
2023-08-11 17:39   ` Drew Fustini
2023-08-11 17:46   ` Conor Dooley
2023-08-11 17:46     ` Conor Dooley

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