From: Jisheng Zhang <jszhang@kernel.org>
To: Xi Ruoyao <xry111@linuxfromscratch.org>
Cc: Conor Dooley <conor.dooley@microchip.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support
Date: Wed, 26 Jul 2023 23:00:55 +0800 [thread overview]
Message-ID: <ZME1J4mpVf5yth32@xhacker> (raw)
In-Reply-To: <3e0994dab495920ac590dc28d6b9d9765abe0c7e.camel@linuxfromscratch.org>
On Wed, Jul 26, 2023 at 08:48:08PM +0800, Xi Ruoyao wrote:
> On Tue, 2023-07-25 at 22:58 +0800, Jisheng Zhang wrote:
> > > Are you using the vendor OpenSBI? IIRC, and the lads can probably
> > > correct me here, you need to have an OpenSBI that contains
> > > https://github.com/riscv-software-src/opensbi/commit/78c2b19218bd62653b9fb31623a42ced45f38ea6
> > > which the vendor supplied OpenSBI does not have.
> >
> > To ruoyao,
> >
> > I believe Conor has provided enough details and given you the clues.
> > And I believe you were using the legacy opensbi. If you still reproduce
> > the issue with the latest opensbi generic platform, plz provided full
> > uart log from openSBI to the kernel panic point.
>
> Thanks you all for the help!
>
> I downloaded the latest opensbi 1.3.1 and put fw_dynamic.bin in the
> generic directory into /boot (renamed not to overwritten the vendor
> one), then loaded it onto address 0 from the vendor u-boot. Now the
> plic issue was gone, but another panic happened. Log is pasted at the
> end of this mail.
>
> I've not set up an initramfs, so I'm expecting a panic after all, but I
> think it should be "VFS: cannot mount root fs" or something, not
> "unexpected interrupt cause".
>
> Is it a problem with vendor u-boot? Should I try loading a latest u-
> boot from the vendor one, and then load the kernel with the new u-boot?
which dts r u using? see below.
>
> Or maybe my toolchain (GCC 13.1.0, Binutils-2.40, with no patches) can
> miscompile the kernel?
>
> ## Flattened Device Tree blob at 46000000
> Booting using the fdt blob at 0x46000000
> Using Device Tree in place at 0000000046000000, end 00000000460050c4
>
> Starting kernel ...
>
>
> OpenSBI v1.3.1
> ____ _____ ____ _____
> / __ \ / ____| _ \_ _|
> | | | |_ __ ___ _ __ | (___ | |_) || |
> | | | | '_ \ / _ \ '_ \ \___ \| _ < | |
> | |__| | |_) | __/ | | |____) | |_) || |_
> \____/| .__/ \___|_| |_|_____/|___/_____|
> | |
> |_|
>
> Platform Name : Sipeed Lichee Pi 4A
> Platform Features : medeleg
> Platform HART Count : 4
> Platform IPI Device : aclint-mswi
> Platform Timer Device : aclint-mtimer @ 3000000Hz
> Platform Console Device : uart8250
> Platform HSM Device : ---
> Platform PMU Device : ---
> Platform Reboot Device : ---
> Platform Shutdown Device : ---
> Platform Suspend Device : ---
> Platform CPPC Device : ---
> Firmware Base : 0x0
> Firmware Size : 224 KB
> Firmware RW Offset : 0x20000
> Firmware RW Size : 96 KB
> Firmware Heap Offset : 0x2e000
> Firmware Heap Size : 40 KB (total), 2 KB (reserved), 9 KB (used), 28 KB (free)
> Firmware Scratch Size : 4096 B (total), 760 B (used), 3336 B (free)
> Runtime SBI Version : 1.0
>
> Domain0 Name : root
> Domain0 Boot HART : 0
> Domain0 HARTs : 0*,1*,2*,3*
> Domain0 Region00 : 0x000000ffdc008000-0x000000ffdc00bfff M: (I,R,W) S/U: ()
> Domain0 Region01 : 0x000000ffdc000000-0x000000ffdc007fff M: (I,R,W) S/U: ()
> Domain0 Region02 : 0x0000000000000000-0x000000000001ffff M: (R,X) S/U: ()
> Domain0 Region03 : 0x0000000000020000-0x000000000003ffff M: (R,W) S/U: ()
> Domain0 Region04 : 0x0000000000000000-0xffffffffffffffff M: (R,W,X) S/U: (R,W,X)
> Domain0 Next Address : 0x0000000040200000
> Domain0 Next Arg1 : 0x0000000046000000
> Domain0 Next Mode : S-mode
> Domain0 SysReset : yes
> Domain0 SysSuspend : yes
>
> Boot HART ID : 0
> Boot HART Domain : root
> Boot HART Priv Version : v1.11
> Boot HART Base ISA : rv64imafdcvx
what? I don't think the mainline dts provide v and x.
> Boot HART ISA Extensions : time
> Boot HART PMP Count : 0
> Boot HART PMP Granularity : 0
> Boot HART PMP Address Bits: 0
> Boot HART MHPM Count : 16
> Boot HART MIDELEG : 0x0000000000000222
> Boot HART MEDELEG : 0x000000000000b109
> [ 0.000000] Linux version 6.5.0-rc3 (lfs@stargazer) (riscv64-lfs-linux-gnu-gcc (GCC) 13.1.0, GNU ld (GNU Binutils) 2.40) #1 SMP PREEMPT Tue Jul 25 13:38:20 CST 2023
> [ 0.000000] Machine model: Sipeed Lichee Pi 4A
> [ 0.000000] SBI specification v1.0 detected
> [ 0.000000] SBI implementation ID=0x1 Version=0x10003
> [ 0.000000] SBI TIME extension detected
> [ 0.000000] SBI IPI extension detected
> [ 0.000000] SBI RFENCE extension detected
> [ 0.000000] earlycon: uart0 at MMIO32 0x000000ffe7014000 (options '115200n8')
> [ 0.000000] printk: bootconsole [uart0] enabled
> [ 0.000000] efi: UEFI not found.
> [ 0.000000] OF: reserved mem: 0x0000000000000000..0x000000000001ffff (128 KiB) nomap non-reusable mmode_resv0@0
> [ 0.000000] OF: reserved mem: 0x0000000000020000..0x000000000003ffff (128 KiB) nomap non-reusable mmode_resv1@20000
> [ 0.000000] Zone ranges:
> [ 0.000000] DMA32 [mem 0x0000000000000000-0x00000000ffffffff]
> [ 0.000000] Normal [mem 0x0000000100000000-0x00000001ffffffff]
> [ 0.000000] Movable zone start for each node
> [ 0.000000] Early memory node ranges
> [ 0.000000] node 0: [mem 0x0000000000000000-0x000000000003ffff]
> [ 0.000000] node 0: [mem 0x0000000000040000-0x00000001ffffffff]
> [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000001ffffffff]
> [ 0.000000] SBI HSM extension detected
> [ 0.000000] riscv: base ISA extensions acdfim
> [ 0.000000] riscv: ELF capabilities acdfim
> [ 0.000000] percpu: Embedded 17 pages/cpu s38184 r0 d31448 u69632
> [ 0.000000] Kernel command line: earlycon console=ttyS0,115200
> [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
> [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
> [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2064384
> [ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
> [ 0.000000] software IO TLB: area num 4.
> [ 0.000000] software IO TLB: mapped [mem 0x00000000fbfff000-0x00000000fffff000] (64MB)
> [ 0.000000] Memory: 8145300K/8388608K available (4922K kernel code, 4786K rwdata, 2048K rodata, 2148K init, 393K bss, 243308K reserved, 0K cma-reserved)
> [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
> [ 0.000000] rcu: Preemptible hierarchical RCU implementation.
> [ 0.000000] rcu: RCU event tracing is enabled.
> [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=4.
> [ 0.000000] Trampoline variant of Tasks RCU enabled.
> [ 0.000000] Tracing variant of Tasks RCU enabled.
> [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 100 jiffies.
> [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
> [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
> [ 0.000000] riscv-intc: 64 local interrupts mapped
> [ 0.000000] plic: interrupt-controller@ffd8000000: mapped 240 interrupts with 4 handlers for 8 contexts.
> [ 0.000000] riscv: providing IPIs using SBI IPI extension
> [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
> [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1623fa770, max_idle_ns: 881590404476 ns
> [ 0.000001] sched_clock: 64 bits at 3000kHz, resolution 333ns, wraps every 4398046511097ns
> [ 0.008488] Console: colour dummy device 80x25
> [ 0.012944] Kernel panic - not syncing: unexpected interrupt cause
> [ 0.012952] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 6.5.0-rc3 #1
> [ 0.012964] Hardware name: Sipeed Lichee Pi 4A (DT)
> [ 0.012970] Call Trace:
> [ 0.012976] [<ffffffff80004c38>] walk_stackframe+0x0/0x7e
> [ 0.013002] [<ffffffff804c868c>] dump_stack_lvl+0x34/0x4e
> [ 0.013022] [<ffffffff804c1334>] panic+0xf2/0x292
> [ 0.013035] [<ffffffff802cddc0>] riscv_intc_irq+0x34/0x38
> [ 0.013052] [<ffffffff804c8716>] handle_riscv_irq+0x66/0xa6
> [ 0.059145] ---[ end Kernel panic - not syncing: unexpected interrupt cause ]---
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Xi Ruoyao <xry111@linuxfromscratch.org>
Cc: Conor Dooley <conor.dooley@microchip.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support
Date: Wed, 26 Jul 2023 23:00:55 +0800 [thread overview]
Message-ID: <ZME1J4mpVf5yth32@xhacker> (raw)
In-Reply-To: <3e0994dab495920ac590dc28d6b9d9765abe0c7e.camel@linuxfromscratch.org>
On Wed, Jul 26, 2023 at 08:48:08PM +0800, Xi Ruoyao wrote:
> On Tue, 2023-07-25 at 22:58 +0800, Jisheng Zhang wrote:
> > > Are you using the vendor OpenSBI? IIRC, and the lads can probably
> > > correct me here, you need to have an OpenSBI that contains
> > > https://github.com/riscv-software-src/opensbi/commit/78c2b19218bd62653b9fb31623a42ced45f38ea6
> > > which the vendor supplied OpenSBI does not have.
> >
> > To ruoyao,
> >
> > I believe Conor has provided enough details and given you the clues.
> > And I believe you were using the legacy opensbi. If you still reproduce
> > the issue with the latest opensbi generic platform, plz provided full
> > uart log from openSBI to the kernel panic point.
>
> Thanks you all for the help!
>
> I downloaded the latest opensbi 1.3.1 and put fw_dynamic.bin in the
> generic directory into /boot (renamed not to overwritten the vendor
> one), then loaded it onto address 0 from the vendor u-boot. Now the
> plic issue was gone, but another panic happened. Log is pasted at the
> end of this mail.
>
> I've not set up an initramfs, so I'm expecting a panic after all, but I
> think it should be "VFS: cannot mount root fs" or something, not
> "unexpected interrupt cause".
>
> Is it a problem with vendor u-boot? Should I try loading a latest u-
> boot from the vendor one, and then load the kernel with the new u-boot?
which dts r u using? see below.
>
> Or maybe my toolchain (GCC 13.1.0, Binutils-2.40, with no patches) can
> miscompile the kernel?
>
> ## Flattened Device Tree blob at 46000000
> Booting using the fdt blob at 0x46000000
> Using Device Tree in place at 0000000046000000, end 00000000460050c4
>
> Starting kernel ...
>
>
> OpenSBI v1.3.1
> ____ _____ ____ _____
> / __ \ / ____| _ \_ _|
> | | | |_ __ ___ _ __ | (___ | |_) || |
> | | | | '_ \ / _ \ '_ \ \___ \| _ < | |
> | |__| | |_) | __/ | | |____) | |_) || |_
> \____/| .__/ \___|_| |_|_____/|___/_____|
> | |
> |_|
>
> Platform Name : Sipeed Lichee Pi 4A
> Platform Features : medeleg
> Platform HART Count : 4
> Platform IPI Device : aclint-mswi
> Platform Timer Device : aclint-mtimer @ 3000000Hz
> Platform Console Device : uart8250
> Platform HSM Device : ---
> Platform PMU Device : ---
> Platform Reboot Device : ---
> Platform Shutdown Device : ---
> Platform Suspend Device : ---
> Platform CPPC Device : ---
> Firmware Base : 0x0
> Firmware Size : 224 KB
> Firmware RW Offset : 0x20000
> Firmware RW Size : 96 KB
> Firmware Heap Offset : 0x2e000
> Firmware Heap Size : 40 KB (total), 2 KB (reserved), 9 KB (used), 28 KB (free)
> Firmware Scratch Size : 4096 B (total), 760 B (used), 3336 B (free)
> Runtime SBI Version : 1.0
>
> Domain0 Name : root
> Domain0 Boot HART : 0
> Domain0 HARTs : 0*,1*,2*,3*
> Domain0 Region00 : 0x000000ffdc008000-0x000000ffdc00bfff M: (I,R,W) S/U: ()
> Domain0 Region01 : 0x000000ffdc000000-0x000000ffdc007fff M: (I,R,W) S/U: ()
> Domain0 Region02 : 0x0000000000000000-0x000000000001ffff M: (R,X) S/U: ()
> Domain0 Region03 : 0x0000000000020000-0x000000000003ffff M: (R,W) S/U: ()
> Domain0 Region04 : 0x0000000000000000-0xffffffffffffffff M: (R,W,X) S/U: (R,W,X)
> Domain0 Next Address : 0x0000000040200000
> Domain0 Next Arg1 : 0x0000000046000000
> Domain0 Next Mode : S-mode
> Domain0 SysReset : yes
> Domain0 SysSuspend : yes
>
> Boot HART ID : 0
> Boot HART Domain : root
> Boot HART Priv Version : v1.11
> Boot HART Base ISA : rv64imafdcvx
what? I don't think the mainline dts provide v and x.
> Boot HART ISA Extensions : time
> Boot HART PMP Count : 0
> Boot HART PMP Granularity : 0
> Boot HART PMP Address Bits: 0
> Boot HART MHPM Count : 16
> Boot HART MIDELEG : 0x0000000000000222
> Boot HART MEDELEG : 0x000000000000b109
> [ 0.000000] Linux version 6.5.0-rc3 (lfs@stargazer) (riscv64-lfs-linux-gnu-gcc (GCC) 13.1.0, GNU ld (GNU Binutils) 2.40) #1 SMP PREEMPT Tue Jul 25 13:38:20 CST 2023
> [ 0.000000] Machine model: Sipeed Lichee Pi 4A
> [ 0.000000] SBI specification v1.0 detected
> [ 0.000000] SBI implementation ID=0x1 Version=0x10003
> [ 0.000000] SBI TIME extension detected
> [ 0.000000] SBI IPI extension detected
> [ 0.000000] SBI RFENCE extension detected
> [ 0.000000] earlycon: uart0 at MMIO32 0x000000ffe7014000 (options '115200n8')
> [ 0.000000] printk: bootconsole [uart0] enabled
> [ 0.000000] efi: UEFI not found.
> [ 0.000000] OF: reserved mem: 0x0000000000000000..0x000000000001ffff (128 KiB) nomap non-reusable mmode_resv0@0
> [ 0.000000] OF: reserved mem: 0x0000000000020000..0x000000000003ffff (128 KiB) nomap non-reusable mmode_resv1@20000
> [ 0.000000] Zone ranges:
> [ 0.000000] DMA32 [mem 0x0000000000000000-0x00000000ffffffff]
> [ 0.000000] Normal [mem 0x0000000100000000-0x00000001ffffffff]
> [ 0.000000] Movable zone start for each node
> [ 0.000000] Early memory node ranges
> [ 0.000000] node 0: [mem 0x0000000000000000-0x000000000003ffff]
> [ 0.000000] node 0: [mem 0x0000000000040000-0x00000001ffffffff]
> [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000001ffffffff]
> [ 0.000000] SBI HSM extension detected
> [ 0.000000] riscv: base ISA extensions acdfim
> [ 0.000000] riscv: ELF capabilities acdfim
> [ 0.000000] percpu: Embedded 17 pages/cpu s38184 r0 d31448 u69632
> [ 0.000000] Kernel command line: earlycon console=ttyS0,115200
> [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
> [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
> [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2064384
> [ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
> [ 0.000000] software IO TLB: area num 4.
> [ 0.000000] software IO TLB: mapped [mem 0x00000000fbfff000-0x00000000fffff000] (64MB)
> [ 0.000000] Memory: 8145300K/8388608K available (4922K kernel code, 4786K rwdata, 2048K rodata, 2148K init, 393K bss, 243308K reserved, 0K cma-reserved)
> [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
> [ 0.000000] rcu: Preemptible hierarchical RCU implementation.
> [ 0.000000] rcu: RCU event tracing is enabled.
> [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=4.
> [ 0.000000] Trampoline variant of Tasks RCU enabled.
> [ 0.000000] Tracing variant of Tasks RCU enabled.
> [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 100 jiffies.
> [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
> [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
> [ 0.000000] riscv-intc: 64 local interrupts mapped
> [ 0.000000] plic: interrupt-controller@ffd8000000: mapped 240 interrupts with 4 handlers for 8 contexts.
> [ 0.000000] riscv: providing IPIs using SBI IPI extension
> [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
> [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1623fa770, max_idle_ns: 881590404476 ns
> [ 0.000001] sched_clock: 64 bits at 3000kHz, resolution 333ns, wraps every 4398046511097ns
> [ 0.008488] Console: colour dummy device 80x25
> [ 0.012944] Kernel panic - not syncing: unexpected interrupt cause
> [ 0.012952] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 6.5.0-rc3 #1
> [ 0.012964] Hardware name: Sipeed Lichee Pi 4A (DT)
> [ 0.012970] Call Trace:
> [ 0.012976] [<ffffffff80004c38>] walk_stackframe+0x0/0x7e
> [ 0.013002] [<ffffffff804c868c>] dump_stack_lvl+0x34/0x4e
> [ 0.013022] [<ffffffff804c1334>] panic+0xf2/0x292
> [ 0.013035] [<ffffffff802cddc0>] riscv_intc_irq+0x34/0x38
> [ 0.013052] [<ffffffff804c8716>] handle_riscv_irq+0x66/0xa6
> [ 0.059145] ---[ end Kernel panic - not syncing: unexpected interrupt cause ]---
>
next prev parent reply other threads:[~2023-07-26 15:12 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-17 16:15 [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 1/8] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 2/8] dt-bindings: timer: Add T-HEAD TH1520 clint Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 3/8] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 4/8] riscv: Add the T-HEAD SoC family Kconfig option Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 5/8] riscv: dts: add initial T-HEAD TH1520 SoC device tree Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 6/8] riscv: dts: thead: add sipeed Lichee Pi 4A board " Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 7/8] MAINTAINERS: add entry for T-HEAD RISC-V SoC Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 8/8] riscv: defconfig: enable T-HEAD SoC Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 17:02 ` [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Conor Dooley
2023-06-17 17:02 ` Conor Dooley
2023-06-18 16:14 ` Jisheng Zhang
2023-06-18 16:14 ` Jisheng Zhang
2023-06-17 18:20 ` Conor Dooley
2023-06-17 18:20 ` Conor Dooley
2023-06-18 16:25 ` Jisheng Zhang
2023-06-18 16:25 ` Jisheng Zhang
2023-06-18 21:01 ` Conor Dooley
2023-06-18 21:01 ` Conor Dooley
2023-06-20 22:52 ` Conor Dooley
2023-06-20 22:52 ` Conor Dooley
2023-06-20 22:55 ` Conor Dooley
2023-06-20 22:55 ` Conor Dooley
2023-07-25 7:38 ` Xi Ruoyao
2023-07-25 7:38 ` Xi Ruoyao
2023-07-25 7:52 ` Conor Dooley
2023-07-25 7:52 ` Conor Dooley
2023-07-25 8:10 ` Conor Dooley
2023-07-25 8:10 ` Conor Dooley
2023-07-25 14:32 ` Drew Fustini
2023-07-25 14:32 ` Drew Fustini
2023-07-25 8:26 ` Xi Ruoyao
2023-07-25 8:26 ` Xi Ruoyao
2023-07-25 14:58 ` Jisheng Zhang
2023-07-25 14:58 ` Jisheng Zhang
2023-07-26 12:48 ` Xi Ruoyao
2023-07-26 12:48 ` Xi Ruoyao
2023-07-26 15:00 ` Jisheng Zhang [this message]
2023-07-26 15:00 ` Jisheng Zhang
2023-07-27 0:14 ` Xi Ruoyao
2023-07-27 0:14 ` Xi Ruoyao
2023-07-27 0:54 ` Xi Ruoyao
2023-07-27 0:54 ` Xi Ruoyao
2023-07-27 9:18 ` Xi Ruoyao
2023-07-27 9:18 ` Xi Ruoyao
2023-07-27 16:11 ` Jisheng Zhang
2023-07-27 16:11 ` Jisheng Zhang
2023-07-27 16:29 ` Xi Ruoyao
2023-07-27 16:29 ` Xi Ruoyao
2023-07-28 7:04 ` Drew Fustini
2023-07-28 7:04 ` Drew Fustini
2023-07-28 7:40 ` Xi Ruoyao
2023-07-28 7:40 ` Xi Ruoyao
2023-07-28 10:05 ` Xi Ruoyao
2023-07-28 10:05 ` Xi Ruoyao
2023-07-28 10:23 ` Emil Renner Berthing
2023-07-28 10:23 ` Emil Renner Berthing
2023-07-28 17:53 ` Drew Fustini
2023-07-28 17:53 ` Drew Fustini
2023-07-29 7:11 ` Xi Ruoyao
2023-07-29 7:11 ` Xi Ruoyao
2023-07-28 0:11 ` Drew Fustini
2023-07-28 0:11 ` Drew Fustini
2023-08-11 17:39 ` Drew Fustini
2023-08-11 17:39 ` Drew Fustini
2023-08-11 17:46 ` Conor Dooley
2023-08-11 17:46 ` Conor Dooley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ZME1J4mpVf5yth32@xhacker \
--to=jszhang@kernel.org \
--cc=aou@eecs.berkeley.edu \
--cc=conor+dt@kernel.org \
--cc=conor.dooley@microchip.com \
--cc=daniel.lezcano@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=guoren@kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=maz@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=tglx@linutronix.de \
--cc=wefu@redhat.com \
--cc=xry111@linuxfromscratch.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.