From: Jisheng Zhang <jszhang@kernel.org>
To: Conor Dooley <conor@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support
Date: Mon, 19 Jun 2023 00:14:01 +0800 [thread overview]
Message-ID: <ZI8tSYgpz85gYJqW@xhacker> (raw)
In-Reply-To: <20230617-preppy-eggbeater-a256e963bcc6@spud>
On Sat, Jun 17, 2023 at 06:02:20PM +0100, Conor Dooley wrote:
> Hey Jisheng,
Hi Conor,
>
> On Sun, Jun 18, 2023 at 12:15:21AM +0800, Jisheng Zhang wrote:
> > Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
> > module which is powered by T-HEAD's TH1520 SoC. Add minimal device
> > tree files for the core module and the development board.
> >
> > Support basic uart/gpio/dmac drivers, so supports booting to a basic
> > shell.
> >
> > NOTE: the thead cpu reset dt-binding and DT node are removed in v3. This
> > makes secondary CPUs unable to be online.
>
> The kernel doesn't do anything with that node though, so if you were to
> load a fitImage in U-Boot containing this DT, having booted with
> whatever the factory provided OpenSBI has, that limitation doesn't
> apply, right?
The cpu reset DT node is for opensbi, linux kernel doesn't need it.
So you are right: if the u-boot contains the DT node(no matter how
the DT node is added, statically added or dynamically added with
uboot cmd), the limitation doesn't apply.
>
> > However, minimal th1520
> > support is better than nothing. And the community has been working on
> > and will work on the cpu reset dt-binding, for example, Conor, Guo and
> > Jessica are discussing about it, I have seen valuable comments and
> > inputs from them. I believe we can add back cpu reset in next
> > development window.
>
> I'll go take a look through this, if it's good I'll apply it and send it
> on to Arnd for 6.5? Although I assume it is fine since v2 was nearly
Thank you for helping to send out this Pull request!
> fine!
>
> Cheers,
> Conor.
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Conor Dooley <conor@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Guo Ren <guoren@kernel.org>, Fu Wei <wefu@redhat.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support
Date: Mon, 19 Jun 2023 00:14:01 +0800 [thread overview]
Message-ID: <ZI8tSYgpz85gYJqW@xhacker> (raw)
In-Reply-To: <20230617-preppy-eggbeater-a256e963bcc6@spud>
On Sat, Jun 17, 2023 at 06:02:20PM +0100, Conor Dooley wrote:
> Hey Jisheng,
Hi Conor,
>
> On Sun, Jun 18, 2023 at 12:15:21AM +0800, Jisheng Zhang wrote:
> > Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
> > module which is powered by T-HEAD's TH1520 SoC. Add minimal device
> > tree files for the core module and the development board.
> >
> > Support basic uart/gpio/dmac drivers, so supports booting to a basic
> > shell.
> >
> > NOTE: the thead cpu reset dt-binding and DT node are removed in v3. This
> > makes secondary CPUs unable to be online.
>
> The kernel doesn't do anything with that node though, so if you were to
> load a fitImage in U-Boot containing this DT, having booted with
> whatever the factory provided OpenSBI has, that limitation doesn't
> apply, right?
The cpu reset DT node is for opensbi, linux kernel doesn't need it.
So you are right: if the u-boot contains the DT node(no matter how
the DT node is added, statically added or dynamically added with
uboot cmd), the limitation doesn't apply.
>
> > However, minimal th1520
> > support is better than nothing. And the community has been working on
> > and will work on the cpu reset dt-binding, for example, Conor, Guo and
> > Jessica are discussing about it, I have seen valuable comments and
> > inputs from them. I believe we can add back cpu reset in next
> > development window.
>
> I'll go take a look through this, if it's good I'll apply it and send it
> on to Arnd for 6.5? Although I assume it is fine since v2 was nearly
Thank you for helping to send out this Pull request!
> fine!
>
> Cheers,
> Conor.
next prev parent reply other threads:[~2023-06-18 16:25 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-17 16:15 [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 1/8] dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 2/8] dt-bindings: timer: Add T-HEAD TH1520 clint Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 3/8] dt-bindings: riscv: Add T-HEAD TH1520 board compatibles Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 4/8] riscv: Add the T-HEAD SoC family Kconfig option Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 5/8] riscv: dts: add initial T-HEAD TH1520 SoC device tree Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 6/8] riscv: dts: thead: add sipeed Lichee Pi 4A board " Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 7/8] MAINTAINERS: add entry for T-HEAD RISC-V SoC Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 16:15 ` [PATCH v3 8/8] riscv: defconfig: enable T-HEAD SoC Jisheng Zhang
2023-06-17 16:15 ` Jisheng Zhang
2023-06-17 17:02 ` [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support Conor Dooley
2023-06-17 17:02 ` Conor Dooley
2023-06-18 16:14 ` Jisheng Zhang [this message]
2023-06-18 16:14 ` Jisheng Zhang
2023-06-17 18:20 ` Conor Dooley
2023-06-17 18:20 ` Conor Dooley
2023-06-18 16:25 ` Jisheng Zhang
2023-06-18 16:25 ` Jisheng Zhang
2023-06-18 21:01 ` Conor Dooley
2023-06-18 21:01 ` Conor Dooley
2023-06-20 22:52 ` Conor Dooley
2023-06-20 22:52 ` Conor Dooley
2023-06-20 22:55 ` Conor Dooley
2023-06-20 22:55 ` Conor Dooley
2023-07-25 7:38 ` Xi Ruoyao
2023-07-25 7:38 ` Xi Ruoyao
2023-07-25 7:52 ` Conor Dooley
2023-07-25 7:52 ` Conor Dooley
2023-07-25 8:10 ` Conor Dooley
2023-07-25 8:10 ` Conor Dooley
2023-07-25 14:32 ` Drew Fustini
2023-07-25 14:32 ` Drew Fustini
2023-07-25 8:26 ` Xi Ruoyao
2023-07-25 8:26 ` Xi Ruoyao
2023-07-25 14:58 ` Jisheng Zhang
2023-07-25 14:58 ` Jisheng Zhang
2023-07-26 12:48 ` Xi Ruoyao
2023-07-26 12:48 ` Xi Ruoyao
2023-07-26 15:00 ` Jisheng Zhang
2023-07-26 15:00 ` Jisheng Zhang
2023-07-27 0:14 ` Xi Ruoyao
2023-07-27 0:14 ` Xi Ruoyao
2023-07-27 0:54 ` Xi Ruoyao
2023-07-27 0:54 ` Xi Ruoyao
2023-07-27 9:18 ` Xi Ruoyao
2023-07-27 9:18 ` Xi Ruoyao
2023-07-27 16:11 ` Jisheng Zhang
2023-07-27 16:11 ` Jisheng Zhang
2023-07-27 16:29 ` Xi Ruoyao
2023-07-27 16:29 ` Xi Ruoyao
2023-07-28 7:04 ` Drew Fustini
2023-07-28 7:04 ` Drew Fustini
2023-07-28 7:40 ` Xi Ruoyao
2023-07-28 7:40 ` Xi Ruoyao
2023-07-28 10:05 ` Xi Ruoyao
2023-07-28 10:05 ` Xi Ruoyao
2023-07-28 10:23 ` Emil Renner Berthing
2023-07-28 10:23 ` Emil Renner Berthing
2023-07-28 17:53 ` Drew Fustini
2023-07-28 17:53 ` Drew Fustini
2023-07-29 7:11 ` Xi Ruoyao
2023-07-29 7:11 ` Xi Ruoyao
2023-07-28 0:11 ` Drew Fustini
2023-07-28 0:11 ` Drew Fustini
2023-08-11 17:39 ` Drew Fustini
2023-08-11 17:39 ` Drew Fustini
2023-08-11 17:46 ` Conor Dooley
2023-08-11 17:46 ` Conor Dooley
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