From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
ajones@ventanamicro.com, philmd@linaro.org,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v2 14/19] target/riscv/cpu.c: export set_misa()
Date: Wed, 6 Sep 2023 06:16:41 -0300 [thread overview]
Message-ID: <20230906091647.1667171-15-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com>
We'll move riscv_init_max_cpu_extensions() to tcg-cpu.c in the next
patch and set_misa() needs to be usable from there.
Rename it to riscv_cpu_set_misa() and make it public.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 34 ++++++++++++++++++----------------
target/riscv/cpu.h | 1 +
2 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 665c21af6a..cf191d576e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -294,7 +294,7 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
}
}
-static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
+void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
{
env->misa_mxl_max = env->misa_mxl = mxl;
env->misa_ext_mask = env->misa_ext = ext;
@@ -399,9 +399,9 @@ static void riscv_any_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env;
#if defined(TARGET_RISCV32)
- set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+ riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#elif defined(TARGET_RISCV64)
- set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+ riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#endif
#ifndef CONFIG_USER_ONLY
@@ -428,7 +428,7 @@ static void riscv_max_cpu_init(Object *obj)
#ifdef TARGET_RISCV32
mlx = MXL_RV32;
#endif
- set_misa(env, mlx, 0);
+ riscv_cpu_set_misa(env, mlx, 0);
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
@@ -441,7 +441,7 @@ static void rv64_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
- set_misa(env, MXL_RV64, 0);
+ riscv_cpu_set_misa(env, MXL_RV64, 0);
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
@@ -453,7 +453,8 @@ static void rv64_sifive_u_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env;
- set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ riscv_cpu_set_misa(env, MXL_RV64,
+ RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
@@ -471,7 +472,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
+ riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -488,7 +489,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
+ riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_11_0;
cpu->cfg.ext_zfa = true;
@@ -519,7 +520,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
+ riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
env->priv_ver = PRIV_VERSION_1_12_0;
/* Enable ISA extensions */
@@ -564,7 +565,7 @@ static void rv128_base_cpu_init(Object *obj)
}
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
- set_misa(env, MXL_RV128, 0);
+ riscv_cpu_set_misa(env, MXL_RV128, 0);
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
@@ -576,7 +577,7 @@ static void rv32_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
/* We set this in the realise function */
- set_misa(env, MXL_RV32, 0);
+ riscv_cpu_set_misa(env, MXL_RV32, 0);
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
@@ -588,7 +589,8 @@ static void rv32_sifive_u_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env;
- set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ riscv_cpu_set_misa(env, MXL_RV32,
+ RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
@@ -606,7 +608,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
+ riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -623,7 +625,7 @@ static void rv32_ibex_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
+ riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_11_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -641,7 +643,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
+ riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -1618,7 +1620,7 @@ static void riscv_init_max_cpu_extensions(Object *obj)
const RISCVCPUMultiExtConfig *prop;
/* Enable RVG, RVJ and RVV that are disabled by default */
- set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
+ riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
isa_ext_update_enabled(cpu, prop->offset, true);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 24d12a9503..cb6372e6e7 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -713,6 +713,7 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
int cpu_cfg_ext_get_min_version(uint32_t ext_offset);
+void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu);
typedef struct RISCVCPUMultiExtConfig {
--
2.41.0
next prev parent reply other threads:[~2023-09-06 9:21 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-06 9:16 [PATCH v2 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 01/19] target/riscv: introduce TCG AccelCPUClass Daniel Henrique Barboza
2023-09-19 9:51 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn() Daniel Henrique Barboza
2023-09-19 9:54 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c Daniel Henrique Barboza
2023-09-19 10:59 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 04/19] target/riscv: move riscv_tcg_ops " Daniel Henrique Barboza
2023-09-19 11:08 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 05/19] target/riscv/cpu.c: add .instance_post_init() Daniel Henrique Barboza
2023-09-11 7:08 ` Andrew Jones
2023-09-19 9:16 ` LIU Zhiwei
2023-09-19 16:07 ` Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 06/19] target/riscv: move 'host' CPU declaration to kvm.c Daniel Henrique Barboza
2023-09-19 11:11 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 07/19] target/riscv/cpu.c: mark extensions arrays as 'const' Daniel Henrique Barboza
2023-09-19 11:19 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c Daniel Henrique Barboza
2023-09-19 11:25 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 09/19] target/riscv: make riscv_add_satp_mode_properties() public Daniel Henrique Barboza
2023-09-11 7:09 ` Andrew Jones
2023-09-19 11:26 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 10/19] target/riscv: remove kvm-stub.c Daniel Henrique Barboza
2023-09-06 10:23 ` Philippe Mathieu-Daudé
2023-09-11 7:49 ` Andrew Jones
2023-09-11 9:04 ` Andrew Jones
2023-09-11 12:23 ` Daniel Henrique Barboza
2023-09-12 10:48 ` Daniel Henrique Barboza
2023-09-12 11:15 ` Philippe Mathieu-Daudé
2023-09-12 12:03 ` Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 11/19] target/riscv: introduce KVM AccelCPUClass Daniel Henrique Barboza
2023-09-11 7:52 ` Andrew Jones
2023-09-19 11:37 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 12/19] target/riscv: move KVM only files to kvm subdir Daniel Henrique Barboza
2023-09-19 11:37 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 13/19] target/riscv/kvm: do not use riscv_cpu_add_misa_properties() Daniel Henrique Barboza
2023-09-06 9:16 ` Daniel Henrique Barboza [this message]
2023-09-06 10:18 ` [PATCH v2 14/19] target/riscv/cpu.c: export set_misa() Philippe Mathieu-Daudé
2023-09-11 7:54 ` Andrew Jones
2023-09-06 9:16 ` [PATCH v2 15/19] target/riscv/tcg: introduce tcg_cpu_instance_init() Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 16/19] target/riscv/cpu.c: make misa_ext_cfgs[] 'const' Daniel Henrique Barboza
2023-09-11 7:56 ` Andrew Jones
2023-09-06 9:16 ` [PATCH v2 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 18/19] target/riscv/cpu.c: export isa_edata_arr[] Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c Daniel Henrique Barboza
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230906091647.1667171-15-dbarboza@ventanamicro.com \
--to=dbarboza@ventanamicro.com \
--cc=ajones@ventanamicro.com \
--cc=alistair.francis@wdc.com \
--cc=bmeng@tinylab.org \
--cc=liweiwei@iscas.ac.cn \
--cc=palmer@rivosinc.com \
--cc=philmd@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.