From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
ajones@ventanamicro.com, philmd@linaro.org,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v2 07/19] target/riscv/cpu.c: mark extensions arrays as 'const'
Date: Wed, 6 Sep 2023 06:16:34 -0300 [thread overview]
Message-ID: <20230906091647.1667171-8-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com>
We'll need to export these arrays to the accelerator classes in the next
patches. Mark them as 'const' now because they should not be modified at
runtime.
Note that 'riscv_cpu_options' will also be exported, but can't be marked
as 'const', because the properties are changed via
qdev_property_add_static().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu.c | 22 +++++++++++++---------
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c15bb572d4..50c2819d68 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1407,7 +1407,7 @@ typedef struct RISCVCPUMultiExtConfig {
{.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
.enabled = _defval}
-static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
+static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true),
@@ -1469,7 +1469,7 @@ static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
DEFINE_PROP_END_OF_LIST(),
};
-static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
+static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
@@ -1487,7 +1487,7 @@ static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
};
/* These are experimental so mark with 'x-' */
-static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
+static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
/* ePMP 0.9.3 */
MULTI_EXT_CFG_BOOL("x-epmp", epmp, false),
MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false),
@@ -1558,7 +1558,7 @@ static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name,
}
static void cpu_add_multi_ext_prop(Object *cpu_obj,
- RISCVCPUMultiExtConfig *multi_cfg)
+ const RISCVCPUMultiExtConfig *multi_cfg)
{
object_property_add(cpu_obj, multi_cfg->name, "bool",
cpu_get_multi_ext_cfg,
@@ -1594,11 +1594,13 @@ static void cpu_set_cfg_unavailable(Object *obj, Visitor *v,
#endif
static void riscv_cpu_add_multiext_prop_array(Object *obj,
- RISCVCPUMultiExtConfig *array)
+ const RISCVCPUMultiExtConfig *array)
{
+ const RISCVCPUMultiExtConfig *prop;
+
g_assert(array);
- for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
+ for (prop = array; prop && prop->name; prop++) {
cpu_add_multi_ext_prop(obj, prop);
}
}
@@ -1622,11 +1624,13 @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_name)
}
static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj,
- RISCVCPUMultiExtConfig *array)
+ const RISCVCPUMultiExtConfig *array)
{
+ const RISCVCPUMultiExtConfig *prop;
+
g_assert(array);
- for (RISCVCPUMultiExtConfig *prop = array; prop && prop->name; prop++) {
+ for (prop = array; prop && prop->name; prop++) {
riscv_cpu_add_kvm_unavail_prop(obj, prop->name);
}
}
@@ -1689,7 +1693,7 @@ static void riscv_init_max_cpu_extensions(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env;
- RISCVCPUMultiExtConfig *prop;
+ const RISCVCPUMultiExtConfig *prop;
/* Enable RVG, RVJ and RVV that are disabled by default */
set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
--
2.41.0
next prev parent reply other threads:[~2023-09-06 9:21 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-06 9:16 [PATCH v2 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 01/19] target/riscv: introduce TCG AccelCPUClass Daniel Henrique Barboza
2023-09-19 9:51 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn() Daniel Henrique Barboza
2023-09-19 9:54 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c Daniel Henrique Barboza
2023-09-19 10:59 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 04/19] target/riscv: move riscv_tcg_ops " Daniel Henrique Barboza
2023-09-19 11:08 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 05/19] target/riscv/cpu.c: add .instance_post_init() Daniel Henrique Barboza
2023-09-11 7:08 ` Andrew Jones
2023-09-19 9:16 ` LIU Zhiwei
2023-09-19 16:07 ` Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 06/19] target/riscv: move 'host' CPU declaration to kvm.c Daniel Henrique Barboza
2023-09-19 11:11 ` LIU Zhiwei
2023-09-06 9:16 ` Daniel Henrique Barboza [this message]
2023-09-19 11:19 ` [PATCH v2 07/19] target/riscv/cpu.c: mark extensions arrays as 'const' LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c Daniel Henrique Barboza
2023-09-19 11:25 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 09/19] target/riscv: make riscv_add_satp_mode_properties() public Daniel Henrique Barboza
2023-09-11 7:09 ` Andrew Jones
2023-09-19 11:26 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 10/19] target/riscv: remove kvm-stub.c Daniel Henrique Barboza
2023-09-06 10:23 ` Philippe Mathieu-Daudé
2023-09-11 7:49 ` Andrew Jones
2023-09-11 9:04 ` Andrew Jones
2023-09-11 12:23 ` Daniel Henrique Barboza
2023-09-12 10:48 ` Daniel Henrique Barboza
2023-09-12 11:15 ` Philippe Mathieu-Daudé
2023-09-12 12:03 ` Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 11/19] target/riscv: introduce KVM AccelCPUClass Daniel Henrique Barboza
2023-09-11 7:52 ` Andrew Jones
2023-09-19 11:37 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 12/19] target/riscv: move KVM only files to kvm subdir Daniel Henrique Barboza
2023-09-19 11:37 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 13/19] target/riscv/kvm: do not use riscv_cpu_add_misa_properties() Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 14/19] target/riscv/cpu.c: export set_misa() Daniel Henrique Barboza
2023-09-06 10:18 ` Philippe Mathieu-Daudé
2023-09-11 7:54 ` Andrew Jones
2023-09-06 9:16 ` [PATCH v2 15/19] target/riscv/tcg: introduce tcg_cpu_instance_init() Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 16/19] target/riscv/cpu.c: make misa_ext_cfgs[] 'const' Daniel Henrique Barboza
2023-09-11 7:56 ` Andrew Jones
2023-09-06 9:16 ` [PATCH v2 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 18/19] target/riscv/cpu.c: export isa_edata_arr[] Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c Daniel Henrique Barboza
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230906091647.1667171-8-dbarboza@ventanamicro.com \
--to=dbarboza@ventanamicro.com \
--cc=ajones@ventanamicro.com \
--cc=alistair.francis@wdc.com \
--cc=bmeng@tinylab.org \
--cc=liweiwei@iscas.ac.cn \
--cc=palmer@rivosinc.com \
--cc=philmd@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.