From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
ajones@ventanamicro.com, philmd@linaro.org,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v2 04/19] target/riscv: move riscv_tcg_ops to tcg-cpu.c
Date: Wed, 6 Sep 2023 06:16:31 -0300 [thread overview]
Message-ID: <20230906091647.1667171-5-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230906091647.1667171-1-dbarboza@ventanamicro.com>
Move the remaining of riscv_tcg_ops now that we have a working realize()
implementation.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/cpu.c | 58 ------------------------------------
target/riscv/cpu.h | 4 ---
target/riscv/tcg/tcg-cpu.c | 60 +++++++++++++++++++++++++++++++++++++-
3 files changed, 59 insertions(+), 63 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e186c026c9..7569955c7e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -838,24 +838,6 @@ static vaddr riscv_cpu_get_pc(CPUState *cs)
return env->pc;
}
-static void riscv_cpu_synchronize_from_tb(CPUState *cs,
- const TranslationBlock *tb)
-{
- if (!(tb_cflags(tb) & CF_PCREL)) {
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
- RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
-
- tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
-
- if (xl == MXL_RV32) {
- env->pc = (int32_t) tb->pc;
- } else {
- env->pc = tb->pc;
- }
- }
-}
-
static bool riscv_cpu_has_work(CPUState *cs)
{
#ifndef CONFIG_USER_ONLY
@@ -871,29 +853,6 @@ static bool riscv_cpu_has_work(CPUState *cs)
#endif
}
-static void riscv_restore_state_to_opc(CPUState *cs,
- const TranslationBlock *tb,
- const uint64_t *data)
-{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
- RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
- target_ulong pc;
-
- if (tb_cflags(tb) & CF_PCREL) {
- pc = (env->pc & TARGET_PAGE_MASK) | data[0];
- } else {
- pc = data[0];
- }
-
- if (xl == MXL_RV32) {
- env->pc = (int32_t)pc;
- } else {
- env->pc = pc;
- }
- env->bins = data[1];
-}
-
static void riscv_cpu_reset_hold(Object *obj)
{
#ifndef CONFIG_USER_ONLY
@@ -1811,23 +1770,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
};
#endif
-const struct TCGCPUOps riscv_tcg_ops = {
- .initialize = riscv_translate_init,
- .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
- .restore_state_to_opc = riscv_restore_state_to_opc,
-
-#ifndef CONFIG_USER_ONLY
- .tlb_fill = riscv_cpu_tlb_fill,
- .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
- .do_interrupt = riscv_cpu_do_interrupt,
- .do_transaction_failed = riscv_cpu_do_transaction_failed,
- .do_unaligned_access = riscv_cpu_do_unaligned_access,
- .debug_excp_handler = riscv_cpu_debug_excp_handler,
- .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
- .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
-#endif /* !CONFIG_USER_ONLY */
-};
-
static bool riscv_cpu_is_dynamic(Object *cpu_obj)
{
return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 721bd0b119..2ac00a0304 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -706,10 +706,6 @@ enum riscv_pmu_event_idx {
RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021,
};
-/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */
-#include "hw/core/tcg-cpu-ops.h"
-extern const struct TCGCPUOps riscv_tcg_ops;
-
/* used by tcg/tcg-cpu.c*/
void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
bool cpu_cfg_ext_is_user_set(uint32_t ext_offset);
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index da18851ed4..8698ce4765 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -26,7 +26,66 @@
#include "qemu/accel.h"
#include "qemu/error-report.h"
#include "hw/core/accel-cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
+#include "tcg/tcg.h"
+static void riscv_cpu_synchronize_from_tb(CPUState *cs,
+ const TranslationBlock *tb)
+{
+ if (!(tb_cflags(tb) & CF_PCREL)) {
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+
+ tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
+
+ if (xl == MXL_RV32) {
+ env->pc = (int32_t) tb->pc;
+ } else {
+ env->pc = tb->pc;
+ }
+ }
+}
+
+static void riscv_restore_state_to_opc(CPUState *cs,
+ const TranslationBlock *tb,
+ const uint64_t *data)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
+ target_ulong pc;
+
+ if (tb_cflags(tb) & CF_PCREL) {
+ pc = (env->pc & TARGET_PAGE_MASK) | data[0];
+ } else {
+ pc = data[0];
+ }
+
+ if (xl == MXL_RV32) {
+ env->pc = (int32_t)pc;
+ } else {
+ env->pc = pc;
+ }
+ env->bins = data[1];
+}
+
+static const struct TCGCPUOps riscv_tcg_ops = {
+ .initialize = riscv_translate_init,
+ .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
+ .restore_state_to_opc = riscv_restore_state_to_opc,
+
+#ifndef CONFIG_USER_ONLY
+ .tlb_fill = riscv_cpu_tlb_fill,
+ .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
+ .do_interrupt = riscv_cpu_do_interrupt,
+ .do_transaction_failed = riscv_cpu_do_transaction_failed,
+ .do_unaligned_access = riscv_cpu_do_unaligned_access,
+ .debug_excp_handler = riscv_cpu_debug_excp_handler,
+ .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
+ .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
+#endif /* !CONFIG_USER_ONLY */
+};
static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
bool value)
@@ -513,7 +572,6 @@ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc)
{
/*
* All cpus use the same set of operations.
- * riscv_tcg_ops is being imported from cpu.c for now.
*/
cc->tcg_ops = &riscv_tcg_ops;
}
--
2.41.0
next prev parent reply other threads:[~2023-09-06 9:23 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-06 9:16 [PATCH v2 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 01/19] target/riscv: introduce TCG AccelCPUClass Daniel Henrique Barboza
2023-09-19 9:51 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn() Daniel Henrique Barboza
2023-09-19 9:54 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c Daniel Henrique Barboza
2023-09-19 10:59 ` LIU Zhiwei
2023-09-06 9:16 ` Daniel Henrique Barboza [this message]
2023-09-19 11:08 ` [PATCH v2 04/19] target/riscv: move riscv_tcg_ops " LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 05/19] target/riscv/cpu.c: add .instance_post_init() Daniel Henrique Barboza
2023-09-11 7:08 ` Andrew Jones
2023-09-19 9:16 ` LIU Zhiwei
2023-09-19 16:07 ` Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 06/19] target/riscv: move 'host' CPU declaration to kvm.c Daniel Henrique Barboza
2023-09-19 11:11 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 07/19] target/riscv/cpu.c: mark extensions arrays as 'const' Daniel Henrique Barboza
2023-09-19 11:19 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c Daniel Henrique Barboza
2023-09-19 11:25 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 09/19] target/riscv: make riscv_add_satp_mode_properties() public Daniel Henrique Barboza
2023-09-11 7:09 ` Andrew Jones
2023-09-19 11:26 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 10/19] target/riscv: remove kvm-stub.c Daniel Henrique Barboza
2023-09-06 10:23 ` Philippe Mathieu-Daudé
2023-09-11 7:49 ` Andrew Jones
2023-09-11 9:04 ` Andrew Jones
2023-09-11 12:23 ` Daniel Henrique Barboza
2023-09-12 10:48 ` Daniel Henrique Barboza
2023-09-12 11:15 ` Philippe Mathieu-Daudé
2023-09-12 12:03 ` Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 11/19] target/riscv: introduce KVM AccelCPUClass Daniel Henrique Barboza
2023-09-11 7:52 ` Andrew Jones
2023-09-19 11:37 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 12/19] target/riscv: move KVM only files to kvm subdir Daniel Henrique Barboza
2023-09-19 11:37 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 13/19] target/riscv/kvm: do not use riscv_cpu_add_misa_properties() Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 14/19] target/riscv/cpu.c: export set_misa() Daniel Henrique Barboza
2023-09-06 10:18 ` Philippe Mathieu-Daudé
2023-09-11 7:54 ` Andrew Jones
2023-09-06 9:16 ` [PATCH v2 15/19] target/riscv/tcg: introduce tcg_cpu_instance_init() Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 16/19] target/riscv/cpu.c: make misa_ext_cfgs[] 'const' Daniel Henrique Barboza
2023-09-11 7:56 ` Andrew Jones
2023-09-06 9:16 ` [PATCH v2 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 18/19] target/riscv/cpu.c: export isa_edata_arr[] Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c Daniel Henrique Barboza
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230906091647.1667171-5-dbarboza@ventanamicro.com \
--to=dbarboza@ventanamicro.com \
--cc=ajones@ventanamicro.com \
--cc=alistair.francis@wdc.com \
--cc=bmeng@tinylab.org \
--cc=liweiwei@iscas.ac.cn \
--cc=palmer@rivosinc.com \
--cc=philmd@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.