From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn, palmer@rivosinc.com,
ajones@ventanamicro.com, philmd@linaro.org
Subject: Re: [PATCH v2 05/19] target/riscv/cpu.c: add .instance_post_init()
Date: Tue, 19 Sep 2023 13:07:37 -0300 [thread overview]
Message-ID: <d19ae0d4-c2eb-aba4-0287-b0e5d943b7d3@ventanamicro.com> (raw)
In-Reply-To: <65e9cd16-da47-05b4-d056-f8f17f109e6f@linux.alibaba.com>
On 9/19/23 06:16, LIU Zhiwei wrote:
>
> On 2023/9/6 17:16, Daniel Henrique Barboza wrote:
>> All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU
>> calls riscv_init_max_cpu_extensions(). Both can be moved to a common
>> instance_post_init() callback, implemented in riscv_cpu_post_init(),
>> called by all CPUs. The call order then becomes:
>>
>> riscv_cpu_init() -> cpu_init() of each CPU -> .instance_post_init()
>>
>> In the near future riscv_cpu_post_init() will call the init() function
>> of the current accelerator, providing a hook for KVM and TCG accel
>> classes to change the init() process of the CPU.
>>
>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> ---
>> target/riscv/cpu.c | 42 ++++++++++++++++++++++++++++++++----------
>> 1 file changed, 32 insertions(+), 10 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 7569955c7e..4c6d595067 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -427,8 +427,6 @@ static void riscv_max_cpu_init(Object *obj)
>> mlx = MXL_RV32;
>> #endif
>> set_misa(env, mlx, 0);
>> - riscv_cpu_add_user_properties(obj);
>> - riscv_init_max_cpu_extensions(obj);
>> env->priv_ver = PRIV_VERSION_LATEST;
>> #ifndef CONFIG_USER_ONLY
>> set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
>> @@ -442,7 +440,6 @@ static void rv64_base_cpu_init(Object *obj)
>> CPURISCVState *env = &RISCV_CPU(obj)->env;
>> /* We set this in the realise function */
>> set_misa(env, MXL_RV64, 0);
>> - riscv_cpu_add_user_properties(obj);
>> /* Set latest version of privileged specification */
>> env->priv_ver = PRIV_VERSION_LATEST;
>> #ifndef CONFIG_USER_ONLY
>> @@ -566,7 +563,6 @@ static void rv128_base_cpu_init(Object *obj)
>> CPURISCVState *env = &RISCV_CPU(obj)->env;
>> /* We set this in the realise function */
>> set_misa(env, MXL_RV128, 0);
>> - riscv_cpu_add_user_properties(obj);
>> /* Set latest version of privileged specification */
>> env->priv_ver = PRIV_VERSION_LATEST;
>> #ifndef CONFIG_USER_ONLY
>> @@ -579,7 +575,6 @@ static void rv32_base_cpu_init(Object *obj)
>> CPURISCVState *env = &RISCV_CPU(obj)->env;
>> /* We set this in the realise function */
>> set_misa(env, MXL_RV32, 0);
>> - riscv_cpu_add_user_properties(obj);
>> /* Set latest version of privileged specification */
>> env->priv_ver = PRIV_VERSION_LATEST;
>> #ifndef CONFIG_USER_ONLY
> I think we should also remove riscv_cpu_add_user_properties from host cpu init.
Line removed in v3. Thanks,
Daniel
>> @@ -1215,6 +1210,37 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
>> }
>> #endif /* CONFIG_USER_ONLY */
>> +static bool riscv_cpu_is_dynamic(Object *cpu_obj)
>> +{
>> + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
>> +}
>> +
>> +static bool riscv_cpu_has_max_extensions(Object *cpu_obj)
>> +{
>> + return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL;
>> +}
>> +
>> +static bool riscv_cpu_has_user_properties(Object *cpu_obj)
>> +{
>> + if (kvm_enabled() &&
>> + object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) {
>> + return true;
>> + }
>> +
>> + return riscv_cpu_is_dynamic(cpu_obj);
>> +}
>> +
>> +static void riscv_cpu_post_init(Object *obj)
>> +{
>> + if (riscv_cpu_has_user_properties(obj)) {
>> + riscv_cpu_add_user_properties(obj);
>
> Otherwise, we will enter here for host cpu.
>
> Thanks,
> Zhiwei
>
>> + }
>> +
>> + if (riscv_cpu_has_max_extensions(obj)) {
>> + riscv_init_max_cpu_extensions(obj);
>> + }
>> +}
>> +
>> static void riscv_cpu_init(Object *obj)
>> {
>> RISCVCPU *cpu = RISCV_CPU(obj);
>> @@ -1770,11 +1796,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
>> };
>> #endif
>> -static bool riscv_cpu_is_dynamic(Object *cpu_obj)
>> -{
>> - return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
>> -}
>> -
>> static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name,
>> void *opaque, Error **errp)
>> {
>> @@ -2011,6 +2032,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>> .instance_size = sizeof(RISCVCPU),
>> .instance_align = __alignof__(RISCVCPU),
>> .instance_init = riscv_cpu_init,
>> + .instance_post_init = riscv_cpu_post_init,
>> .abstract = true,
>> .class_size = sizeof(RISCVCPUClass),
>> .class_init = riscv_cpu_class_init,
next prev parent reply other threads:[~2023-09-19 16:08 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-06 9:16 [PATCH v2 00/19] riscv: split TCG/KVM accelerators from cpu.c Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 01/19] target/riscv: introduce TCG AccelCPUClass Daniel Henrique Barboza
2023-09-19 9:51 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn() Daniel Henrique Barboza
2023-09-19 9:54 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c Daniel Henrique Barboza
2023-09-19 10:59 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 04/19] target/riscv: move riscv_tcg_ops " Daniel Henrique Barboza
2023-09-19 11:08 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 05/19] target/riscv/cpu.c: add .instance_post_init() Daniel Henrique Barboza
2023-09-11 7:08 ` Andrew Jones
2023-09-19 9:16 ` LIU Zhiwei
2023-09-19 16:07 ` Daniel Henrique Barboza [this message]
2023-09-06 9:16 ` [PATCH v2 06/19] target/riscv: move 'host' CPU declaration to kvm.c Daniel Henrique Barboza
2023-09-19 11:11 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 07/19] target/riscv/cpu.c: mark extensions arrays as 'const' Daniel Henrique Barboza
2023-09-19 11:19 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c Daniel Henrique Barboza
2023-09-19 11:25 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 09/19] target/riscv: make riscv_add_satp_mode_properties() public Daniel Henrique Barboza
2023-09-11 7:09 ` Andrew Jones
2023-09-19 11:26 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 10/19] target/riscv: remove kvm-stub.c Daniel Henrique Barboza
2023-09-06 10:23 ` Philippe Mathieu-Daudé
2023-09-11 7:49 ` Andrew Jones
2023-09-11 9:04 ` Andrew Jones
2023-09-11 12:23 ` Daniel Henrique Barboza
2023-09-12 10:48 ` Daniel Henrique Barboza
2023-09-12 11:15 ` Philippe Mathieu-Daudé
2023-09-12 12:03 ` Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 11/19] target/riscv: introduce KVM AccelCPUClass Daniel Henrique Barboza
2023-09-11 7:52 ` Andrew Jones
2023-09-19 11:37 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 12/19] target/riscv: move KVM only files to kvm subdir Daniel Henrique Barboza
2023-09-19 11:37 ` LIU Zhiwei
2023-09-06 9:16 ` [PATCH v2 13/19] target/riscv/kvm: do not use riscv_cpu_add_misa_properties() Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 14/19] target/riscv/cpu.c: export set_misa() Daniel Henrique Barboza
2023-09-06 10:18 ` Philippe Mathieu-Daudé
2023-09-11 7:54 ` Andrew Jones
2023-09-06 9:16 ` [PATCH v2 15/19] target/riscv/tcg: introduce tcg_cpu_instance_init() Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 16/19] target/riscv/cpu.c: make misa_ext_cfgs[] 'const' Daniel Henrique Barboza
2023-09-11 7:56 ` Andrew Jones
2023-09-06 9:16 ` [PATCH v2 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 18/19] target/riscv/cpu.c: export isa_edata_arr[] Daniel Henrique Barboza
2023-09-06 9:16 ` [PATCH v2 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c Daniel Henrique Barboza
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