[PATCH V2 0/3] riscv: Add Zicbop & prefetchw support

From: guoren@kernel.org
To: paul.walmsley@sifive.com, palmer@dabbelt.com, guoren@kernel.org,
	panqinglin2020@iscas.ac.cn, bjorn@rivosinc.com,
	conor.dooley@microchip.com, leobras@redhat.com,
	peterz@infradead.org, keescook@chromium.org,
	wuwei2016@iscas.ac.cn, xiaoguang.xing@sophgo.com,
	chao.wei@sophgo.com, unicorn_wang@outlook.com, uwu@icenowy.me,
	jszhang@kernel.org, wefu@redhat.com, atishp@atishpatra.org,
	ajones@ventanamicro.com
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Guo Ren <guoren@linux.alibaba.com>
Subject: [PATCH V2 0/3] riscv: Add Zicbop & prefetchw support
Date: Sun, 31 Dec 2023 03:29:50 -0500	[thread overview]
Message-ID: <20231231082955.16516-1-guoren@kernel.org> (raw)

From: Guo Ren <guoren@linux.alibaba.com>

This patch series adds Zicbop support and then enables the Linux
prefetchw feature. It's based on v6.7-rc7.

PATCH[1] - Add Zicbop support
PATCH[2] - Add prefetchw support
PATCH[3] - Enhance xchg_small

Changelog:
V2:
 - Separate from the qspinlock series
 - Optimize coding convention with last review advice
 - Add DEFINE_INSN_S type in insn-def.h
 - Add CBO_PREFETCH_I/R/W

V1:
https://lore.kernel.org/linux-riscv/20230910082911.3378782-4-guoren@kernel.org/

Guo Ren (3):
  riscv: Add Zicbop instruction definitions & cpufeature
  riscv: Add ARCH_HAS_PRETCHW support with Zibop
  riscv: xchg: Prefetch the destination word for sc.w

 arch/riscv/Kconfig                 | 15 ++++++++
 arch/riscv/include/asm/cmpxchg.h   |  4 +-
 arch/riscv/include/asm/hwcap.h     |  1 +
 arch/riscv/include/asm/insn-def.h  | 60 ++++++++++++++++++++++++++++++
 arch/riscv/include/asm/processor.h | 16 ++++++++
 arch/riscv/kernel/cpufeature.c     |  1 +
 6 files changed, 96 insertions(+), 1 deletion(-)

-- 
2.40.1

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