Re: [PATCH V2 1/3] riscv: Add Zicbop instruction definitions & cpufeature

From: Andrew Jones <ajones@ventanamicro.com>
To: guoren@kernel.org
Cc: wefu@redhat.com, keescook@chromium.org, peterz@infradead.org,
	unicorn_wang@outlook.com, atishp@atishpatra.org,
	chao.wei@sophgo.com, bjorn@rivosinc.com,
	linux-kernel@vger.kernel.org, xiaoguang.xing@sophgo.com,
	conor.dooley@microchip.com, leobras@redhat.com,
	palmer@dabbelt.com, jszhang@kernel.org, paul.walmsley@sifive.com,
	Guo Ren <guoren@linux.alibaba.com>,
	panqinglin2020@iscas.ac.cn, linux-riscv@lists.infradead.org,
	wuwei2016@iscas.ac.cn
Subject: Re: [PATCH V2 1/3] riscv: Add Zicbop instruction definitions & cpufeature
Date: Wed, 3 Jan 2024 20:48:12 +0100	[thread overview]
Message-ID: <20240103-4f92e1f7290975300ecc64ce@orel> (raw)
In-Reply-To: <20231231082955.16516-2-guoren@kernel.org>

On Sun, Dec 31, 2023 at 03:29:51AM -0500, guoren@kernel.org wrote:
...
> +#define CBO_PREFETCH_I(base, offset)				\
> +	INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(0),		\
> +	       SIMM12(offset), RS1(base))
> +
> +#define CBO_PREFETCH_R(base, offset)				\
> +	INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(1),		\
> +	       SIMM12(offset), RS1(base))
> +
> +#define CBO_PREFETCH_W(base, offset)				\
> +	INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(3),		\
> +	       SIMM12(offset), RS1(base))

These should just be named

 PREFETCH_I
 PREFETCH_R
 PREFETCH_W

without the CBO_ prefix. The other CMO instructions we've added have the
CBO_ prefix because their actual instruction names are e.g. cbo.zero,
but the prefix instructions are not named that way.

Thanks,
drew

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