Re: [PATCH V2 2/3] riscv: Add ARCH_HAS_PRETCHW support with Zibop

From: Andrew Jones <ajones@ventanamicro.com>
To: guoren@kernel.org
Cc: wefu@redhat.com, keescook@chromium.org, peterz@infradead.org,
	unicorn_wang@outlook.com, atishp@atishpatra.org,
	chao.wei@sophgo.com, bjorn@rivosinc.com,
	linux-kernel@vger.kernel.org, xiaoguang.xing@sophgo.com,
	conor.dooley@microchip.com, leobras@redhat.com,
	palmer@dabbelt.com, jszhang@kernel.org, paul.walmsley@sifive.com,
	Guo Ren <guoren@linux.alibaba.com>,
	panqinglin2020@iscas.ac.cn, linux-riscv@lists.infradead.org,
	wuwei2016@iscas.ac.cn
Subject: Re: [PATCH V2 2/3] riscv: Add ARCH_HAS_PRETCHW support with Zibop
Date: Tue, 2 Jan 2024 11:45:08 +0100	[thread overview]
Message-ID: <20240102-7e62facbd8322db4dee4b0dd@orel> (raw)
In-Reply-To: <20231231082955.16516-3-guoren@kernel.org>

s/Zibop/Zicbop/ <<<$SUBJECT

On Sun, Dec 31, 2023 at 03:29:52AM -0500, guoren@kernel.org wrote:
> From: Guo Ren <guoren@linux.alibaba.com>
> 
> Enable Linux prefetchw primitive with Zibop cpufeature, which preloads

Also s/Zibop/Zicbop/ here

> cache line into L1 cache for the next write operation.
> 
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@kernel.org>
> ---
>  arch/riscv/include/asm/processor.h | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
> index f19f861cda54..8d3a2ab37678 100644
> --- a/arch/riscv/include/asm/processor.h
> +++ b/arch/riscv/include/asm/processor.h
> @@ -13,6 +13,9 @@
>  #include <vdso/processor.h>
>  
>  #include <asm/ptrace.h>
> +#include <asm/insn-def.h>
> +#include <asm/alternative-macros.h>
> +#include <asm/hwcap.h>
>  
>  #ifdef CONFIG_64BIT
>  #define DEFAULT_MAP_WINDOW	(UL(1) << (MMAP_VA_BITS - 1))
> @@ -106,6 +109,19 @@ static inline void arch_thread_struct_whitelist(unsigned long *offset,
>  #define KSTK_EIP(tsk)		(task_pt_regs(tsk)->epc)
>  #define KSTK_ESP(tsk)		(task_pt_regs(tsk)->sp)
>  
> +#ifdef CONFIG_RISCV_ISA_ZICBOP
> +#define ARCH_HAS_PREFETCHW
> +
> +#define PREFETCHW_ASM(x)						\
> +	ALTERNATIVE(__nops(1), CBO_PREFETCH_W(x, 0), 0,			\
> +		    RISCV_ISA_EXT_ZICBOP, CONFIG_RISCV_ISA_ZICBOP)
> +
> +
> +static inline void prefetchw(const void *x)
> +{
> +	__asm__ __volatile__(PREFETCHW_ASM(%0) : : "r" (x) : "memory");
> +}

Shouldn't we create an interface which exposes the offset input of
the instruction, allowing a sequence of calls to be unrolled? But
I guess that could be put off until there's a need for it.

> +#endif /* CONFIG_RISCV_ISA_ZICBOP */
>  
>  /* Do necessary setup to start up a newly executed thread. */
>  extern void start_thread(struct pt_regs *regs,
> -- 
> 2.40.1
> 

Thanks,
drew

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