Re: [PATCH V2 1/3] riscv: Add Zicbop instruction definitions & cpufeature

From: Leonardo Bras <leobras@redhat.com>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: wefu@redhat.com, keescook@chromium.org, atishp@atishpatra.org,
	peterz@infradead.org, unicorn_wang@outlook.com,
	paul.walmsley@sifive.com, chao.wei@sophgo.com,
	bjorn@rivosinc.com, linux-kernel@vger.kernel.org,
	xiaoguang.xing@sophgo.com, conor.dooley@microchip.com,
	Leonardo Bras <leobras@redhat.com>,
	palmer@dabbelt.com, jszhang@kernel.org,
	panqinglin2020@iscas.ac.cn, Guo Ren <guoren@linux.alibaba.com>,
	guoren@kernel.org, linux-riscv@lists.infradead.org,
	wuwei2016@iscas.ac.cn
Subject: Re: [PATCH V2 1/3] riscv: Add Zicbop instruction definitions & cpufeature
Date: Wed,  3 Jan 2024 17:34:29 -0300	[thread overview]
Message-ID: <ZZXE1WoXaAdkrH8A@LeoBras> (raw)
In-Reply-To: <20240103-4f92e1f7290975300ecc64ce@orel>

On Wed, Jan 03, 2024 at 08:48:12PM +0100, Andrew Jones wrote:
> On Sun, Dec 31, 2023 at 03:29:51AM -0500, guoren@kernel.org wrote:
> ...
> > +#define CBO_PREFETCH_I(base, offset)				\
> > +	INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(0),		\
> > +	       SIMM12(offset), RS1(base))
> > +
> > +#define CBO_PREFETCH_R(base, offset)				\
> > +	INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(1),		\
> > +	       SIMM12(offset), RS1(base))
> > +
> > +#define CBO_PREFETCH_W(base, offset)				\
> > +	INSN_S(OPCODE_OP_IMM, FUNC3(6), __RS2(3),		\
> > +	       SIMM12(offset), RS1(base))
> 
> These should just be named
> 
>  PREFETCH_I
>  PREFETCH_R
>  PREFETCH_W
> 
> without the CBO_ prefix. The other CMO instructions we've added have the
> CBO_ prefix because their actual instruction names are e.g. cbo.zero,
> but the prefix instructions are not named that way.
> 
> Thanks,
> drew
> 

Sure, that's ok this way :)


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