From: Simon Horman <horms@kernel.org>
To: Karol Kolacinski <karol.kolacinski@intel.com>
Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
intel-wired-lan@lists.osuosl.org, przemyslaw.kitszel@intel.com
Subject: Re: [Intel-wired-lan] [PATCH iwl-next 3/7] ice: Align E810T GPIO to other products
Date: Mon, 1 Jul 2024 14:25:51 +0100 [thread overview]
Message-ID: <20240701132551.GA17134@kernel.org> (raw)
In-Reply-To: <20240627151127.284884-12-karol.kolacinski@intel.com>
On Thu, Jun 27, 2024 at 05:09:27PM +0200, Karol Kolacinski wrote:
> Instead of having separate PTP GPIO implementation for E810T, use
> existing one from all other products.
>
> Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
...
> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c
...
> @@ -72,242 +78,99 @@ static int ice_ptp_find_pin_idx(struct ice_pf *pf, enum ptp_pin_function func,
>
> return -1;
> }
> -
nit: I think this blank line should stay
> /**
> - * ice_get_sma_config_e810t
> - * @hw: pointer to the hw struct
> - * @ptp_pins: pointer to the ptp_pin_desc struture
> - *
> - * Read the configuration of the SMA control logic and put it into the
> - * ptp_pin_desc structure
> + * ice_ptp_update_sma_data - update SMA pins data according to pins setup
> + * @pf: Board private structure
> + * @sma_pins: parsed SMA pins status
> + * @data: SMA data to update
> */
> -static int
> -ice_get_sma_config_e810t(struct ice_hw *hw, struct ptp_pin_desc *ptp_pins)
> +static void ice_ptp_update_sma_data(struct ice_pf *pf, uint sma_pins[],
> + u8 *data)
...
WARNING: multiple messages have this Message-ID (diff)
From: Simon Horman <horms@kernel.org>
To: Karol Kolacinski <karol.kolacinski@intel.com>
Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org,
anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Subject: Re: [PATCH iwl-next 3/7] ice: Align E810T GPIO to other products
Date: Mon, 1 Jul 2024 14:25:51 +0100 [thread overview]
Message-ID: <20240701132551.GA17134@kernel.org> (raw)
In-Reply-To: <20240627151127.284884-12-karol.kolacinski@intel.com>
On Thu, Jun 27, 2024 at 05:09:27PM +0200, Karol Kolacinski wrote:
> Instead of having separate PTP GPIO implementation for E810T, use
> existing one from all other products.
>
> Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
...
> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c
...
> @@ -72,242 +78,99 @@ static int ice_ptp_find_pin_idx(struct ice_pf *pf, enum ptp_pin_function func,
>
> return -1;
> }
> -
nit: I think this blank line should stay
> /**
> - * ice_get_sma_config_e810t
> - * @hw: pointer to the hw struct
> - * @ptp_pins: pointer to the ptp_pin_desc struture
> - *
> - * Read the configuration of the SMA control logic and put it into the
> - * ptp_pin_desc structure
> + * ice_ptp_update_sma_data - update SMA pins data according to pins setup
> + * @pf: Board private structure
> + * @sma_pins: parsed SMA pins status
> + * @data: SMA data to update
> */
> -static int
> -ice_get_sma_config_e810t(struct ice_hw *hw, struct ptp_pin_desc *ptp_pins)
> +static void ice_ptp_update_sma_data(struct ice_pf *pf, uint sma_pins[],
> + u8 *data)
...
next prev parent reply other threads:[~2024-07-01 13:26 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-27 15:09 [Intel-wired-lan] [PATCH iwl-next 0/7] ice: Cleanup and refactor PTP pin handling Karol Kolacinski
2024-06-27 15:09 ` Karol Kolacinski
2024-06-27 15:09 ` [Intel-wired-lan] [PATCH iwl-next 1/7] ice: Implement ice_ptp_pin_desc Karol Kolacinski
2024-06-27 15:09 ` Karol Kolacinski
2024-07-01 13:23 ` [Intel-wired-lan] " Simon Horman
2024-07-01 13:23 ` Simon Horman
2024-06-27 15:09 ` [Intel-wired-lan] [PATCH iwl-next 2/7] ice: Add SDPs support for E825C Karol Kolacinski
2024-06-27 15:09 ` Karol Kolacinski
2024-07-01 13:25 ` [Intel-wired-lan] " Simon Horman
2024-07-01 13:25 ` Simon Horman
2024-06-27 15:09 ` [Intel-wired-lan] [PATCH iwl-next 3/7] ice: Align E810T GPIO to other products Karol Kolacinski
2024-06-27 15:09 ` Karol Kolacinski
2024-07-01 13:25 ` Simon Horman [this message]
2024-07-01 13:25 ` Simon Horman
2024-06-27 15:09 ` [Intel-wired-lan] [PATCH iwl-next 4/7] ice: Cache perout/extts requests and check flags Karol Kolacinski
2024-06-27 15:09 ` Karol Kolacinski
2024-07-01 13:26 ` [Intel-wired-lan] " Simon Horman
2024-07-01 13:26 ` Simon Horman
2024-06-27 15:09 ` [Intel-wired-lan] [PATCH iwl-next 5/7] ice: Disable shared pin on E810 on setfunc Karol Kolacinski
2024-06-27 15:09 ` Karol Kolacinski
2024-07-01 13:27 ` [Intel-wired-lan] " Simon Horman
2024-07-01 13:27 ` Simon Horman
2024-06-27 15:09 ` [Intel-wired-lan] [PATCH iwl-next 6/7] ice: Read SDP section from NVM for pin definitions Karol Kolacinski
2024-06-27 15:09 ` Karol Kolacinski
2024-06-27 15:09 ` [Intel-wired-lan] [PATCH iwl-next 7/7] ice: Enable 1PPS out from CGU for E825C products Karol Kolacinski
2024-06-27 15:09 ` Karol Kolacinski
2024-06-27 15:37 ` [Intel-wired-lan] " Paul Menzel
2024-06-27 15:37 ` Paul Menzel
2024-07-01 13:49 ` Kolacinski, Karol
2024-07-01 13:49 ` Kolacinski, Karol
2024-07-01 13:27 ` Simon Horman
2024-07-01 13:27 ` Simon Horman
2024-07-01 15:08 ` [Intel-wired-lan] " Przemek Kitszel
2024-07-01 15:08 ` Przemek Kitszel
2024-07-02 10:56 ` [Intel-wired-lan] " Simon Horman
2024-07-02 10:56 ` Simon Horman
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