From: Deepak Gupta <debug@rivosinc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: richard.henderson@linaro.org, pbonzini@redhat.com,
palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu,
bmeng.cn@gmail.com, liwei1518@gmail.com,
dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com,
Deepak Gupta <debug@rivosinc.com>
Subject: [PATCH v3 01/20] accel/tcg: restrict assert on icount_enabled to qemu-system
Date: Tue, 6 Aug 2024 17:06:32 -0700 [thread overview]
Message-ID: <20240807000652.1417776-2-debug@rivosinc.com> (raw)
In-Reply-To: <20240807000652.1417776-1-debug@rivosinc.com>
commit 16ad9788 [1] restricted icount to qemu-system only. Although
assert in `cpu_loop_exec_tb` is on `icount_enabled()` which is 0 when
its qemu-user and debug build starts asserting.
Move assert for qemu-system.
[1] - https://lists.gnu.org/archive/html/qemu-riscv/2024-01/msg00608.html
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
accel/tcg/cpu-exec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 245fd6327d..8cc2a6104f 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -927,9 +927,9 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb,
return;
}
+#ifndef CONFIG_USER_ONLY
/* Instruction counter expired. */
assert(icount_enabled());
-#ifndef CONFIG_USER_ONLY
/* Ensure global icount has gone forward */
icount_update(cpu);
/* Refill decrementer and continue execution. */
--
2.44.0
next prev parent reply other threads:[~2024-08-07 0:08 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-07 0:06 [PATCH v3 00/20] riscv support for control flow integrity extensions Deepak Gupta
2024-08-07 0:06 ` Deepak Gupta [this message]
2024-08-07 0:48 ` [PATCH v3 01/20] accel/tcg: restrict assert on icount_enabled to qemu-system Richard Henderson
2024-08-07 18:45 ` Deepak Gupta
2024-08-12 17:41 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 02/20] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 03/20] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-07 0:56 ` Richard Henderson
2024-08-07 18:46 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 04/20] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-07 1:06 ` Richard Henderson
2024-08-07 20:11 ` Deepak Gupta
2024-08-07 22:40 ` Richard Henderson
2024-08-07 22:58 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 05/20] target/riscv: additional code information for sw check Deepak Gupta
2024-08-07 1:11 ` Richard Henderson
2024-08-07 0:06 ` [PATCH v3 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-07 1:23 ` Richard Henderson
2024-08-07 20:15 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 07/20] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-07 2:01 ` Richard Henderson
2024-08-07 2:04 ` Richard Henderson
2024-08-07 0:06 ` [PATCH v3 08/20] disas/riscv: enabled `lpad` disassembly Deepak Gupta
2024-08-07 2:06 ` Richard Henderson
2024-08-07 0:06 ` [PATCH v3 09/20] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 10/20] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-07 2:11 ` Richard Henderson
2024-08-07 2:12 ` Richard Henderson
2024-08-07 20:21 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 11/20] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-07 2:13 ` Richard Henderson
2024-08-07 0:06 ` [PATCH v3 12/20] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-07 2:39 ` Richard Henderson
2024-08-07 2:56 ` Richard Henderson
2024-08-07 21:25 ` Deepak Gupta
2024-08-07 20:35 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 13/20] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-07 2:40 ` Richard Henderson
2024-08-07 0:06 ` [PATCH v3 14/20] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-07 3:19 ` Richard Henderson
2024-08-09 18:55 ` Deepak Gupta
2024-08-11 22:23 ` Richard Henderson
2024-08-07 0:06 ` [PATCH v3 15/20] target/riscv: shadow stack mmu index for shadow stack instructions Deepak Gupta
2024-08-07 2:43 ` Richard Henderson
2024-08-07 21:23 ` Deepak Gupta
2024-08-07 22:57 ` Richard Henderson
2024-08-07 23:13 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 16/20] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-07 3:24 ` Richard Henderson
2024-08-07 0:06 ` [PATCH v3 17/20] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 18/20] target/riscv: add trace-hooks for each case of sw-check exception Deepak Gupta
2024-08-07 3:27 ` Richard Henderson
2024-08-07 20:52 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 19/20] linux-user: permit RISC-V CFI dynamic entry in VDSO Deepak Gupta
2024-08-07 3:36 ` Richard Henderson
2024-08-07 20:53 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 20/20] linux-user: Add RISC-V zicfilp support " Deepak Gupta
2024-08-07 3:41 ` Richard Henderson
2024-08-07 21:00 ` Deepak Gupta
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240807000652.1417776-2-debug@rivosinc.com \
--to=debug@rivosinc.com \
--cc=Alistair.Francis@wdc.com \
--cc=bmeng.cn@gmail.com \
--cc=dbarboza@ventanamicro.com \
--cc=laurent@vivier.eu \
--cc=liwei1518@gmail.com \
--cc=palmer@dabbelt.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.