* [Intel-wired-lan] [PATCH iwl-next v1 0/3] E825C PTP cleanup @ 2025-02-06 8:36 ` Grzegorz Nitka 0 siblings, 0 replies; 20+ messages in thread From: Grzegorz Nitka @ 2025-02-06 8:36 UTC (permalink / raw) To: intel-wired-lan; +Cc: netdev, anthony.l.nguyen, przemyslaw.kitszel This patch series simplifies PTP code related to E825C products by simplifying PHY register info definition. Cleanup the code by removing unused register definitions. Also, add sync delay compensation between PHC and PHY for E825C. Karol Kolacinski (3): ice: Add sync delay for E825C ice: Refactor E825C PHY registers info struct ice: E825C PHY register cleanup .../net/ethernet/intel/ice/ice_ptp_consts.h | 75 ++++--------------- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 20 ++--- drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 36 ++++----- 3 files changed, 43 insertions(+), 88 deletions(-) base-commit: 70bdf16570c2c207a562e996833ff196a4bd7029 -- 2.39.3 ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH iwl-next v1 0/3] E825C PTP cleanup @ 2025-02-06 8:36 ` Grzegorz Nitka 0 siblings, 0 replies; 20+ messages in thread From: Grzegorz Nitka @ 2025-02-06 8:36 UTC (permalink / raw) To: intel-wired-lan Cc: netdev, anthony.l.nguyen, przemyslaw.kitszel, Grzegorz Nitka This patch series simplifies PTP code related to E825C products by simplifying PHY register info definition. Cleanup the code by removing unused register definitions. Also, add sync delay compensation between PHC and PHY for E825C. Karol Kolacinski (3): ice: Add sync delay for E825C ice: Refactor E825C PHY registers info struct ice: E825C PHY register cleanup .../net/ethernet/intel/ice/ice_ptp_consts.h | 75 ++++--------------- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 20 ++--- drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 36 ++++----- 3 files changed, 43 insertions(+), 88 deletions(-) base-commit: 70bdf16570c2c207a562e996833ff196a4bd7029 -- 2.39.3 ^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-wired-lan] [PATCH iwl-next v1 1/3] ice: Add sync delay for E825C 2025-02-06 8:36 ` Grzegorz Nitka @ 2025-02-06 8:36 ` Grzegorz Nitka -1 siblings, 0 replies; 20+ messages in thread From: Grzegorz Nitka @ 2025-02-06 8:36 UTC (permalink / raw) To: intel-wired-lan Cc: netdev, Karol Kolacinski, anthony.l.nguyen, przemyslaw.kitszel From: Karol Kolacinski <karol.kolacinski@intel.com> Implement setting GLTSYN_SYNC_DLAY for E825C products. This is the execution delay compensation of SYNC command between PHC and PHY. Also, refactor the code by changing ice_ptp_init_phc_eth56g function name to ice_ptp_init_phc_e825, to be consistent with the naming pattern for other devices. Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> --- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 14 +++++++------- drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 3 +++ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 3e824f7b30c0..c3dea6d61de4 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -2650,18 +2650,18 @@ static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable) } /** - * ice_ptp_init_phc_eth56g - Perform E82X specific PHC initialization + * ice_ptp_init_phc_e825 - Perform E825 specific PHC initialization * @hw: pointer to HW struct * - * Perform PHC initialization steps specific to E82X devices. + * Perform E825-specific PTP hardware clock initialization steps. * - * Return: - * * %0 - success - * * %other - failed to initialize CGU + * Return: 0 on success, negative error code otherwise. */ -static int ice_ptp_init_phc_eth56g(struct ice_hw *hw) +static int ice_ptp_init_phc_e825(struct ice_hw *hw) { ice_sb_access_ena_eth56g(hw, true); + ice_ptp_cfg_sync_delay(hw, ICE_E825_SYNC_DELAY); + /* Initialize the Clock Generation Unit */ return ice_init_cgu_e82x(hw); } @@ -6123,7 +6123,7 @@ int ice_ptp_init_phc(struct ice_hw *hw) case ICE_MAC_GENERIC: return ice_ptp_init_phc_e82x(hw); case ICE_MAC_GENERIC_3K_E825: - return ice_ptp_init_phc_eth56g(hw); + return ice_ptp_init_phc_e825(hw); default: return -EOPNOTSUPP; } diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index 8442d1d60351..10295fa9a383 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -324,7 +324,10 @@ extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD]; */ #define ICE_E810_PLL_FREQ 812500000 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL + +/* PHC to PHY synchronization delay definitions */ #define ICE_E810_E830_SYNC_DELAY 0 +#define ICE_E825_SYNC_DELAY 6 /* Device agnostic functions */ u8 ice_get_ptp_src_clock_index(struct ice_hw *hw); -- 2.39.3 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH iwl-next v1 1/3] ice: Add sync delay for E825C @ 2025-02-06 8:36 ` Grzegorz Nitka 0 siblings, 0 replies; 20+ messages in thread From: Grzegorz Nitka @ 2025-02-06 8:36 UTC (permalink / raw) To: intel-wired-lan Cc: netdev, anthony.l.nguyen, przemyslaw.kitszel, Karol Kolacinski, Grzegorz Nitka From: Karol Kolacinski <karol.kolacinski@intel.com> Implement setting GLTSYN_SYNC_DLAY for E825C products. This is the execution delay compensation of SYNC command between PHC and PHY. Also, refactor the code by changing ice_ptp_init_phc_eth56g function name to ice_ptp_init_phc_e825, to be consistent with the naming pattern for other devices. Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> --- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 14 +++++++------- drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 3 +++ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 3e824f7b30c0..c3dea6d61de4 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -2650,18 +2650,18 @@ static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable) } /** - * ice_ptp_init_phc_eth56g - Perform E82X specific PHC initialization + * ice_ptp_init_phc_e825 - Perform E825 specific PHC initialization * @hw: pointer to HW struct * - * Perform PHC initialization steps specific to E82X devices. + * Perform E825-specific PTP hardware clock initialization steps. * - * Return: - * * %0 - success - * * %other - failed to initialize CGU + * Return: 0 on success, negative error code otherwise. */ -static int ice_ptp_init_phc_eth56g(struct ice_hw *hw) +static int ice_ptp_init_phc_e825(struct ice_hw *hw) { ice_sb_access_ena_eth56g(hw, true); + ice_ptp_cfg_sync_delay(hw, ICE_E825_SYNC_DELAY); + /* Initialize the Clock Generation Unit */ return ice_init_cgu_e82x(hw); } @@ -6123,7 +6123,7 @@ int ice_ptp_init_phc(struct ice_hw *hw) case ICE_MAC_GENERIC: return ice_ptp_init_phc_e82x(hw); case ICE_MAC_GENERIC_3K_E825: - return ice_ptp_init_phc_eth56g(hw); + return ice_ptp_init_phc_e825(hw); default: return -EOPNOTSUPP; } diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index 8442d1d60351..10295fa9a383 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -324,7 +324,10 @@ extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD]; */ #define ICE_E810_PLL_FREQ 812500000 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL + +/* PHC to PHY synchronization delay definitions */ #define ICE_E810_E830_SYNC_DELAY 0 +#define ICE_E825_SYNC_DELAY 6 /* Device agnostic functions */ u8 ice_get_ptp_src_clock_index(struct ice_hw *hw); -- 2.39.3 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [Intel-wired-lan] [PATCH iwl-next v1 1/3] ice: Add sync delay for E825C 2025-02-06 8:36 ` Grzegorz Nitka @ 2025-02-07 10:03 ` Simon Horman -1 siblings, 0 replies; 20+ messages in thread From: Simon Horman @ 2025-02-07 10:03 UTC (permalink / raw) To: Grzegorz Nitka Cc: intel-wired-lan, netdev, anthony.l.nguyen, przemyslaw.kitszel, Karol Kolacinski On Thu, Feb 06, 2025 at 09:36:53AM +0100, Grzegorz Nitka wrote: > From: Karol Kolacinski <karol.kolacinski@intel.com> > > Implement setting GLTSYN_SYNC_DLAY for E825C products. > This is the execution delay compensation of SYNC command between > PHC and PHY. > Also, refactor the code by changing ice_ptp_init_phc_eth56g function > name to ice_ptp_init_phc_e825, to be consistent with the naming pattern > for other devices. Adding support for GLTSYN_SYNC_DLAY and the refactor seem to be two distinct changes, albeit touching common code. I think it would be slightly better to split this into two patches. > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> > Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> ... ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH iwl-next v1 1/3] ice: Add sync delay for E825C @ 2025-02-07 10:03 ` Simon Horman 0 siblings, 0 replies; 20+ messages in thread From: Simon Horman @ 2025-02-07 10:03 UTC (permalink / raw) To: Grzegorz Nitka Cc: intel-wired-lan, netdev, anthony.l.nguyen, przemyslaw.kitszel, Karol Kolacinski On Thu, Feb 06, 2025 at 09:36:53AM +0100, Grzegorz Nitka wrote: > From: Karol Kolacinski <karol.kolacinski@intel.com> > > Implement setting GLTSYN_SYNC_DLAY for E825C products. > This is the execution delay compensation of SYNC command between > PHC and PHY. > Also, refactor the code by changing ice_ptp_init_phc_eth56g function > name to ice_ptp_init_phc_e825, to be consistent with the naming pattern > for other devices. Adding support for GLTSYN_SYNC_DLAY and the refactor seem to be two distinct changes, albeit touching common code. I think it would be slightly better to split this into two patches. > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> > Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> ... ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-wired-lan] [PATCH iwl-next v1 1/3] ice: Add sync delay for E825C 2025-02-07 10:03 ` Simon Horman @ 2025-02-10 10:54 ` Nitka, Grzegorz -1 siblings, 0 replies; 20+ messages in thread From: Nitka, Grzegorz @ 2025-02-10 10:54 UTC (permalink / raw) To: Simon Horman Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, Nguyen, Anthony L, Kitszel, Przemyslaw, Kolacinski, Karol > -----Original Message----- > From: Simon Horman <horms@kernel.org> > Sent: Friday, February 7, 2025 11:04 AM > To: Nitka, Grzegorz <grzegorz.nitka@intel.com> > Cc: intel-wired-lan@lists.osuosl.org; netdev@vger.kernel.org; Nguyen, > Anthony L <anthony.l.nguyen@intel.com>; Kitszel, Przemyslaw > <przemyslaw.kitszel@intel.com>; Kolacinski, Karol > <karol.kolacinski@intel.com> > Subject: Re: [PATCH iwl-next v1 1/3] ice: Add sync delay for E825C > > On Thu, Feb 06, 2025 at 09:36:53AM +0100, Grzegorz Nitka wrote: > > From: Karol Kolacinski <karol.kolacinski@intel.com> > > > > Implement setting GLTSYN_SYNC_DLAY for E825C products. > > This is the execution delay compensation of SYNC command between > > PHC and PHY. > > Also, refactor the code by changing ice_ptp_init_phc_eth56g function > > name to ice_ptp_init_phc_e825, to be consistent with the naming pattern > > for other devices. > > Adding support for GLTSYN_SYNC_DLAY and the refactor seem > to be two distinct changes, albeit touching common code. > > I think it would be slightly better to split this into two patches. > Sure, will exclude this commit from the series and will submit it as separate patch. Thanks for your review and valuable feedback. > > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> > > Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> > > ... ^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [PATCH iwl-next v1 1/3] ice: Add sync delay for E825C @ 2025-02-10 10:54 ` Nitka, Grzegorz 0 siblings, 0 replies; 20+ messages in thread From: Nitka, Grzegorz @ 2025-02-10 10:54 UTC (permalink / raw) To: Simon Horman Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, Nguyen, Anthony L, Kitszel, Przemyslaw, Kolacinski, Karol > -----Original Message----- > From: Simon Horman <horms@kernel.org> > Sent: Friday, February 7, 2025 11:04 AM > To: Nitka, Grzegorz <grzegorz.nitka@intel.com> > Cc: intel-wired-lan@lists.osuosl.org; netdev@vger.kernel.org; Nguyen, > Anthony L <anthony.l.nguyen@intel.com>; Kitszel, Przemyslaw > <przemyslaw.kitszel@intel.com>; Kolacinski, Karol > <karol.kolacinski@intel.com> > Subject: Re: [PATCH iwl-next v1 1/3] ice: Add sync delay for E825C > > On Thu, Feb 06, 2025 at 09:36:53AM +0100, Grzegorz Nitka wrote: > > From: Karol Kolacinski <karol.kolacinski@intel.com> > > > > Implement setting GLTSYN_SYNC_DLAY for E825C products. > > This is the execution delay compensation of SYNC command between > > PHC and PHY. > > Also, refactor the code by changing ice_ptp_init_phc_eth56g function > > name to ice_ptp_init_phc_e825, to be consistent with the naming pattern > > for other devices. > > Adding support for GLTSYN_SYNC_DLAY and the refactor seem > to be two distinct changes, albeit touching common code. > > I think it would be slightly better to split this into two patches. > Sure, will exclude this commit from the series and will submit it as separate patch. Thanks for your review and valuable feedback. > > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> > > Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> > > ... ^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-wired-lan] [PATCH iwl-next v1 2/3] ice: Refactor E825C PHY registers info struct 2025-02-06 8:36 ` Grzegorz Nitka @ 2025-02-06 8:36 ` Grzegorz Nitka -1 siblings, 0 replies; 20+ messages in thread From: Grzegorz Nitka @ 2025-02-06 8:36 UTC (permalink / raw) To: intel-wired-lan Cc: netdev, Karol Kolacinski, anthony.l.nguyen, przemyslaw.kitszel From: Karol Kolacinski <karol.kolacinski@intel.com> Simplify ice_phy_reg_info_eth56g struct definition to include base address for the very first quad. Use base address info and 'step' value to determine address for specific PHY quad. Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> --- .../net/ethernet/intel/ice/ice_ptp_consts.h | 75 ++++--------------- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 6 +- drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 2 +- 3 files changed, 19 insertions(+), 64 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_consts.h b/drivers/net/ethernet/intel/ice/ice_ptp_consts.h index ac46d1183300..003cdfada3ca 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_consts.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_consts.h @@ -10,70 +10,25 @@ /* Constants defined for the PTP 1588 clock hardware. */ const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES] = { - /* ETH56G_PHY_REG_PTP */ - { - /* base_addr */ - { - 0x092000, - 0x126000, - 0x1BA000, - 0x24E000, - 0x2E2000, - }, - /* step */ - 0x98, + [ETH56G_PHY_REG_PTP] = { + .base_addr = 0x092000, + .step = 0x98, }, - /* ETH56G_PHY_MEM_PTP */ - { - /* base_addr */ - { - 0x093000, - 0x127000, - 0x1BB000, - 0x24F000, - 0x2E3000, - }, - /* step */ - 0x200, + [ETH56G_PHY_MEM_PTP] = { + .base_addr = 0x093000, + .step = 0x200, }, - /* ETH56G_PHY_REG_XPCS */ - { - /* base_addr */ - { - 0x000000, - 0x009400, - 0x128000, - 0x1BC000, - 0x250000, - }, - /* step */ - 0x21000, + [ETH56G_PHY_REG_XPCS] = { + .base_addr = 0x000000, + .step = 0x21000, }, - /* ETH56G_PHY_REG_MAC */ - { - /* base_addr */ - { - 0x085000, - 0x119000, - 0x1AD000, - 0x241000, - 0x2D5000, - }, - /* step */ - 0x1000, + [ETH56G_PHY_REG_MAC] = { + .base_addr = 0x085000, + .step = 0x1000, }, - /* ETH56G_PHY_REG_GPCS */ - { - /* base_addr */ - { - 0x084000, - 0x118000, - 0x1AC000, - 0x240000, - 0x2D4000, - }, - /* step */ - 0x400, + [ETH56G_PHY_REG_GPCS] = { + .base_addr = 0x084000, + .step = 0x400, }, }; diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index c3dea6d61de4..5c61bc3a2c25 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -1010,7 +1010,7 @@ static int ice_phy_res_address_eth56g(struct ice_hw *hw, u8 lane, /* Lanes 4..7 are in fact 0..3 on a second PHY */ lane %= hw->ptp.ports_per_phy; - *addr = eth56g_phy_res[res_type].base[0] + + *addr = eth56g_phy_res[res_type].base_addr + lane * eth56g_phy_res[res_type].step + offset; return 0; @@ -1240,7 +1240,7 @@ static int ice_write_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port, if (port >= hw->ptp.num_lports) return -EIO; - addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base[0] + offset; + addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset; return ice_write_phy_eth56g(hw, port, addr, val); } @@ -1265,7 +1265,7 @@ static int ice_read_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port, if (port >= hw->ptp.num_lports) return -EIO; - addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base[0] + offset; + addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset; return ice_read_phy_eth56g(hw, port, addr, val); } diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index 10295fa9a383..63a63ef64aaa 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -72,7 +72,7 @@ enum ice_eth56g_link_spd { * ETH56G devices */ struct ice_phy_reg_info_eth56g { - u32 base[NUM_ETH56G_PHY_RES]; + u32 base_addr; u32 step; }; -- 2.39.3 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH iwl-next v1 2/3] ice: Refactor E825C PHY registers info struct @ 2025-02-06 8:36 ` Grzegorz Nitka 0 siblings, 0 replies; 20+ messages in thread From: Grzegorz Nitka @ 2025-02-06 8:36 UTC (permalink / raw) To: intel-wired-lan Cc: netdev, anthony.l.nguyen, przemyslaw.kitszel, Karol Kolacinski, Grzegorz Nitka From: Karol Kolacinski <karol.kolacinski@intel.com> Simplify ice_phy_reg_info_eth56g struct definition to include base address for the very first quad. Use base address info and 'step' value to determine address for specific PHY quad. Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> --- .../net/ethernet/intel/ice/ice_ptp_consts.h | 75 ++++--------------- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 6 +- drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 2 +- 3 files changed, 19 insertions(+), 64 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_consts.h b/drivers/net/ethernet/intel/ice/ice_ptp_consts.h index ac46d1183300..003cdfada3ca 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_consts.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_consts.h @@ -10,70 +10,25 @@ /* Constants defined for the PTP 1588 clock hardware. */ const struct ice_phy_reg_info_eth56g eth56g_phy_res[NUM_ETH56G_PHY_RES] = { - /* ETH56G_PHY_REG_PTP */ - { - /* base_addr */ - { - 0x092000, - 0x126000, - 0x1BA000, - 0x24E000, - 0x2E2000, - }, - /* step */ - 0x98, + [ETH56G_PHY_REG_PTP] = { + .base_addr = 0x092000, + .step = 0x98, }, - /* ETH56G_PHY_MEM_PTP */ - { - /* base_addr */ - { - 0x093000, - 0x127000, - 0x1BB000, - 0x24F000, - 0x2E3000, - }, - /* step */ - 0x200, + [ETH56G_PHY_MEM_PTP] = { + .base_addr = 0x093000, + .step = 0x200, }, - /* ETH56G_PHY_REG_XPCS */ - { - /* base_addr */ - { - 0x000000, - 0x009400, - 0x128000, - 0x1BC000, - 0x250000, - }, - /* step */ - 0x21000, + [ETH56G_PHY_REG_XPCS] = { + .base_addr = 0x000000, + .step = 0x21000, }, - /* ETH56G_PHY_REG_MAC */ - { - /* base_addr */ - { - 0x085000, - 0x119000, - 0x1AD000, - 0x241000, - 0x2D5000, - }, - /* step */ - 0x1000, + [ETH56G_PHY_REG_MAC] = { + .base_addr = 0x085000, + .step = 0x1000, }, - /* ETH56G_PHY_REG_GPCS */ - { - /* base_addr */ - { - 0x084000, - 0x118000, - 0x1AC000, - 0x240000, - 0x2D4000, - }, - /* step */ - 0x400, + [ETH56G_PHY_REG_GPCS] = { + .base_addr = 0x084000, + .step = 0x400, }, }; diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index c3dea6d61de4..5c61bc3a2c25 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -1010,7 +1010,7 @@ static int ice_phy_res_address_eth56g(struct ice_hw *hw, u8 lane, /* Lanes 4..7 are in fact 0..3 on a second PHY */ lane %= hw->ptp.ports_per_phy; - *addr = eth56g_phy_res[res_type].base[0] + + *addr = eth56g_phy_res[res_type].base_addr + lane * eth56g_phy_res[res_type].step + offset; return 0; @@ -1240,7 +1240,7 @@ static int ice_write_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port, if (port >= hw->ptp.num_lports) return -EIO; - addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base[0] + offset; + addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset; return ice_write_phy_eth56g(hw, port, addr, val); } @@ -1265,7 +1265,7 @@ static int ice_read_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port, if (port >= hw->ptp.num_lports) return -EIO; - addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base[0] + offset; + addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset; return ice_read_phy_eth56g(hw, port, addr, val); } diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index 10295fa9a383..63a63ef64aaa 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -72,7 +72,7 @@ enum ice_eth56g_link_spd { * ETH56G devices */ struct ice_phy_reg_info_eth56g { - u32 base[NUM_ETH56G_PHY_RES]; + u32 base_addr; u32 step; }; -- 2.39.3 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [Intel-wired-lan] [PATCH iwl-next v1 2/3] ice: Refactor E825C PHY registers info struct 2025-02-06 8:36 ` Grzegorz Nitka @ 2025-02-07 10:03 ` Simon Horman -1 siblings, 0 replies; 20+ messages in thread From: Simon Horman @ 2025-02-07 10:03 UTC (permalink / raw) To: Grzegorz Nitka Cc: intel-wired-lan, netdev, anthony.l.nguyen, przemyslaw.kitszel, Karol Kolacinski On Thu, Feb 06, 2025 at 09:36:54AM +0100, Grzegorz Nitka wrote: > From: Karol Kolacinski <karol.kolacinski@intel.com> > > Simplify ice_phy_reg_info_eth56g struct definition to include base > address for the very first quad. Use base address info and 'step' > value to determine address for specific PHY quad. > > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> > Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> Reviewed-by: Simon Horman <horms@kernel.org> ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH iwl-next v1 2/3] ice: Refactor E825C PHY registers info struct @ 2025-02-07 10:03 ` Simon Horman 0 siblings, 0 replies; 20+ messages in thread From: Simon Horman @ 2025-02-07 10:03 UTC (permalink / raw) To: Grzegorz Nitka Cc: intel-wired-lan, netdev, anthony.l.nguyen, przemyslaw.kitszel, Karol Kolacinski On Thu, Feb 06, 2025 at 09:36:54AM +0100, Grzegorz Nitka wrote: > From: Karol Kolacinski <karol.kolacinski@intel.com> > > Simplify ice_phy_reg_info_eth56g struct definition to include base > address for the very first quad. Use base address info and 'step' > value to determine address for specific PHY quad. > > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> > Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> Reviewed-by: Simon Horman <horms@kernel.org> ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-wired-lan] [PATCH iwl-next v1 2/3] ice: Refactor E825C PHY registers info struct 2025-02-07 10:03 ` Simon Horman @ 2025-02-07 10:05 ` Simon Horman -1 siblings, 0 replies; 20+ messages in thread From: Simon Horman @ 2025-02-07 10:05 UTC (permalink / raw) To: Grzegorz Nitka Cc: intel-wired-lan, netdev, anthony.l.nguyen, przemyslaw.kitszel, Karol Kolacinski On Fri, Feb 07, 2025 at 10:03:45AM +0000, Simon Horman wrote: > On Thu, Feb 06, 2025 at 09:36:54AM +0100, Grzegorz Nitka wrote: > > From: Karol Kolacinski <karol.kolacinski@intel.com> > > > > Simplify ice_phy_reg_info_eth56g struct definition to include base > > address for the very first quad. Use base address info and 'step' > > value to determine address for specific PHY quad. > > > > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> > > Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> > > Reviewed-by: Simon Horman <horms@kernel.org> Sorry, I failed to notice that the kdoc for ice_phy_reg_info_eth56g needs to be updated to document base_addr instead of base. ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH iwl-next v1 2/3] ice: Refactor E825C PHY registers info struct @ 2025-02-07 10:05 ` Simon Horman 0 siblings, 0 replies; 20+ messages in thread From: Simon Horman @ 2025-02-07 10:05 UTC (permalink / raw) To: Grzegorz Nitka Cc: intel-wired-lan, netdev, anthony.l.nguyen, przemyslaw.kitszel, Karol Kolacinski On Fri, Feb 07, 2025 at 10:03:45AM +0000, Simon Horman wrote: > On Thu, Feb 06, 2025 at 09:36:54AM +0100, Grzegorz Nitka wrote: > > From: Karol Kolacinski <karol.kolacinski@intel.com> > > > > Simplify ice_phy_reg_info_eth56g struct definition to include base > > address for the very first quad. Use base address info and 'step' > > value to determine address for specific PHY quad. > > > > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> > > Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> > > Reviewed-by: Simon Horman <horms@kernel.org> Sorry, I failed to notice that the kdoc for ice_phy_reg_info_eth56g needs to be updated to document base_addr instead of base. ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-wired-lan] [PATCH iwl-next v1 2/3] ice: Refactor E825C PHY registers info struct 2025-02-07 10:05 ` Simon Horman @ 2025-02-10 11:05 ` Nitka, Grzegorz -1 siblings, 0 replies; 20+ messages in thread From: Nitka, Grzegorz @ 2025-02-10 11:05 UTC (permalink / raw) To: Simon Horman Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, Nguyen, Anthony L, Kitszel, Przemyslaw, Kolacinski, Karol > -----Original Message----- > From: Simon Horman <horms@kernel.org> > Sent: Friday, February 7, 2025 11:06 AM > To: Nitka, Grzegorz <grzegorz.nitka@intel.com> > Cc: intel-wired-lan@lists.osuosl.org; netdev@vger.kernel.org; Nguyen, > Anthony L <anthony.l.nguyen@intel.com>; Kitszel, Przemyslaw > <przemyslaw.kitszel@intel.com>; Kolacinski, Karol > <karol.kolacinski@intel.com> > Subject: Re: [PATCH iwl-next v1 2/3] ice: Refactor E825C PHY registers info > struct > > On Fri, Feb 07, 2025 at 10:03:45AM +0000, Simon Horman wrote: > > On Thu, Feb 06, 2025 at 09:36:54AM +0100, Grzegorz Nitka wrote: > > > From: Karol Kolacinski <karol.kolacinski@intel.com> > > > > > > Simplify ice_phy_reg_info_eth56g struct definition to include base > > > address for the very first quad. Use base address info and 'step' > > > value to determine address for specific PHY quad. > > > > > > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > > > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> > > > Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> > > > > Reviewed-by: Simon Horman <horms@kernel.org> > > Sorry, I failed to notice that the kdoc for ice_phy_reg_info_eth56g > needs to be updated to document base_addr instead of base. Good catch! Thanks! To be fixed in v2. ^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [PATCH iwl-next v1 2/3] ice: Refactor E825C PHY registers info struct @ 2025-02-10 11:05 ` Nitka, Grzegorz 0 siblings, 0 replies; 20+ messages in thread From: Nitka, Grzegorz @ 2025-02-10 11:05 UTC (permalink / raw) To: Simon Horman Cc: intel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org, Nguyen, Anthony L, Kitszel, Przemyslaw, Kolacinski, Karol > -----Original Message----- > From: Simon Horman <horms@kernel.org> > Sent: Friday, February 7, 2025 11:06 AM > To: Nitka, Grzegorz <grzegorz.nitka@intel.com> > Cc: intel-wired-lan@lists.osuosl.org; netdev@vger.kernel.org; Nguyen, > Anthony L <anthony.l.nguyen@intel.com>; Kitszel, Przemyslaw > <przemyslaw.kitszel@intel.com>; Kolacinski, Karol > <karol.kolacinski@intel.com> > Subject: Re: [PATCH iwl-next v1 2/3] ice: Refactor E825C PHY registers info > struct > > On Fri, Feb 07, 2025 at 10:03:45AM +0000, Simon Horman wrote: > > On Thu, Feb 06, 2025 at 09:36:54AM +0100, Grzegorz Nitka wrote: > > > From: Karol Kolacinski <karol.kolacinski@intel.com> > > > > > > Simplify ice_phy_reg_info_eth56g struct definition to include base > > > address for the very first quad. Use base address info and 'step' > > > value to determine address for specific PHY quad. > > > > > > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > > > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> > > > Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> > > > > Reviewed-by: Simon Horman <horms@kernel.org> > > Sorry, I failed to notice that the kdoc for ice_phy_reg_info_eth56g > needs to be updated to document base_addr instead of base. Good catch! Thanks! To be fixed in v2. ^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-wired-lan] [PATCH iwl-next v1 3/3] ice: E825C PHY register cleanup 2025-02-06 8:36 ` Grzegorz Nitka @ 2025-02-06 8:36 ` Grzegorz Nitka -1 siblings, 0 replies; 20+ messages in thread From: Grzegorz Nitka @ 2025-02-06 8:36 UTC (permalink / raw) To: intel-wired-lan Cc: netdev, Karol Kolacinski, anthony.l.nguyen, przemyslaw.kitszel From: Karol Kolacinski <karol.kolacinski@intel.com> Minor PTP register refactor, including logical grouping E825C 1-step timestamping registers. Remove unused register definitions (PHY_REG_GPCS_BITSLIP, PHY_REG_REVISION). Also, apply preferred GENMASK macro (instead of ICE_M) for register fields definition affected by this patch. Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> --- drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 31 ++++++++++----------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index 63a63ef64aaa..6ca1561ec5e8 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -783,36 +783,19 @@ static inline bool ice_is_dual(struct ice_hw *hw) #define PHY_MAC_XIF_TS_SFD_ENA_M ICE_M(0x1, 20) #define PHY_MAC_XIF_GMII_TS_SEL_M ICE_M(0x1, 21) -/* GPCS config register */ -#define PHY_GPCS_CONFIG_REG0 0x268 -#define PHY_GPCS_CONFIG_REG0_TX_THR_M ICE_M(0xF, 24) -#define PHY_GPCS_BITSLIP 0x5C - #define PHY_TS_INT_CONFIG_THRESHOLD_M ICE_M(0x3F, 0) #define PHY_TS_INT_CONFIG_ENA_M BIT(6) -/* 1-step PTP config */ -#define PHY_PTP_1STEP_CONFIG 0x270 -#define PHY_PTP_1STEP_T1S_UP64_M ICE_M(0xF, 4) -#define PHY_PTP_1STEP_T1S_DELTA_M ICE_M(0xF, 8) -#define PHY_PTP_1STEP_PEER_DELAY(_port) (0x274 + 4 * (_port)) -#define PHY_PTP_1STEP_PD_ADD_PD_M ICE_M(0x1, 0) -#define PHY_PTP_1STEP_PD_DELAY_M ICE_M(0x3fffffff, 1) -#define PHY_PTP_1STEP_PD_DLY_V_M ICE_M(0x1, 31) - /* Macros to derive offsets for TimeStampLow and TimeStampHigh */ #define PHY_TSTAMP_L(x) (((x) * 8) + 0) #define PHY_TSTAMP_U(x) (((x) * 8) + 4) -#define PHY_REG_REVISION 0x85000 - #define PHY_REG_DESKEW_0 0x94 #define PHY_REG_DESKEW_0_RLEVEL GENMASK(6, 0) #define PHY_REG_DESKEW_0_RLEVEL_FRAC GENMASK(9, 7) #define PHY_REG_DESKEW_0_RLEVEL_FRAC_W 3 #define PHY_REG_DESKEW_0_VALID GENMASK(10, 10) -#define PHY_REG_GPCS_BITSLIP 0x5C #define PHY_REG_SD_BIT_SLIP(_port_offset) (0x29C + 4 * (_port_offset)) #define PHY_REVISION_ETH56G 0x10200 #define PHY_VENDOR_TXLANE_THRESH 0x2000C @@ -832,7 +815,21 @@ static inline bool ice_is_dual(struct ice_hw *hw) #define PHY_MAC_BLOCKTIME 0x50 #define PHY_MAC_MARKERTIME 0x54 #define PHY_MAC_TX_OFFSET 0x58 +#define PHY_GPCS_BITSLIP 0x5C #define PHY_PTP_INT_STATUS 0x7FD140 +/* ETH56G registers shared per quad */ +/* GPCS config register */ +#define PHY_GPCS_CONFIG_REG0 0x268 +#define PHY_GPCS_CONFIG_REG0_TX_THR_M GENMASK(27, 24) +/* 1-step PTP config */ +#define PHY_PTP_1STEP_CONFIG 0x270 +#define PHY_PTP_1STEP_T1S_UP64_M GENMASK(7, 4) +#define PHY_PTP_1STEP_T1S_DELTA_M GENMASK(11, 8) +#define PHY_PTP_1STEP_PEER_DELAY(_quad_lane) (0x274 + 4 * (_quad_lane)) +#define PHY_PTP_1STEP_PD_ADD_PD_M BIT(0) +#define PHY_PTP_1STEP_PD_DELAY_M GENMASK(30, 1) +#define PHY_PTP_1STEP_PD_DLY_V_M BIT(31) + #endif /* _ICE_PTP_HW_H_ */ -- 2.39.3 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH iwl-next v1 3/3] ice: E825C PHY register cleanup @ 2025-02-06 8:36 ` Grzegorz Nitka 0 siblings, 0 replies; 20+ messages in thread From: Grzegorz Nitka @ 2025-02-06 8:36 UTC (permalink / raw) To: intel-wired-lan Cc: netdev, anthony.l.nguyen, przemyslaw.kitszel, Karol Kolacinski, Grzegorz Nitka From: Karol Kolacinski <karol.kolacinski@intel.com> Minor PTP register refactor, including logical grouping E825C 1-step timestamping registers. Remove unused register definitions (PHY_REG_GPCS_BITSLIP, PHY_REG_REVISION). Also, apply preferred GENMASK macro (instead of ICE_M) for register fields definition affected by this patch. Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> --- drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 31 ++++++++++----------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index 63a63ef64aaa..6ca1561ec5e8 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -783,36 +783,19 @@ static inline bool ice_is_dual(struct ice_hw *hw) #define PHY_MAC_XIF_TS_SFD_ENA_M ICE_M(0x1, 20) #define PHY_MAC_XIF_GMII_TS_SEL_M ICE_M(0x1, 21) -/* GPCS config register */ -#define PHY_GPCS_CONFIG_REG0 0x268 -#define PHY_GPCS_CONFIG_REG0_TX_THR_M ICE_M(0xF, 24) -#define PHY_GPCS_BITSLIP 0x5C - #define PHY_TS_INT_CONFIG_THRESHOLD_M ICE_M(0x3F, 0) #define PHY_TS_INT_CONFIG_ENA_M BIT(6) -/* 1-step PTP config */ -#define PHY_PTP_1STEP_CONFIG 0x270 -#define PHY_PTP_1STEP_T1S_UP64_M ICE_M(0xF, 4) -#define PHY_PTP_1STEP_T1S_DELTA_M ICE_M(0xF, 8) -#define PHY_PTP_1STEP_PEER_DELAY(_port) (0x274 + 4 * (_port)) -#define PHY_PTP_1STEP_PD_ADD_PD_M ICE_M(0x1, 0) -#define PHY_PTP_1STEP_PD_DELAY_M ICE_M(0x3fffffff, 1) -#define PHY_PTP_1STEP_PD_DLY_V_M ICE_M(0x1, 31) - /* Macros to derive offsets for TimeStampLow and TimeStampHigh */ #define PHY_TSTAMP_L(x) (((x) * 8) + 0) #define PHY_TSTAMP_U(x) (((x) * 8) + 4) -#define PHY_REG_REVISION 0x85000 - #define PHY_REG_DESKEW_0 0x94 #define PHY_REG_DESKEW_0_RLEVEL GENMASK(6, 0) #define PHY_REG_DESKEW_0_RLEVEL_FRAC GENMASK(9, 7) #define PHY_REG_DESKEW_0_RLEVEL_FRAC_W 3 #define PHY_REG_DESKEW_0_VALID GENMASK(10, 10) -#define PHY_REG_GPCS_BITSLIP 0x5C #define PHY_REG_SD_BIT_SLIP(_port_offset) (0x29C + 4 * (_port_offset)) #define PHY_REVISION_ETH56G 0x10200 #define PHY_VENDOR_TXLANE_THRESH 0x2000C @@ -832,7 +815,21 @@ static inline bool ice_is_dual(struct ice_hw *hw) #define PHY_MAC_BLOCKTIME 0x50 #define PHY_MAC_MARKERTIME 0x54 #define PHY_MAC_TX_OFFSET 0x58 +#define PHY_GPCS_BITSLIP 0x5C #define PHY_PTP_INT_STATUS 0x7FD140 +/* ETH56G registers shared per quad */ +/* GPCS config register */ +#define PHY_GPCS_CONFIG_REG0 0x268 +#define PHY_GPCS_CONFIG_REG0_TX_THR_M GENMASK(27, 24) +/* 1-step PTP config */ +#define PHY_PTP_1STEP_CONFIG 0x270 +#define PHY_PTP_1STEP_T1S_UP64_M GENMASK(7, 4) +#define PHY_PTP_1STEP_T1S_DELTA_M GENMASK(11, 8) +#define PHY_PTP_1STEP_PEER_DELAY(_quad_lane) (0x274 + 4 * (_quad_lane)) +#define PHY_PTP_1STEP_PD_ADD_PD_M BIT(0) +#define PHY_PTP_1STEP_PD_DELAY_M GENMASK(30, 1) +#define PHY_PTP_1STEP_PD_DLY_V_M BIT(31) + #endif /* _ICE_PTP_HW_H_ */ -- 2.39.3 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [Intel-wired-lan] [PATCH iwl-next v1 3/3] ice: E825C PHY register cleanup 2025-02-06 8:36 ` Grzegorz Nitka @ 2025-02-07 10:07 ` Simon Horman -1 siblings, 0 replies; 20+ messages in thread From: Simon Horman @ 2025-02-07 10:07 UTC (permalink / raw) To: Grzegorz Nitka Cc: intel-wired-lan, netdev, anthony.l.nguyen, przemyslaw.kitszel, Karol Kolacinski On Thu, Feb 06, 2025 at 09:36:55AM +0100, Grzegorz Nitka wrote: > From: Karol Kolacinski <karol.kolacinski@intel.com> > > Minor PTP register refactor, including logical grouping E825C 1-step > timestamping registers. Remove unused register definitions > (PHY_REG_GPCS_BITSLIP, PHY_REG_REVISION). > Also, apply preferred GENMASK macro (instead of ICE_M) for register > fields definition affected by this patch. > > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> > Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> In reference to my comment on patch 1/3, this patch is also doing sevearl things. But I think that is fine because: they are all cleanups; they are somewhat related to each other; and overall the patch is still not so long. Reviewed-by: Simon Horman <horms@kernel.org> ... ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH iwl-next v1 3/3] ice: E825C PHY register cleanup @ 2025-02-07 10:07 ` Simon Horman 0 siblings, 0 replies; 20+ messages in thread From: Simon Horman @ 2025-02-07 10:07 UTC (permalink / raw) To: Grzegorz Nitka Cc: intel-wired-lan, netdev, anthony.l.nguyen, przemyslaw.kitszel, Karol Kolacinski On Thu, Feb 06, 2025 at 09:36:55AM +0100, Grzegorz Nitka wrote: > From: Karol Kolacinski <karol.kolacinski@intel.com> > > Minor PTP register refactor, including logical grouping E825C 1-step > timestamping registers. Remove unused register definitions > (PHY_REG_GPCS_BITSLIP, PHY_REG_REVISION). > Also, apply preferred GENMASK macro (instead of ICE_M) for register > fields definition affected by this patch. > > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> > Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com> In reference to my comment on patch 1/3, this patch is also doing sevearl things. But I think that is fine because: they are all cleanups; they are somewhat related to each other; and overall the patch is still not so long. Reviewed-by: Simon Horman <horms@kernel.org> ... ^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2025-02-10 11:05 UTC | newest] Thread overview: 20+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-02-06 8:36 [Intel-wired-lan] [PATCH iwl-next v1 0/3] E825C PTP cleanup Grzegorz Nitka 2025-02-06 8:36 ` Grzegorz Nitka 2025-02-06 8:36 ` [Intel-wired-lan] [PATCH iwl-next v1 1/3] ice: Add sync delay for E825C Grzegorz Nitka 2025-02-06 8:36 ` Grzegorz Nitka 2025-02-07 10:03 ` [Intel-wired-lan] " Simon Horman 2025-02-07 10:03 ` Simon Horman 2025-02-10 10:54 ` [Intel-wired-lan] " Nitka, Grzegorz 2025-02-10 10:54 ` Nitka, Grzegorz 2025-02-06 8:36 ` [Intel-wired-lan] [PATCH iwl-next v1 2/3] ice: Refactor E825C PHY registers info struct Grzegorz Nitka 2025-02-06 8:36 ` Grzegorz Nitka 2025-02-07 10:03 ` [Intel-wired-lan] " Simon Horman 2025-02-07 10:03 ` Simon Horman 2025-02-07 10:05 ` [Intel-wired-lan] " Simon Horman 2025-02-07 10:05 ` Simon Horman 2025-02-10 11:05 ` [Intel-wired-lan] " Nitka, Grzegorz 2025-02-10 11:05 ` Nitka, Grzegorz 2025-02-06 8:36 ` [Intel-wired-lan] [PATCH iwl-next v1 3/3] ice: E825C PHY register cleanup Grzegorz Nitka 2025-02-06 8:36 ` Grzegorz Nitka 2025-02-07 10:07 ` [Intel-wired-lan] " Simon Horman 2025-02-07 10:07 ` Simon Horman
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.