From: Jamin Lin via <qemu-arm@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>
Subject: [PATCH v1 06/21] hw/arm/ast27x0: Add SRAM alias for SSP and ensure correct device realization order
Date: Thu, 17 Jul 2025 11:40:34 +0800 [thread overview]
Message-ID: <20250717034054.1903991-7-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com>
AST2700 has a 128KB SRAM, physically mapped at 0x10000000–0x1001FFFF for the
main CA35 processor. The SSP coprocessor accesses this same memory at a
different memory address: 0x70000000–0x7001FFFF.
To support this shared memory model, this commit introduces "ssp.sram_mr_alias",
a "MemoryRegion" alias of the original SRAM region ("s->sram"). The alias is
realized during SSP SoC setup and mapped into the SSP's SoC memory map.
Additionally, because the SRAM must be realized before the SSP can create an
alias to it, the device realization order is explicitly managed:
"aspeed_soc_ast2700_ssp_realize()" is invoked after SRAM is initialized.
This ensures that SSP’s access to shared SRAM functions correctly.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 1 +
hw/arm/aspeed_ast27x0-ssp.c | 5 +++++
hw/arm/aspeed_ast27x0.c | 15 ++++++++++++++-
3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 3dd317cfee..9b935b9bca 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -134,6 +134,7 @@ struct Aspeed27x0SSPSoCState {
UnimplementedDeviceState ipc[2];
UnimplementedDeviceState scuio;
MemoryRegion memory;
+ MemoryRegion sram_mr_alias;
ARMv7MState armv7m;
};
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 9641e27de1..b7b886f4bf 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -19,6 +19,7 @@
static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
[ASPEED_DEV_SDRAM] = 0x00000000,
+ [ASPEED_DEV_SRAM] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
@@ -192,6 +193,10 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
sc->memmap[ASPEED_DEV_SDRAM],
&s->dram_container);
+ /* SRAM */
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
+ &a->sram_mr_alias);
+
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 665627f788..9064249bed 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -624,6 +624,7 @@ static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp)
{
Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
AspeedSoCState *s = ASPEED_SOC(dev);
+ MemoryRegion *mr;
Clock *sysclk;
sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
@@ -637,6 +638,9 @@ static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp)
return false;
}
+ mr = &s->sram;
+ memory_region_init_alias(&a->ssp.sram_mr_alias, OBJECT(s), "ssp.sram.alias",
+ mr, 0, memory_region_size(mr));
if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) {
return false;
}
@@ -779,7 +783,16 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0,
sc->memmap[ASPEED_DEV_SCUIO]);
- /* Coprocessors */
+ /*
+ * Coprocessors must be realized after the SRAM region.
+ *
+ * The SRAM is used for shared memory between the main CPU (PSP) and
+ * coprocessors. The coprocessors accesses this shared SRAM region
+ * through a memory alias mapped to a different physical address.
+ *
+ * Therefore, the SRAM must be fully initialized before the coprocessors
+ * can create aliases pointing to it.
+ */
if (mc->default_cpus > sc->num_cpus) {
if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) {
return;
--
2.43.0
WARNING: multiple messages have this Message-ID (diff)
From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Steven Lee" <steven_lee@aspeedtech.com>,
"Troy Lee" <leetroy@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Joel Stanley" <joel@jms.id.au>,
"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>
Subject: [PATCH v1 06/21] hw/arm/ast27x0: Add SRAM alias for SSP and ensure correct device realization order
Date: Thu, 17 Jul 2025 11:40:34 +0800 [thread overview]
Message-ID: <20250717034054.1903991-7-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20250717034054.1903991-1-jamin_lin@aspeedtech.com>
AST2700 has a 128KB SRAM, physically mapped at 0x10000000–0x1001FFFF for the
main CA35 processor. The SSP coprocessor accesses this same memory at a
different memory address: 0x70000000–0x7001FFFF.
To support this shared memory model, this commit introduces "ssp.sram_mr_alias",
a "MemoryRegion" alias of the original SRAM region ("s->sram"). The alias is
realized during SSP SoC setup and mapped into the SSP's SoC memory map.
Additionally, because the SRAM must be realized before the SSP can create an
alias to it, the device realization order is explicitly managed:
"aspeed_soc_ast2700_ssp_realize()" is invoked after SRAM is initialized.
This ensures that SSP’s access to shared SRAM functions correctly.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed_soc.h | 1 +
hw/arm/aspeed_ast27x0-ssp.c | 5 +++++
hw/arm/aspeed_ast27x0.c | 15 ++++++++++++++-
3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 3dd317cfee..9b935b9bca 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -134,6 +134,7 @@ struct Aspeed27x0SSPSoCState {
UnimplementedDeviceState ipc[2];
UnimplementedDeviceState scuio;
MemoryRegion memory;
+ MemoryRegion sram_mr_alias;
ARMv7MState armv7m;
};
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 9641e27de1..b7b886f4bf 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -19,6 +19,7 @@
static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
[ASPEED_DEV_SDRAM] = 0x00000000,
+ [ASPEED_DEV_SRAM] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
@@ -192,6 +193,10 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
sc->memmap[ASPEED_DEV_SDRAM],
&s->dram_container);
+ /* SRAM */
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
+ &a->sram_mr_alias);
+
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index 665627f788..9064249bed 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -624,6 +624,7 @@ static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp)
{
Aspeed27x0SoCState *a = ASPEED27X0_SOC(dev);
AspeedSoCState *s = ASPEED_SOC(dev);
+ MemoryRegion *mr;
Clock *sysclk;
sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
@@ -637,6 +638,9 @@ static bool aspeed_soc_ast2700_ssp_realize(DeviceState *dev, Error **errp)
return false;
}
+ mr = &s->sram;
+ memory_region_init_alias(&a->ssp.sram_mr_alias, OBJECT(s), "ssp.sram.alias",
+ mr, 0, memory_region_size(mr));
if (!qdev_realize(DEVICE(&a->ssp), NULL, &error_abort)) {
return false;
}
@@ -779,7 +783,16 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scuio), 0,
sc->memmap[ASPEED_DEV_SCUIO]);
- /* Coprocessors */
+ /*
+ * Coprocessors must be realized after the SRAM region.
+ *
+ * The SRAM is used for shared memory between the main CPU (PSP) and
+ * coprocessors. The coprocessors accesses this shared SRAM region
+ * through a memory alias mapped to a different physical address.
+ *
+ * Therefore, the SRAM must be fully initialized before the coprocessors
+ * can create aliases pointing to it.
+ */
if (mc->default_cpus > sc->num_cpus) {
if (!aspeed_soc_ast2700_ssp_realize(dev, errp)) {
return;
--
2.43.0
next prev parent reply other threads:[~2025-07-17 3:44 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-17 3:40 [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 01/21] hw/arm/aspeed_ast27x0-fc: Support VBootRom Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-09-02 6:01 ` [SPAM] " Cédric Le Goater
2025-09-02 8:28 ` Jamin Lin
2025-09-02 13:23 ` Cédric Le Goater
2025-09-03 5:19 ` Jamin Lin
2025-09-03 8:48 ` Jamin Lin
2025-07-17 3:40 ` [PATCH v1 02/21] hw/arm/ast27x0: Move SSP coprocessor initialization from machine to SoC leve Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-09-02 6:20 ` [SPAM] " Cédric Le Goater
2025-09-02 7:27 ` Markus Armbruster
2025-09-02 8:49 ` Jamin Lin
2025-09-02 9:39 ` Markus Armbruster
2025-09-02 8:41 ` Jamin Lin
2025-09-02 13:24 ` Cédric Le Goater
2025-07-17 3:40 ` [PATCH v1 03/21] hw/arm/ast27x0: Move TSP " Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 04/21] hw/arm/aspeed_ast27x0-ssp: Switch SSP memory to SDRAM and use dram_container for remap support Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-09-02 7:36 ` [SPAM] " Cédric Le Goater
2025-09-03 1:45 ` Jamin Lin
2025-07-17 3:40 ` [PATCH v1 05/21] hw/arm/aspeed_ast27x0-tsp: Switch TSP " Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via [this message]
2025-07-17 3:40 ` [PATCH v1 06/21] hw/arm/ast27x0: Add SRAM alias for SSP and ensure correct device realization order Jamin Lin via
2025-09-02 7:47 ` [SPAM] " Cédric Le Goater
2025-09-03 1:48 ` Jamin Lin
2025-07-17 3:40 ` [PATCH v1 07/21] hw/arm/ast27x0: Add SRAM alias for TSP " Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 08/21] hw/arm/ast27x0: Add SCU alias for SSP " Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-09-02 8:09 ` [SPAM] " Cédric Le Goater
2025-09-23 8:31 ` Jamin Lin
2025-09-23 11:33 ` Cédric Le Goater
2025-09-24 6:03 ` Jamin Lin
2025-09-24 11:13 ` Cédric Le Goater
2025-09-25 2:32 ` Jamin Lin
2025-09-26 3:13 ` Jamin Lin
2025-09-26 7:44 ` Cédric Le Goater
2025-07-17 3:40 ` [PATCH v1 09/21] hw/arm/ast27x0: Add SCU alias for TSP " Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 10/21] hw/arm/ast27x0: Move DRAM and SDMC initialization earlier to support memory aliasing Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-09-02 7:51 ` [SPAM] " Cédric Le Goater
2025-09-03 1:50 ` Jamin Lin
2025-07-17 3:40 ` [PATCH v1 11/21] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap and update realization order Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 12/21] hw/arm/ast27x0: Add DRAM alias for TSP " Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 13/21] hw/arm/ast27x0: Start SSP in powered-off state to match hardware behavior Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 14/21] hw/arm/ast27x0: Start TSP " Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 15/21] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 16/21] hw/misc/aspeed_scu: Add SCU support for TSP " Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 17/21] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 18/21] hw/misc/aspeed_scu: Implement TSP " Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-07-22 15:21 ` [SPAM] " Cédric Le Goater
2025-07-23 2:42 ` Jamin Lin
2025-07-27 19:51 ` Michael Tokarev
2025-07-28 6:49 ` Cédric Le Goater
2025-07-28 7:02 ` Jamin Lin via
2025-07-28 7:02 ` Jamin Lin via
2025-07-28 7:11 ` Cédric Le Goater
2025-07-28 7:11 ` Michael Tokarev
2025-07-28 7:41 ` Jamin Lin via
2025-07-28 7:41 ` Jamin Lin via
2025-07-29 9:12 ` Cédric Le Goater
2025-07-30 1:47 ` Jamin Lin via
2025-07-30 1:47 ` Jamin Lin via
2025-07-30 4:59 ` Cédric Le Goater
2025-07-28 8:32 ` Michael Tokarev
2025-07-28 8:40 ` Cédric Le Goater
2025-07-17 3:40 ` [PATCH v1 20/21] tests/function/aspeed: Replace manual loader with vbootrom for ast2700fc test Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-07-17 3:40 ` [PATCH v1 21/21] docs: Add support vbootrom for ast2700fc Jamin Lin via
2025-07-17 3:40 ` Jamin Lin via
2025-07-17 5:22 ` [PATCH v1 00/21] Control coprocessor reset for AST2700 Jamin Lin
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