* [PATCH 1/2] drm/scdc: add frl config/status registers to scdc header.
@ 2025-11-14 3:53 Dave Airlie
2025-11-14 3:53 ` [PATCH 2/2] amd/dc: add frl bits to the registers Dave Airlie
2025-11-21 14:31 ` [PATCH 1/2] drm/scdc: add frl config/status registers to scdc header Derek Foreman
0 siblings, 2 replies; 4+ messages in thread
From: Dave Airlie @ 2025-11-14 3:53 UTC (permalink / raw)
To: dri-devel
From: Dave Airlie <airlied@redhat.com>
These are sourced from publically available presentations like
https://www.ti.com/content/dam/videos/external-videos/en-us/11/3816841626001/overview-ddc-bus-hdmi-systems.mp4/subassets/overview-ddc-bus-hdmi-systems-presentation.pdf
Document in the kernel in case they are of use to someone.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
include/drm/display/drm_scdc.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/include/drm/display/drm_scdc.h b/include/drm/display/drm_scdc.h
index 3d58f37e8ed8..3b6a8a4a4bca 100644
--- a/include/drm/display/drm_scdc.h
+++ b/include/drm/display/drm_scdc.h
@@ -29,6 +29,8 @@
#define SCDC_SOURCE_VERSION 0x02
#define SCDC_UPDATE_0 0x10
+#define SCDC_FLT_UPDATE (1 << 5)
+#define SCDC_FRL_START (1 << 4)
#define SCDC_READ_REQUEST_TEST (1 << 2)
#define SCDC_CED_UPDATE (1 << 1)
#define SCDC_STATUS_UPDATE (1 << 0)
@@ -46,7 +48,20 @@
#define SCDC_CONFIG_0 0x30
#define SCDC_READ_REQUEST_ENABLE (1 << 0)
+#define SCDC_CONFIG_FRL 0x31
+#define SCDC_FRL_RATE(x) (((x) & 0x7) << 0)
+#define SCDC_FRL_RATE_DISABLE 0
+#define SCDC_FRL_RATE_FIXED_3LANE_3GB 1
+#define SCDC_FRL_RATE_FIXED_3LANE_6GB 2
+#define SCDC_FRL_RATE_FIXED_4LANE_6GB 3
+#define SCDC_FRL_RATE_FIXED_4LANE_8GB 4
+#define SCDC_FRL_RATE_FIXED_4LANE_10GB 5
+#define SCDC_FRL_RATE_FIXED_4LANE_12GB 6
+#define SCDC_FRL_FFE_LEVELS(x) (((x) & 0xF) << 4)
+
#define SCDC_STATUS_FLAGS_0 0x40
+#define SCDC_FLT_READY (1 << 6)
+#define SCDC_LANE3_LOCK (1 << 4)
#define SCDC_CH2_LOCK (1 << 3)
#define SCDC_CH1_LOCK (1 << 2)
#define SCDC_CH0_LOCK (1 << 1)
@@ -55,6 +70,9 @@
#define SCDC_STATUS_FLAGS_1 0x41
+#define SCDC_LN_LTP_01 0x41
+#define SCDC_LN_LTP_23 0x42
+
#define SCDC_ERR_DET_0_L 0x50
#define SCDC_ERR_DET_0_H 0x51
#define SCDC_ERR_DET_1_L 0x52
--
2.51.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] amd/dc: add frl bits to the registers
2025-11-14 3:53 [PATCH 1/2] drm/scdc: add frl config/status registers to scdc header Dave Airlie
@ 2025-11-14 3:53 ` Dave Airlie
2025-11-21 14:31 ` Derek Foreman
2025-11-21 14:31 ` [PATCH 1/2] drm/scdc: add frl config/status registers to scdc header Derek Foreman
1 sibling, 1 reply; 4+ messages in thread
From: Dave Airlie @ 2025-11-14 3:53 UTC (permalink / raw)
To: dri-devel
From: Dave Airlie <airlied@redhat.com>
document the same bits as added to the main headers.
Signed-off-by: Dave Airlie <airlied@redhat.com>
---
.../gpu/drm/amd/display/dc/dc_hdmi_types.h | 30 +++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h b/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h
index b015e80672ec..693129b987ac 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h
@@ -77,11 +77,24 @@ union hdmi_scdc_update_read_data {
uint8_t STATUS_UPDATE:1;
uint8_t CED_UPDATE:1;
uint8_t RR_TEST:1;
- uint8_t RESERVED:5;
+ uint8_t RESERVED0:1;
+ uint8_t FRL_START:1;
+ uint8_t FLT_UPDATE:1;
+ uint8_t RESERVED:2;
uint8_t RESERVED2:8;
} fields;
};
+union hdmi_scdc_config_data {
+ uint8_t byte[2];
+ struct {
+ uint8_t RR_ENABLE:1;
+ uint8_t RESERVED:7;
+ uint8_t FRL_RATE:4;
+ uint8_t FFE_LEVELS:4;
+ } fields;
+};
+
union hdmi_scdc_status_flags_data {
uint8_t byte;
struct {
@@ -89,7 +102,20 @@ union hdmi_scdc_status_flags_data {
uint8_t CH0_LOCKED:1;
uint8_t CH1_LOCKED:1;
uint8_t CH2_LOCKED:1;
- uint8_t RESERVED:4;
+ uint8_t LANE3_LOCKED:1;
+ uint8_t RESERVED:1;
+ uint8_t FLT_READY:1;
+ uint8_t RESERVED2:1;
+ } fields;
+};
+
+union hdmi_scdc_lane_status_data {
+ uint8_t byte[2];
+ struct {
+ uint8_t ltp_0:4;
+ uint8_t ltp_1:4;
+ uint8_t ltp_2:4;
+ uint8_t ltp_3:4;
} fields;
};
--
2.51.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] drm/scdc: add frl config/status registers to scdc header.
2025-11-14 3:53 [PATCH 1/2] drm/scdc: add frl config/status registers to scdc header Dave Airlie
2025-11-14 3:53 ` [PATCH 2/2] amd/dc: add frl bits to the registers Dave Airlie
@ 2025-11-21 14:31 ` Derek Foreman
1 sibling, 0 replies; 4+ messages in thread
From: Derek Foreman @ 2025-11-21 14:31 UTC (permalink / raw)
To: Dave Airlie, dri-devel
On 11/13/25 9:53 PM, Dave Airlie wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> These are sourced from publically available presentations like
> https://www.ti.com/content/dam/videos/external-videos/en-us/11/3816841626001/overview-ddc-bus-hdmi-systems.mp4/subassets/overview-ddc-bus-hdmi-systems-presentation.pdf
>
> Document in the kernel in case they are of use to someone.
>
> Signed-off-by: Dave Airlie <airlied@redhat.com>
> ---
> include/drm/display/drm_scdc.h | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
Acked-by: Derek Foreman <derek.foreman@collabora.com>
> diff --git a/include/drm/display/drm_scdc.h b/include/drm/display/drm_scdc.h
> index 3d58f37e8ed8..3b6a8a4a4bca 100644
> --- a/include/drm/display/drm_scdc.h
> +++ b/include/drm/display/drm_scdc.h
> @@ -29,6 +29,8 @@
> #define SCDC_SOURCE_VERSION 0x02
>
> #define SCDC_UPDATE_0 0x10
> +#define SCDC_FLT_UPDATE (1 << 5)
> +#define SCDC_FRL_START (1 << 4)
> #define SCDC_READ_REQUEST_TEST (1 << 2)
> #define SCDC_CED_UPDATE (1 << 1)
> #define SCDC_STATUS_UPDATE (1 << 0)
> @@ -46,7 +48,20 @@
> #define SCDC_CONFIG_0 0x30
> #define SCDC_READ_REQUEST_ENABLE (1 << 0)
>
> +#define SCDC_CONFIG_FRL 0x31
> +#define SCDC_FRL_RATE(x) (((x) & 0x7) << 0)
> +#define SCDC_FRL_RATE_DISABLE 0
> +#define SCDC_FRL_RATE_FIXED_3LANE_3GB 1
> +#define SCDC_FRL_RATE_FIXED_3LANE_6GB 2
> +#define SCDC_FRL_RATE_FIXED_4LANE_6GB 3
> +#define SCDC_FRL_RATE_FIXED_4LANE_8GB 4
> +#define SCDC_FRL_RATE_FIXED_4LANE_10GB 5
> +#define SCDC_FRL_RATE_FIXED_4LANE_12GB 6
> +#define SCDC_FRL_FFE_LEVELS(x) (((x) & 0xF) << 4)
> +
> #define SCDC_STATUS_FLAGS_0 0x40
> +#define SCDC_FLT_READY (1 << 6)
> +#define SCDC_LANE3_LOCK (1 << 4)
> #define SCDC_CH2_LOCK (1 << 3)
> #define SCDC_CH1_LOCK (1 << 2)
> #define SCDC_CH0_LOCK (1 << 1)
> @@ -55,6 +70,9 @@
>
> #define SCDC_STATUS_FLAGS_1 0x41
>
> +#define SCDC_LN_LTP_01 0x41
> +#define SCDC_LN_LTP_23 0x42
> +
> #define SCDC_ERR_DET_0_L 0x50
> #define SCDC_ERR_DET_0_H 0x51
> #define SCDC_ERR_DET_1_L 0x52
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] amd/dc: add frl bits to the registers
2025-11-14 3:53 ` [PATCH 2/2] amd/dc: add frl bits to the registers Dave Airlie
@ 2025-11-21 14:31 ` Derek Foreman
0 siblings, 0 replies; 4+ messages in thread
From: Derek Foreman @ 2025-11-21 14:31 UTC (permalink / raw)
To: Dave Airlie, dri-devel
On 11/13/25 9:53 PM, Dave Airlie wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> document the same bits as added to the main headers.
>
> Signed-off-by: Dave Airlie <airlied@redhat.com>
> ---
> .../gpu/drm/amd/display/dc/dc_hdmi_types.h | 30 +++++++++++++++++--
> 1 file changed, 28 insertions(+), 2 deletions(-)
Acked-by: Derek Foreman <derek.foreman@collabora.com>
> diff --git a/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h b/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h
> index b015e80672ec..693129b987ac 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h
> @@ -77,11 +77,24 @@ union hdmi_scdc_update_read_data {
> uint8_t STATUS_UPDATE:1;
> uint8_t CED_UPDATE:1;
> uint8_t RR_TEST:1;
> - uint8_t RESERVED:5;
> + uint8_t RESERVED0:1;
> + uint8_t FRL_START:1;
> + uint8_t FLT_UPDATE:1;
> + uint8_t RESERVED:2;
> uint8_t RESERVED2:8;
> } fields;
> };
>
> +union hdmi_scdc_config_data {
> + uint8_t byte[2];
> + struct {
> + uint8_t RR_ENABLE:1;
> + uint8_t RESERVED:7;
> + uint8_t FRL_RATE:4;
> + uint8_t FFE_LEVELS:4;
> + } fields;
> +};
> +
> union hdmi_scdc_status_flags_data {
> uint8_t byte;
> struct {
> @@ -89,7 +102,20 @@ union hdmi_scdc_status_flags_data {
> uint8_t CH0_LOCKED:1;
> uint8_t CH1_LOCKED:1;
> uint8_t CH2_LOCKED:1;
> - uint8_t RESERVED:4;
> + uint8_t LANE3_LOCKED:1;
> + uint8_t RESERVED:1;
> + uint8_t FLT_READY:1;
> + uint8_t RESERVED2:1;
> + } fields;
> +};
> +
> +union hdmi_scdc_lane_status_data {
> + uint8_t byte[2];
> + struct {
> + uint8_t ltp_0:4;
> + uint8_t ltp_1:4;
> + uint8_t ltp_2:4;
> + uint8_t ltp_3:4;
> } fields;
> };
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2025-11-21 14:48 UTC | newest]
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2025-11-14 3:53 [PATCH 1/2] drm/scdc: add frl config/status registers to scdc header Dave Airlie
2025-11-14 3:53 ` [PATCH 2/2] amd/dc: add frl bits to the registers Dave Airlie
2025-11-21 14:31 ` Derek Foreman
2025-11-21 14:31 ` [PATCH 1/2] drm/scdc: add frl config/status registers to scdc header Derek Foreman
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