[PATCH v2 0/7] hw/arm/smmuv3-accel: Resolve AUTO properties

[PATCH v2 0/7] hw/arm/smmuv3-accel: Resolve AUTO properties

[Nathan Chen]

Hi,

This series introduces support for resolving 'auto' for arm-smmuv3
accelerated mode's ATS, RIL, SSIDSIZE, and OAS feature properties based
on host IOMMU capabilities. This is dependent on the series [0] for
changing these property types to accept 'auto' values.

Accelerated SMMUv3 Address Translation Services support is derived from
IDR0, Range Invalidation support is derived from IDR3, Substream ID
size is derived from IDR1, and output address space is derived from
IDR5.

The default values are set to 'auto' for all properties. If accel=off
and the values are set to 'auto' or are omitted and resolve to 'auto',
the default property values defined in smmuv3_init_id_regs() for OAS
and RIL will remain unchanged, while SSIDSIZE and ATS values will
remain initialized at 0.

A complete branch can be found here:
https://github.com/NathanChenNVIDIA/qemu/tree/smmuv3-accel-auto-resolve-v2

Please take a look and let me know your feedback.

Thanks,
Nathan

[0] https://lore.kernel.org/qemu-arm/20260323182454.1416110-1-nathanc@nvidia.com/

Example usage:
qemu-system-aarch64 \
  -object iommufd,id=iommufd0 \
  -machine virt,accel=kvm,gic-version=3,ras=on,highmem-mmio-size=4T \
  -cpu host -smp cpus=4 -m size=16G -nographic \
  -object memory-backend-ram,size=16G,id=m0 \
  -numa node,memdev=m0,cpus=0-3,nodeid=0 \
  -numa node,nodeid=1 -numa node,nodeid=2 -numa node,nodeid=3 -numa node,nodeid=4 \
  -numa node,nodeid=5 -numa node,nodeid=6 -numa node,nodeid=7 -numa node,nodeid=8 \
  -device pxb-pcie,id=pcie.1,bus_nr=1,bus=pcie.0,numa_node=0 \
  -device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1,accel=on,ats=auto,ssidsize=auto,ril=auto,oas=auto \
  -device pcie-root-port,id=pcie.port1,bus=pcie.1,chassis=1,io-reserve=0 \
  -device vfio-pci-nohotplug,host=0009:06:00.0,bus=pcie.port1,rombar=0,id=dev0,iommufd=iommufd0,ats=auto \
  -object acpi-generic-initiator,id=gi0,pci-dev=dev0,node=1 \
  -object acpi-generic-initiator,id=gi1,pci-dev=dev0,node=2 \
  -object acpi-generic-initiator,id=gi2,pci-dev=dev0,node=3 \
  -object acpi-generic-initiator,id=gi3,pci-dev=dev0,node=4 \
  -object acpi-generic-initiator,id=gi4,pci-dev=dev0,node=5 \
  -object acpi-generic-initiator,id=gi5,pci-dev=dev0,node=6 \
  -object acpi-generic-initiator,id=gi6,pci-dev=dev0,node=7 \
  -object acpi-generic-initiator,id=gi7,pci-dev=dev0,node=8 \
  -bios /usr/share/AAVMF/AAVMF_CODE.fd \
  -device nvme,drive=nvme0,serial=deadbeaf1,bus=pcie.0 \
  -drive file=/var/lib/libvirt/images/guest.qcow2,index=0,media=disk,format=qcow2,if=none,id=nvme0 \
  -device e1000,romfile=/usr/local/share/qemu/efi-e1000.rom,netdev=net0,bus=pcie.0 \
  -netdev user,id=net0,hostfwd=tcp::5558-:22,hostfwd=tcp::5586-:5586

Testing:
Basic sanity testing was performed on an NVIDIA Grace platform with GPU
device assignment and running CUDA test apps on the guest. Observed the
feature properties being set based on host IOMMU capabilities.
Verified that the VM boot will fail without a cold-plugged device, and
that a hot-plugged device re-uses the resolved values from the initial
cold-plug. Additional testing and feedback are welcome.

Nathan Chen (7):
  hw/arm/smmuv3-accel: Add helper for resolving auto parameters
  hw/arm/smmuv3-accel: Implement "auto" value for "ats"
  hw/arm/smmuv3-accel: Implement "auto" value for "ril"
  hw/arm/smmuv3-accel: Implement "auto" value for "ssidsize"
  hw/arm/smmuv3-accel: Implement "auto" value for "oas"
  hw/arm/smmuv3: Set default ats, ril, ssidsize, oas to auto
  qemu-options.hx: Support "auto" for accel SMMUv3 properties

 hw/arm/smmuv3-accel.c   | 80 ++++++++++++++++++++++++++++++++++++++++-
 hw/arm/smmuv3-accel.h   |  2 ++
 hw/arm/smmuv3.c         | 63 +++++++++++++++-----------------
 hw/core/machine.c       |  8 +++++
 include/hw/arm/smmuv3.h |  2 ++
 qemu-options.hx         | 33 +++++++++++------
 6 files changed, 143 insertions(+), 45 deletions(-)

-- 
2.43.0

[PATCH v2 1/7] hw/arm/smmuv3-accel: Add helper for resolving auto parameters

[Nathan Chen]

Introduce smmuv3_accel_auto_finalise() to resolve properties that are
set to 'auto' for accelerated SMMUv3. This helper function allows
properties such as ats, ril, ssidsize, and oas support to be resolved
from host IOMMU capabilities via IOMMU_GET_HW_INFO.

The later commits in this series set the auto_mode flag to true when
an accel SMMUv3 property value is explicitly set to 'auto', or if the
property value is not set and defaults to auto mode.

Setting these property values to 'auto' requires at least one
cold-plugged device to retrieve and finalise these properties. If the
auto_mode flag is true, register a machine_init_done notifier to
verify this requirement and fail boot if it is not met.

Hot-plugged devices into an accel SMMUv3-associated bus will re-use
the resolved host values from the initial cold-plug.

Subsequent patches will make use of this helper to resolve 'auto' to
what is reported by host IOMMU capabilities.

Suggested-by: Shameer Kolothum <skolothumtho@nvidia.com>
Signed-off-by: Nathan Chen <nathanc@nvidia.com>
---
 hw/arm/smmuv3-accel.c   | 43 +++++++++++++++++++++++++++++++++++++++++
 hw/arm/smmuv3-accel.h   |  2 ++
 include/hw/arm/smmuv3.h |  2 ++
 3 files changed, 47 insertions(+)

diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
index 65c2f44880..8b3bbf3ef6 100644
--- a/hw/arm/smmuv3-accel.c
+++ b/hw/arm/smmuv3-accel.c
@@ -18,6 +18,7 @@
 
 #include "smmuv3-internal.h"
 #include "smmuv3-accel.h"
+#include "system/system.h"
 
 /*
  * The root region aliases the global system memory, and shared_as_sysmem
@@ -35,11 +36,32 @@ static int smmuv3_oas_bits(uint32_t oas)
     return map[oas];
 }
 
+static void smmuv3_accel_auto_finalise(SMMUv3State *s,
+                                       struct iommu_hw_info_arm_smmuv3 *info) {
+    SMMUv3AccelState *accel = s->s_accel;
+
+    /*
+     * Return if 'auto' was not set for any accel SMMUv3 property, or
+     * if property values were already resolved from a previous call
+     * to this function (e.g. if this function was called again after
+     * VM boot during device hot plug). We do not accept new property
+     * values in this case where auto_finalised == true, and we re-use
+     * the values determined from the initial cold plug.
+     */
+    if (!accel->auto_mode || accel->auto_finalised) {
+        return;
+    }
+
+    accel->auto_finalised = true;
+}
+
 static bool
 smmuv3_accel_check_hw_compatible(SMMUv3State *s,
                                  struct iommu_hw_info_arm_smmuv3 *info,
                                  Error **errp)
 {
+    smmuv3_accel_auto_finalise(s, info);
+
     /* QEMU SMMUv3 supports both linear and 2-level stream tables */
     if (FIELD_EX32(info->idr[0], IDR0, STLEVEL) !=
                 FIELD_EX32(s->idr[0], IDR0, STLEVEL)) {
@@ -917,6 +939,22 @@ static void smmuv3_accel_as_init(SMMUv3State *s)
     address_space_init(shared_as_sysmem, &root, "smmuv3-accel-as-sysmem");
 }
 
+static void smmuv3_machine_done(Notifier *notifier, void *data)
+{
+    SMMUv3State *s = container_of(notifier, SMMUv3State, machine_done);
+    SMMUv3AccelState *accel = s->s_accel;
+
+    if (!s->accel) {
+        return;
+    }
+
+    if (accel->auto_mode && !accel->auto_finalised) {
+        error_report("arm-smmuv3 accel=on with 'auto' properties requires "
+                     "at least one cold-plugged VFIO device");
+        exit(1);
+    }
+}
+
 void smmuv3_accel_init(SMMUv3State *s)
 {
     SMMUState *bs = ARM_SMMU(s);
@@ -924,4 +962,9 @@ void smmuv3_accel_init(SMMUv3State *s)
     s->s_accel = g_new0(SMMUv3AccelState, 1);
     bs->iommu_ops = &smmuv3_accel_ops;
     smmuv3_accel_as_init(s);
+
+    if (s->s_accel->auto_mode) {
+        s->machine_done.notify = smmuv3_machine_done;
+        qemu_add_machine_init_done_notifier(&s->machine_done);
+    }
 }
diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h
index dba6c71de5..3c1cd55714 100644
--- a/hw/arm/smmuv3-accel.h
+++ b/hw/arm/smmuv3-accel.h
@@ -26,6 +26,8 @@ typedef struct SMMUv3AccelState {
     uint32_t bypass_hwpt_id;
     uint32_t abort_hwpt_id;
     QLIST_HEAD(, SMMUv3AccelDevice) device_list;
+    bool auto_mode;
+    bool auto_finalised;
 } SMMUv3AccelState;
 
 typedef struct SMMUS1Hwpt {
diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
index 82f18eb090..fe0493c1aa 100644
--- a/include/hw/arm/smmuv3.h
+++ b/include/hw/arm/smmuv3.h
@@ -74,6 +74,8 @@ struct SMMUv3State {
     OnOffAuto ats;
     OasMode oas;
     SsidSizeMode ssidsize;
+
+    Notifier machine_done;
 };
 
 typedef enum {
-- 
2.43.0

[PATCH v2 2/7] hw/arm/smmuv3-accel: Implement "auto" value for "ats"

[Nathan Chen]

Allow accelerated SMMUv3 Address Translation Services support property
to be derived from host IOMMU capabilities. Derive host values using
IOMMU_GET_HW_INFO, retrieving ATS capability from IDR0.

Signed-off-by: Nathan Chen <nathanc@nvidia.com>
---
 hw/arm/smmuv3-accel.c |  9 +++++++++
 hw/arm/smmuv3.c       | 10 +++-------
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
index 8b3bbf3ef6..b42d189d29 100644
--- a/hw/arm/smmuv3-accel.c
+++ b/hw/arm/smmuv3-accel.c
@@ -52,6 +52,11 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,
         return;
     }
 
+    if (s->ats == ON_OFF_AUTO_AUTO) {
+        s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS,
+                               FIELD_EX32(info->idr[0], IDR0, ATS));
+    }
+
     accel->auto_finalised = true;
 }
 
@@ -963,6 +968,10 @@ void smmuv3_accel_init(SMMUv3State *s)
     bs->iommu_ops = &smmuv3_accel_ops;
     smmuv3_accel_as_init(s);
 
+    if (s->ats == ON_OFF_AUTO_AUTO) {
+        s->s_accel->auto_mode = true;
+    }
+
     if (s->s_accel->auto_mode) {
         s->machine_done.notify = smmuv3_machine_done;
         qemu_add_machine_init_done_notifier(&s->machine_done);
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 7fead1c3cf..5671649fee 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -1972,10 +1972,6 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
     }
 #endif
 
-    if (s->ats == ON_OFF_AUTO_AUTO) {
-        error_setg(errp, "ats auto mode is not supported");
-        return false;
-    }
     if (s->ril == ON_OFF_AUTO_AUTO) {
         error_setg(errp, "ril auto mode is not supported");
         return false;
@@ -2175,9 +2171,9 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)
         "Disable range invalidation support (for accel=on). ril=auto "
         "is not supported.");
     object_class_property_set_description(klass, "ats",
-        "Enable/disable ATS support (for accel=on). Please ensure host "
-        "platform has ATS support before enabling this. ats=auto is not "
-        "supported.");
+        "Enable/disable ATS support (for accel=on). "
+        "Valid values are on, off, and auto. Defaults to off. "
+        "Please ensure host platform supports ATS before enabling.");
     object_class_property_set_description(klass, "oas",
         "Specify Output Address Size (for accel=on). Supported values "
         "are 44 or 48 bits. Defaults to 44 bits. oas=auto is not "
-- 
2.43.0

[PATCH v2 3/7] hw/arm/smmuv3-accel: Implement "auto" value for "ril"

[Nathan Chen]

Allow accelerated SMMUv3 Range Invalidation support property to be
derived from host IOMMU capabilities. Derive host values using
IOMMU_GET_HW_INFO, retrieving RIL capability from IDR3.

Signed-off-by: Nathan Chen <nathanc@nvidia.com>
---
 hw/arm/smmuv3-accel.c |  8 +++++++-
 hw/arm/smmuv3.c       | 10 ++++------
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
index b42d189d29..98c2cdcb5e 100644
--- a/hw/arm/smmuv3-accel.c
+++ b/hw/arm/smmuv3-accel.c
@@ -57,6 +57,11 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,
                                FIELD_EX32(info->idr[0], IDR0, ATS));
     }
 
+    if (s->ril == ON_OFF_AUTO_AUTO) {
+        s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL,
+                               FIELD_EX32(info->idr[3], IDR3, RIL));
+    }
+
     accel->auto_finalised = true;
 }
 
@@ -968,7 +973,8 @@ void smmuv3_accel_init(SMMUv3State *s)
     bs->iommu_ops = &smmuv3_accel_ops;
     smmuv3_accel_as_init(s);
 
-    if (s->ats == ON_OFF_AUTO_AUTO) {
+    if (s->ats == ON_OFF_AUTO_AUTO ||
+        s->ril == ON_OFF_AUTO_AUTO) {
         s->s_accel->auto_mode = true;
     }
 
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 5671649fee..b7aa4122eb 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -1972,10 +1972,6 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
     }
 #endif
 
-    if (s->ril == ON_OFF_AUTO_AUTO) {
-        error_setg(errp, "ril auto mode is not supported");
-        return false;
-    }
     if (s->ssidsize == SSID_SIZE_MODE_AUTO) {
         error_setg(errp, "ssidsize auto mode is not supported");
         return false;
@@ -2168,8 +2164,10 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)
         "Enable SMMUv3 accelerator support. Allows host SMMUv3 to be "
         "configured in nested mode for vfio-pci dev assignment");
     object_class_property_set_description(klass, "ril",
-        "Disable range invalidation support (for accel=on). ril=auto "
-        "is not supported.");
+        "Enable/disable range invalidation support (for accel=on). "
+        "Valid values are on, off, and auto. Defaults to on. "
+        "Please enable if host platform supports RIL, and disable if "
+        "host platform does not support RIL.");
     object_class_property_set_description(klass, "ats",
         "Enable/disable ATS support (for accel=on). "
         "Valid values are on, off, and auto. Defaults to off. "
-- 
2.43.0

[PATCH v2 4/7] hw/arm/smmuv3-accel: Implement "auto" value for "ssidsize"

[Nathan Chen]

Allow accelerated SMMUv3 SSID size property to be derived from host
IOMMU capabilities. Derive host values using IOMMU_GET_HW_INFO,
retrieving SSID size from IDR1. When the auto SSID size is resolved
to a non-zero value, PASID capability is advertised to the vIOMMU
and accelerated use cases such as Shared Virtual Addressing (SVA)
are supported.

Signed-off-by: Nathan Chen <nathanc@nvidia.com>
---
 hw/arm/smmuv3-accel.c | 18 ++++++++++++++++--
 hw/arm/smmuv3.c       | 20 ++++++++++----------
 2 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
index 98c2cdcb5e..d13d15a11d 100644
--- a/hw/arm/smmuv3-accel.c
+++ b/hw/arm/smmuv3-accel.c
@@ -62,6 +62,12 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,
                                FIELD_EX32(info->idr[3], IDR3, RIL));
     }
 
+    if (s->ssidsize == SSID_SIZE_MODE_AUTO) {
+        /* Store for get_viommu_flags() to determine PASID support */
+        s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SSIDSIZE,
+                               FIELD_EX32(info->idr[1], IDR1, SSIDSIZE));
+    }
+
     accel->auto_finalised = true;
 }
 
@@ -822,6 +828,13 @@ static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque,
     }
 }
 
+static inline bool smmuv3_pasid_supported(SMMUv3State *s)
+{
+    return s->ssidsize > SSID_SIZE_MODE_0 ||
+           (s->ssidsize == SSID_SIZE_MODE_AUTO &&
+            FIELD_EX32(s->idr[1], IDR1, SSIDSIZE));
+}
+
 static uint64_t smmuv3_accel_get_viommu_flags(void *opaque)
 {
     /*
@@ -834,7 +847,7 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *opaque)
     SMMUState *bs = opaque;
     SMMUv3State *s = ARM_SMMUV3(bs);
 
-    if (s->ssidsize > SSID_SIZE_MODE_0) {
+    if (smmuv3_pasid_supported(s)) {
         flags |= VIOMMU_FLAG_PASID_SUPPORTED;
     }
     return flags;
@@ -974,7 +987,8 @@ void smmuv3_accel_init(SMMUv3State *s)
     smmuv3_accel_as_init(s);
 
     if (s->ats == ON_OFF_AUTO_AUTO ||
-        s->ril == ON_OFF_AUTO_AUTO) {
+        s->ril == ON_OFF_AUTO_AUTO ||
+        s->ssidsize == SSID_SIZE_MODE_AUTO) {
         s->s_accel->auto_mode = true;
     }
 
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index b7aa4122eb..07025245e2 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -626,7 +626,10 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
     }
 
     /* Multiple context descriptors require SubstreamID support */
-    if (s->ssidsize == SSID_SIZE_MODE_0 && STE_S1CDMAX(ste) != 0) {
+    if ((s->ssidsize == SSID_SIZE_MODE_0 ||
+         (s->ssidsize == SSID_SIZE_MODE_AUTO &&
+          !FIELD_EX32(s->idr[1], IDR1, SSIDSIZE))) &&
+        STE_S1CDMAX(ste) != 0) {
         qemu_log_mask(LOG_UNIMP,
                 "SMMUv3: multiple S1 context descriptors require SubstreamID support. "
                 "Configure ssidsize > 0 (requires accel=on)\n");
@@ -1972,10 +1975,6 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
     }
 #endif
 
-    if (s->ssidsize == SSID_SIZE_MODE_AUTO) {
-        error_setg(errp, "ssidsize auto mode is not supported");
-        return false;
-    }
     if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48) {
         error_setg(errp, "QEMU SMMUv3 model only implements 44 and 48 bit"
                    "OAS; other OasMode values are not supported");
@@ -1996,7 +1995,8 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
             return false;
         }
         if (s->ssidsize > SSID_SIZE_MODE_0) {
-            error_setg(errp, "ssidsize can only be set if accel=on");
+            error_setg(errp, "ssidsize can only be greater than 0 "
+                       "bits if accel=on");
             return false;
         }
         return true;
@@ -2177,11 +2177,11 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)
         "are 44 or 48 bits. Defaults to 44 bits. oas=auto is not "
         "supported.");
     object_class_property_set_description(klass, "ssidsize",
-        "Number of bits used to represent SubstreamIDs (SSIDs). "
+        "Set number of bits used to represent SubstreamIDs (SSIDs). "
+        "Valid values are 0-20 and auto. Defaults to 0. "
         "A value of N allows SSIDs in the range [0 .. 2^N - 1]. "
-        "Valid range is 0-20, where 0 disables SubstreamID support. "
-        "Defaults to 0. A value greater than 0 is required to enable "
-        "PASID support. ssidsize=auto is not supported.");
+        "A value of 0 disables SubstreamID support. A value greater "
+        "than 0 is required to enable PASID support.");
 }
 
 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu,
-- 
2.43.0

[PATCH v2 5/7] hw/arm/smmuv3-accel: Implement "auto" value for "oas"

[Nathan Chen]

Allow accelerated SMMUv3 OAS property to be derived from host IOMMU
capabilities. Derive host values using IOMMU_GET_HW_INFO, retrieving
OAS from IDR5.

This keeps the OAS value advertised by the virtual SMMU compatible with
the capabilities of the host SMMUv3, so that the intermediate physical
addresses (IPA) consumed by host SMMU for stage-2 translation do not
exceed the host's max supported IPA size.

Signed-off-by: Nathan Chen <nathanc@nvidia.com>
---
 hw/arm/smmuv3-accel.c |  8 +++++++-
 hw/arm/smmuv3.c       | 15 ++++++++-------
 2 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
index d13d15a11d..f45e268bde 100644
--- a/hw/arm/smmuv3-accel.c
+++ b/hw/arm/smmuv3-accel.c
@@ -68,6 +68,11 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,
                                FIELD_EX32(info->idr[1], IDR1, SSIDSIZE));
     }
 
+    if (s->oas == OAS_MODE_AUTO) {
+        s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS,
+                               FIELD_EX32(info->idr[5], IDR5, OAS));
+    }
+
     accel->auto_finalised = true;
 }
 
@@ -988,7 +993,8 @@ void smmuv3_accel_init(SMMUv3State *s)
 
     if (s->ats == ON_OFF_AUTO_AUTO ||
         s->ril == ON_OFF_AUTO_AUTO ||
-        s->ssidsize == SSID_SIZE_MODE_AUTO) {
+        s->ssidsize == SSID_SIZE_MODE_AUTO ||
+        s->oas == OAS_MODE_AUTO) {
         s->s_accel->auto_mode = true;
     }
 
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 07025245e2..39a6f72938 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -1975,9 +1975,11 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
     }
 #endif
 
-    if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48) {
-        error_setg(errp, "QEMU SMMUv3 model only implements 44 and 48 bit"
-                   "OAS; other OasMode values are not supported");
+    if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48 &&
+        s->oas != OAS_MODE_AUTO) {
+        error_setg(errp, "QEMU SMMUv3 model only implements auto, "
+                   "44 bit, or 48 bit OAS. Other OasMode values are "
+                   "not supported.");
         return false;
     }
 
@@ -1991,7 +1993,7 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
             return false;
         }
         if (s->oas > OAS_MODE_44) {
-            error_setg(errp, "OAS must be 44 bits when accel=off");
+            error_setg(errp, "oas must be 44 bits when accel=off");
             return false;
         }
         if (s->ssidsize > SSID_SIZE_MODE_0) {
@@ -2173,9 +2175,8 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)
         "Valid values are on, off, and auto. Defaults to off. "
         "Please ensure host platform supports ATS before enabling.");
     object_class_property_set_description(klass, "oas",
-        "Specify Output Address Size (for accel=on). Supported values "
-        "are 44 or 48 bits. Defaults to 44 bits. oas=auto is not "
-        "supported.");
+        "Set Output Address Size in bits (for accel=on). "
+        "Valid values are 44, 48, and auto. Defaults to 44 bits.");
     object_class_property_set_description(klass, "ssidsize",
         "Set number of bits used to represent SubstreamIDs (SSIDs). "
         "Valid values are 0-20 and auto. Defaults to 0. "
-- 
2.43.0

[PATCH v2 6/7] hw/arm/smmuv3: Set default ats, ril, ssidsize, oas to auto

[Nathan Chen]

Set the default value of ATS, RIL, SSIDSIZE, and OAS to auto, in order
to match the host IOMMU properties when accel=on.

If accel=off and these property values are set to auto, the default
property values defined in smmuv3_init_id_regs() for OAS and RIL will
remain unchanged, while SSIDSIZE and ATS values will remain initialized
at 0.

Introduce a new compat for the changed defaults.

Signed-off-by: Nathan Chen <nathanc@nvidia.com>
---
 hw/arm/smmuv3.c   | 14 +++++++-------
 hw/core/machine.c |  8 ++++++++
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 39a6f72938..e8ca6be34a 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -2135,11 +2135,11 @@ static const Property smmuv3_properties[] = {
     /* GPA of MSI doorbell, for SMMUv3 accel use. */
     DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0),
     /* RIL can be turned off for accel cases */
-    DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON),
-    DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF),
-    DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_44),
+    DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_AUTO),
+    DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_AUTO),
+    DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_AUTO),
     DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize,
-                              SSID_SIZE_MODE_0),
+                              SSID_SIZE_MODE_AUTO),
 };
 
 static void smmuv3_instance_init(Object *obj)
@@ -2167,7 +2167,7 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)
         "configured in nested mode for vfio-pci dev assignment");
     object_class_property_set_description(klass, "ril",
         "Enable/disable range invalidation support (for accel=on). "
-        "Valid values are on, off, and auto. Defaults to on. "
+        "Valid values are on, off, and auto. Defaults to auto. "
         "Please enable if host platform supports RIL, and disable if "
         "host platform does not support RIL.");
     object_class_property_set_description(klass, "ats",
@@ -2176,10 +2176,10 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)
         "Please ensure host platform supports ATS before enabling.");
     object_class_property_set_description(klass, "oas",
         "Set Output Address Size in bits (for accel=on). "
-        "Valid values are 44, 48, and auto. Defaults to 44 bits.");
+        "Valid values are 44, 48, and auto. Defaults to auto.");
     object_class_property_set_description(klass, "ssidsize",
         "Set number of bits used to represent SubstreamIDs (SSIDs). "
-        "Valid values are 0-20 and auto. Defaults to 0. "
+        "Valid values are 0-20 and auto. Defaults to auto. "
         "A value of N allows SSIDs in the range [0 .. 2^N - 1]. "
         "A value of 0 disables SubstreamID support. A value greater "
         "than 0 is required to enable PASID support.");
diff --git a/hw/core/machine.c b/hw/core/machine.c
index 0aa77a57e9..a668bb2ec3 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -37,6 +37,14 @@
 #include "hw/virtio/virtio-iommu.h"
 #include "hw/acpi/generic_event_device.h"
 #include "qemu/audio.h"
+#include "hw/arm/smmuv3.h"
+
+GlobalProperty hw_compat_11_0[] = {
+    { TYPE_ARM_SMMUV3, "ats", "off" },
+    { TYPE_ARM_SMMUV3, "ril", "on" },
+    { TYPE_ARM_SMMUV3, "ssidsize", "0" },
+    { TYPE_ARM_SMMUV3, "oas", "44" },
+};
 
 GlobalProperty hw_compat_10_2[] = {
     { "scsi-block", "migrate-pr", "off" },
-- 
2.43.0

[PATCH v2 7/7] qemu-options.hx: Support "auto" for accel SMMUv3 properties

[Nathan Chen]

Update documentation now that "auto" is supported for accelerated SMMUv3
properties.

Signed-off-by: Nathan Chen <nathanc@nvidia.com>
---
 qemu-options.hx | 33 +++++++++++++++++++++++----------
 1 file changed, 23 insertions(+), 10 deletions(-)

diff --git a/qemu-options.hx b/qemu-options.hx
index 21972f8326..2c6ba16a26 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1291,30 +1291,43 @@ SRST
         Enabling accel configures the host SMMUv3 in nested mode to support
         vfio-pci passthrough.
 
-     The following options are available when accel=on.
-     Note: 'auto' mode is not currently supported.
-
-    ``ril=on|off`` (default: on)
+     The following options will be set to auto by default if not manually
+     set. When accel=on and these properties are set to auto, the value is
+     derived from the host SMMUv3 capabilities via IOMMU_GET_HW_INFO. With
+     accel=on, this requires at least one cold-plugged vfio-pci device; if
+     none is present at machine init, QEMU will abort.
+
+     If accel=off and these property values are set to auto, the values will
+     not be derived from the host SMMUv3 capabilities. Instead, they will
+     resolve to the defaults described below, and a cold-plugged vfio-pci
+     device is not required.
+
+    ``ril=on|off`` (default: auto)
         Support for Range Invalidation, which allows the SMMUv3 driver to
         invalidate TLB entries for a range of IOVAs at once instead of issuing
         separate commands to invalidate each page. Must match with host SMMUv3
-        Range Invalidation support.
+        Range Invalidation support. If accel=off and ril is set to auto, this
+        property value will resolve to on.
 
-    ``ats=on|off`` (default: off)
+    ``ats=on|off`` (default: auto)
         Support for Address Translation Services, which enables PCIe devices to
         cache address translations in their local TLB and reduce latency. Host
         SMMUv3 must support ATS in order to enable this feature for the vIOMMU.
+        If accel=off and ats is set to auto, the property value will resolve to
+        off.
 
-    ``oas=val`` (supported values are 44 and 48. default: 44)
+    ``oas=val`` (supported values are 44 and 48. default: auto)
         Sets the Output Address Size in bits. The value set here must be less
         than or equal to the host SMMUv3's supported OAS, so that the
         intermediate physical addresses (IPA) consumed by host SMMU for stage-2
-        translation do not exceed the host's max supported IPA size.
+        translation do not exceed the host's max supported IPA size. If
+        accel=off and oas is set to auto, the property value will resolve to 44.
 
-    ``ssidsize=val`` (val between 0 and 20. default: 0)
+    ``ssidsize=val`` (val between 0 and 20. default: auto)
         Sets the Substream ID size in bits. When set to a non-zero value,
         PASID capability is advertised to the vIOMMU and accelerated use cases
-        such as Shared Virtual Addressing (SVA) are supported.
+        such as Shared Virtual Addressing (SVA) are supported. If accel=off
+        and ssidsize is set to auto, the property value will resolve to 0.
 
 ``-device amd-iommu[,option=...]``
     Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU).
-- 
2.43.0

Re: [PATCH v2 0/7] hw/arm/smmuv3-accel: Resolve AUTO properties

[Cédric Le Goater]

Hello Nathan,

On 4/22/26 22:43, Nathan Chen wrote:
> Hi,
> 
> This series introduces support for resolving 'auto' for arm-smmuv3
> accelerated mode's ATS, RIL, SSIDSIZE, and OAS feature properties based
> on host IOMMU capabilities. This is dependent on the series [0] for
> changing these property types to accept 'auto' values.
> 
> Accelerated SMMUv3 Address Translation Services support is derived from
> IDR0, Range Invalidation support is derived from IDR3, Substream ID
> size is derived from IDR1, and output address space is derived from
> IDR5.
> 
> The default values are set to 'auto' for all properties. If accel=off
> and the values are set to 'auto' or are omitted and resolve to 'auto',
> the default property values defined in smmuv3_init_id_regs() for OAS
> and RIL will remain unchanged, while SSIDSIZE and ATS values will
> remain initialized at 0.
> 
> A complete branch can be found here:
> https://github.com/NathanChenNVIDIA/qemu/tree/smmuv3-accel-auto-resolve-v2
> 
> Please take a look and let me know your feedback.
> 
> Thanks,
> Nathan
> 
> [0] https://lore.kernel.org/qemu-arm/20260323182454.1416110-1-nathanc@nvidia.com/
> 
> Example usage:
> qemu-system-aarch64 \
>    -object iommufd,id=iommufd0 \
>    -machine virt,accel=kvm,gic-version=3,ras=on,highmem-mmio-size=4T \
>    -cpu host -smp cpus=4 -m size=16G -nographic \
>    -object memory-backend-ram,size=16G,id=m0 \
>    -numa node,memdev=m0,cpus=0-3,nodeid=0 \
>    -numa node,nodeid=1 -numa node,nodeid=2 -numa node,nodeid=3 -numa node,nodeid=4 \
>    -numa node,nodeid=5 -numa node,nodeid=6 -numa node,nodeid=7 -numa node,nodeid=8 \
>    -device pxb-pcie,id=pcie.1,bus_nr=1,bus=pcie.0,numa_node=0 \
>    -device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.1,accel=on,ats=auto,ssidsize=auto,ril=auto,oas=auto \
>    -device pcie-root-port,id=pcie.port1,bus=pcie.1,chassis=1,io-reserve=0 \
>    -device vfio-pci-nohotplug,host=0009:06:00.0,bus=pcie.port1,rombar=0,id=dev0,iommufd=iommufd0,ats=auto \
>    -object acpi-generic-initiator,id=gi0,pci-dev=dev0,node=1 \
>    -object acpi-generic-initiator,id=gi1,pci-dev=dev0,node=2 \
>    -object acpi-generic-initiator,id=gi2,pci-dev=dev0,node=3 \
>    -object acpi-generic-initiator,id=gi3,pci-dev=dev0,node=4 \
>    -object acpi-generic-initiator,id=gi4,pci-dev=dev0,node=5 \
>    -object acpi-generic-initiator,id=gi5,pci-dev=dev0,node=6 \
>    -object acpi-generic-initiator,id=gi6,pci-dev=dev0,node=7 \
>    -object acpi-generic-initiator,id=gi7,pci-dev=dev0,node=8 \
>    -bios /usr/share/AAVMF/AAVMF_CODE.fd \
>    -device nvme,drive=nvme0,serial=deadbeaf1,bus=pcie.0 \
>    -drive file=/var/lib/libvirt/images/guest.qcow2,index=0,media=disk,format=qcow2,if=none,id=nvme0 \
>    -device e1000,romfile=/usr/local/share/qemu/efi-e1000.rom,netdev=net0,bus=pcie.0 \
>    -netdev user,id=net0,hostfwd=tcp::5558-:22,hostfwd=tcp::5586-:5586
> 
> Testing:
> Basic sanity testing was performed on an NVIDIA Grace platform with GPU
> device assignment and running CUDA test apps on the guest. Observed the
> feature properties being set based on host IOMMU capabilities.
> Verified that the VM boot will fail without a cold-plugged device, and
> that a hot-plugged device re-uses the resolved values from the initial
> cold-plug. Additional testing and feedback are welcome.

It is helpful to have a changelog between different versions of
the same series of patches.

So, the linux headers and vfio update are not required anymore ?

Thanks,

C.


> 
> Nathan Chen (7):
>    hw/arm/smmuv3-accel: Add helper for resolving auto parameters
>    hw/arm/smmuv3-accel: Implement "auto" value for "ats"
>    hw/arm/smmuv3-accel: Implement "auto" value for "ril"
>    hw/arm/smmuv3-accel: Implement "auto" value for "ssidsize"
>    hw/arm/smmuv3-accel: Implement "auto" value for "oas"
>    hw/arm/smmuv3: Set default ats, ril, ssidsize, oas to auto
>    qemu-options.hx: Support "auto" for accel SMMUv3 properties
> 
>   hw/arm/smmuv3-accel.c   | 80 ++++++++++++++++++++++++++++++++++++++++-
>   hw/arm/smmuv3-accel.h   |  2 ++
>   hw/arm/smmuv3.c         | 63 +++++++++++++++-----------------
>   hw/core/machine.c       |  8 +++++
>   include/hw/arm/smmuv3.h |  2 ++
>   qemu-options.hx         | 33 +++++++++++------
>   6 files changed, 143 insertions(+), 45 deletions(-)
> 

RE: [PATCH v2 0/7] hw/arm/smmuv3-accel: Resolve AUTO properties

[Shameer Kolothum Thodi]

Hi Cédric,

> -----Original Message-----
> From: Cédric Le Goater <clg@redhat.com>
> Sent: 04 May 2026 15:58
> To: Nathan Chen <nathanc@nvidia.com>; qemu-arm@nongnu.org; qemu-
> devel@nongnu.org
> Cc: Eric Auger <eric.auger@redhat.com>; Peter Maydell
> <peter.maydell@linaro.org>; Marcel Apfelbaum
> <marcel.apfelbaum@gmail.com>; Philippe Mathieu-Daudé
> <philmd@linaro.org>; Yanan Wang <wangyanan55@huawei.com>; Zhao Liu
> <zhao1.liu@intel.com>; Shameer Kolothum Thodi
> <skolothumtho@nvidia.com>; Matt Ochs <mochs@nvidia.com>; Nicolin Chen
> <nicolinc@nvidia.com>
> Subject: Re: [PATCH v2 0/7] hw/arm/smmuv3-accel: Resolve AUTO properties
> 
> External email: Use caution opening links or attachments
> 
> 
> Hello Nathan,
> 
> On 4/22/26 22:43, Nathan Chen wrote:
> > Hi,
> >
> > This series introduces support for resolving 'auto' for arm-smmuv3
> > accelerated mode's ATS, RIL, SSIDSIZE, and OAS feature properties
> > based on host IOMMU capabilities. This is dependent on the series [0]
> > for changing these property types to accept 'auto' values.
> >
> > Accelerated SMMUv3 Address Translation Services support is derived
> > from IDR0, Range Invalidation support is derived from IDR3, Substream
> > ID size is derived from IDR1, and output address space is derived from
> > IDR5.
> >
> > The default values are set to 'auto' for all properties. If accel=off
> > and the values are set to 'auto' or are omitted and resolve to 'auto',
> > the default property values defined in smmuv3_init_id_regs() for OAS
> > and RIL will remain unchanged, while SSIDSIZE and ATS values will
> > remain initialized at 0.
> >
> > A complete branch can be found here:
> > https://github.com/NathanChenNVIDIA/qemu/tree/smmuv3-accel-auto-
> resolv
> > e-v2
> >
> > Please take a look and let me know your feedback.
> >
> > Thanks,
> > Nathan
> >
> > [0]
> > https://lore.kernel.org/qemu-arm/20260323182454.1416110-1-
> nathanc@nvid
> > ia.com/
> >
> > Example usage:
> > qemu-system-aarch64 \
> >    -object iommufd,id=iommufd0 \
> >    -machine virt,accel=kvm,gic-version=3,ras=on,highmem-mmio-size=4T \
> >    -cpu host -smp cpus=4 -m size=16G -nographic \
> >    -object memory-backend-ram,size=16G,id=m0 \
> >    -numa node,memdev=m0,cpus=0-3,nodeid=0 \
> >    -numa node,nodeid=1 -numa node,nodeid=2 -numa node,nodeid=3 -
> numa node,nodeid=4 \
> >    -numa node,nodeid=5 -numa node,nodeid=6 -numa node,nodeid=7 -
> numa node,nodeid=8 \
> >    -device pxb-pcie,id=pcie.1,bus_nr=1,bus=pcie.0,numa_node=0 \
> >    -device arm-smmuv3,primary-
> bus=pcie.1,id=smmuv3.1,accel=on,ats=auto,ssidsize=auto,ril=auto,oas=auto \
> >    -device pcie-root-port,id=pcie.port1,bus=pcie.1,chassis=1,io-reserve=0 \
> >    -device vfio-pci-
> nohotplug,host=0009:06:00.0,bus=pcie.port1,rombar=0,id=dev0,iommufd=i
> ommufd0,ats=auto \
> >    -object acpi-generic-initiator,id=gi0,pci-dev=dev0,node=1 \
> >    -object acpi-generic-initiator,id=gi1,pci-dev=dev0,node=2 \
> >    -object acpi-generic-initiator,id=gi2,pci-dev=dev0,node=3 \
> >    -object acpi-generic-initiator,id=gi3,pci-dev=dev0,node=4 \
> >    -object acpi-generic-initiator,id=gi4,pci-dev=dev0,node=5 \
> >    -object acpi-generic-initiator,id=gi5,pci-dev=dev0,node=6 \
> >    -object acpi-generic-initiator,id=gi6,pci-dev=dev0,node=7 \
> >    -object acpi-generic-initiator,id=gi7,pci-dev=dev0,node=8 \
> >    -bios /usr/share/AAVMF/AAVMF_CODE.fd \
> >    -device nvme,drive=nvme0,serial=deadbeaf1,bus=pcie.0 \
> >    -drive
> file=/var/lib/libvirt/images/guest.qcow2,index=0,media=disk,format=qcow2,if
> =none,id=nvme0 \
> >    -device e1000,romfile=/usr/local/share/qemu/efi-
> e1000.rom,netdev=net0,bus=pcie.0 \
> >    -netdev user,id=net0,hostfwd=tcp::5558-:22,hostfwd=tcp::5586-:5586
> >
> > Testing:
> > Basic sanity testing was performed on an NVIDIA Grace platform with
> > GPU device assignment and running CUDA test apps on the guest.
> > Observed the feature properties being set based on host IOMMU
> capabilities.
> > Verified that the VM boot will fail without a cold-plugged device, and
> > that a hot-plugged device re-uses the resolved values from the initial
> > cold-plug. Additional testing and feedback are welcome.
> 
> It is helpful to have a changelog between different versions of the same series
> of patches.
> 
> So, the linux headers and vfio update are not required anymore ?

Just jumping in as Nathan is on PTO.

My understanding is that the Linux headers and VFIO updates are not
included in this series because, based on previous feedback, the
ATS related VFIO changes will be sent as an independent series.

Thanks,
Shameer

Re: [PATCH v2 0/7] hw/arm/smmuv3-accel: Resolve AUTO properties

[Cédric Le Goater]

Hello Shameer,

On 5/5/26 09:59, Shameer Kolothum Thodi wrote:
> Hi Cédric,
> 
>> -----Original Message-----
>> From: Cédric Le Goater <clg@redhat.com>
>> Sent: 04 May 2026 15:58
>> To: Nathan Chen <nathanc@nvidia.com>; qemu-arm@nongnu.org; qemu-
>> devel@nongnu.org
>> Cc: Eric Auger <eric.auger@redhat.com>; Peter Maydell
>> <peter.maydell@linaro.org>; Marcel Apfelbaum
>> <marcel.apfelbaum@gmail.com>; Philippe Mathieu-Daudé
>> <philmd@linaro.org>; Yanan Wang <wangyanan55@huawei.com>; Zhao Liu
>> <zhao1.liu@intel.com>; Shameer Kolothum Thodi
>> <skolothumtho@nvidia.com>; Matt Ochs <mochs@nvidia.com>; Nicolin Chen
>> <nicolinc@nvidia.com>
>> Subject: Re: [PATCH v2 0/7] hw/arm/smmuv3-accel: Resolve AUTO properties
>>
>> External email: Use caution opening links or attachments
>>
>>
>> Hello Nathan,
>>
>> On 4/22/26 22:43, Nathan Chen wrote:
>>> Hi,
>>>
>>> This series introduces support for resolving 'auto' for arm-smmuv3
>>> accelerated mode's ATS, RIL, SSIDSIZE, and OAS feature properties
>>> based on host IOMMU capabilities. This is dependent on the series [0]
>>> for changing these property types to accept 'auto' values.
>>>
>>> Accelerated SMMUv3 Address Translation Services support is derived
>>> from IDR0, Range Invalidation support is derived from IDR3, Substream
>>> ID size is derived from IDR1, and output address space is derived from
>>> IDR5.
>>>
>>> The default values are set to 'auto' for all properties. If accel=off
>>> and the values are set to 'auto' or are omitted and resolve to 'auto',
>>> the default property values defined in smmuv3_init_id_regs() for OAS
>>> and RIL will remain unchanged, while SSIDSIZE and ATS values will
>>> remain initialized at 0.
>>>
>>> A complete branch can be found here:
>>> https://github.com/NathanChenNVIDIA/qemu/tree/smmuv3-accel-auto-
>> resolv
>>> e-v2
>>>
>>> Please take a look and let me know your feedback.
>>>
>>> Thanks,
>>> Nathan
>>>
>>> [0]
>>> https://lore.kernel.org/qemu-arm/20260323182454.1416110-1-
>> nathanc@nvid
>>> ia.com/
>>>
>>> Example usage:
>>> qemu-system-aarch64 \
>>>     -object iommufd,id=iommufd0 \
>>>     -machine virt,accel=kvm,gic-version=3,ras=on,highmem-mmio-size=4T \
>>>     -cpu host -smp cpus=4 -m size=16G -nographic \
>>>     -object memory-backend-ram,size=16G,id=m0 \
>>>     -numa node,memdev=m0,cpus=0-3,nodeid=0 \
>>>     -numa node,nodeid=1 -numa node,nodeid=2 -numa node,nodeid=3 -
>> numa node,nodeid=4 \
>>>     -numa node,nodeid=5 -numa node,nodeid=6 -numa node,nodeid=7 -
>> numa node,nodeid=8 \
>>>     -device pxb-pcie,id=pcie.1,bus_nr=1,bus=pcie.0,numa_node=0 \
>>>     -device arm-smmuv3,primary-
>> bus=pcie.1,id=smmuv3.1,accel=on,ats=auto,ssidsize=auto,ril=auto,oas=auto \
>>>     -device pcie-root-port,id=pcie.port1,bus=pcie.1,chassis=1,io-reserve=0 \
>>>     -device vfio-pci-
>> nohotplug,host=0009:06:00.0,bus=pcie.port1,rombar=0,id=dev0,iommufd=i
>> ommufd0,ats=auto \
>>>     -object acpi-generic-initiator,id=gi0,pci-dev=dev0,node=1 \
>>>     -object acpi-generic-initiator,id=gi1,pci-dev=dev0,node=2 \
>>>     -object acpi-generic-initiator,id=gi2,pci-dev=dev0,node=3 \
>>>     -object acpi-generic-initiator,id=gi3,pci-dev=dev0,node=4 \
>>>     -object acpi-generic-initiator,id=gi4,pci-dev=dev0,node=5 \
>>>     -object acpi-generic-initiator,id=gi5,pci-dev=dev0,node=6 \
>>>     -object acpi-generic-initiator,id=gi6,pci-dev=dev0,node=7 \
>>>     -object acpi-generic-initiator,id=gi7,pci-dev=dev0,node=8 \
>>>     -bios /usr/share/AAVMF/AAVMF_CODE.fd \
>>>     -device nvme,drive=nvme0,serial=deadbeaf1,bus=pcie.0 \
>>>     -drive
>> file=/var/lib/libvirt/images/guest.qcow2,index=0,media=disk,format=qcow2,if
>> =none,id=nvme0 \
>>>     -device e1000,romfile=/usr/local/share/qemu/efi-
>> e1000.rom,netdev=net0,bus=pcie.0 \
>>>     -netdev user,id=net0,hostfwd=tcp::5558-:22,hostfwd=tcp::5586-:5586
>>>
>>> Testing:
>>> Basic sanity testing was performed on an NVIDIA Grace platform with
>>> GPU device assignment and running CUDA test apps on the guest.
>>> Observed the feature properties being set based on host IOMMU
>> capabilities.
>>> Verified that the VM boot will fail without a cold-plugged device, and
>>> that a hot-plugged device re-uses the resolved values from the initial
>>> cold-plug. Additional testing and feedback are welcome.
>>
>> It is helpful to have a changelog between different versions of the same series
>> of patches.
>>
>> So, the linux headers and vfio update are not required anymore ?
> 
> Just jumping in as Nathan is on PTO.
> 
> My understanding is that the Linux headers and VFIO updates are not
> included in this series because, based on previous feedback, the
> ATS related VFIO changes will be sent as an independent series.

OK.

The linux headers update is handled here :

   https://lore.kernel.org/qemu-devel/20260427070029.1059386-1-gaosong@loongson.cn/

We should help Song Gao.


The VFIO part adding an ats property :

   https://lore.kernel.org/qemu-devel/20260401010231.4166776-5-nathanc@nvidia.com/

will need an update.

Thanks,

C.

Re: [PATCH v2 1/7] hw/arm/smmuv3-accel: Add helper for resolving auto parameters

[Eric Auger]

Hi Nathan,

On 4/22/26 10:43 PM, Nathan Chen wrote:
> Introduce smmuv3_accel_auto_finalise() to resolve properties that are
> set to 'auto' for accelerated SMMUv3. This helper function allows
> properties such as ats, ril, ssidsize, and oas support to be resolved
> from host IOMMU capabilities via IOMMU_GET_HW_INFO.
>
> The later commits in this series set the auto_mode flag to true when
> an accel SMMUv3 property value is explicitly set to 'auto', or if the
> property value is not set and defaults to auto mode.
>
> Setting these property values to 'auto' requires at least one
> cold-plugged device to retrieve and finalise these properties. If the
> auto_mode flag is true, register a machine_init_done notifier to
> verify this requirement and fail boot if it is not met.
>
> Hot-plugged devices into an accel SMMUv3-associated bus will re-use
> the resolved host values from the initial cold-plug.
>
> Subsequent patches will make use of this helper to resolve 'auto' to
> what is reported by host IOMMU capabilities.
>
> Suggested-by: Shameer Kolothum <skolothumtho@nvidia.com>
> Signed-off-by: Nathan Chen <nathanc@nvidia.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>

Eric
> ---
>  hw/arm/smmuv3-accel.c   | 43 +++++++++++++++++++++++++++++++++++++++++
>  hw/arm/smmuv3-accel.h   |  2 ++
>  include/hw/arm/smmuv3.h |  2 ++
>  3 files changed, 47 insertions(+)
>
> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
> index 65c2f44880..8b3bbf3ef6 100644
> --- a/hw/arm/smmuv3-accel.c
> +++ b/hw/arm/smmuv3-accel.c
> @@ -18,6 +18,7 @@
>  
>  #include "smmuv3-internal.h"
>  #include "smmuv3-accel.h"
> +#include "system/system.h"
>  
>  /*
>   * The root region aliases the global system memory, and shared_as_sysmem
> @@ -35,11 +36,32 @@ static int smmuv3_oas_bits(uint32_t oas)
>      return map[oas];
>  }
>  
> +static void smmuv3_accel_auto_finalise(SMMUv3State *s,
> +                                       struct iommu_hw_info_arm_smmuv3 *info) {
> +    SMMUv3AccelState *accel = s->s_accel;
> +
> +    /*
> +     * Return if 'auto' was not set for any accel SMMUv3 property, or
> +     * if property values were already resolved from a previous call
> +     * to this function (e.g. if this function was called again after
> +     * VM boot during device hot plug). We do not accept new property
> +     * values in this case where auto_finalised == true, and we re-use
> +     * the values determined from the initial cold plug.
> +     */
> +    if (!accel->auto_mode || accel->auto_finalised) {
> +        return;
> +    }
> +
> +    accel->auto_finalised = true;
> +}
> +
>  static bool
>  smmuv3_accel_check_hw_compatible(SMMUv3State *s,
>                                   struct iommu_hw_info_arm_smmuv3 *info,
>                                   Error **errp)
>  {
> +    smmuv3_accel_auto_finalise(s, info);
> +
>      /* QEMU SMMUv3 supports both linear and 2-level stream tables */
>      if (FIELD_EX32(info->idr[0], IDR0, STLEVEL) !=
>                  FIELD_EX32(s->idr[0], IDR0, STLEVEL)) {
> @@ -917,6 +939,22 @@ static void smmuv3_accel_as_init(SMMUv3State *s)
>      address_space_init(shared_as_sysmem, &root, "smmuv3-accel-as-sysmem");
>  }
>  
> +static void smmuv3_machine_done(Notifier *notifier, void *data)
> +{
> +    SMMUv3State *s = container_of(notifier, SMMUv3State, machine_done);
> +    SMMUv3AccelState *accel = s->s_accel;
> +
> +    if (!s->accel) {
> +        return;
> +    }
> +
> +    if (accel->auto_mode && !accel->auto_finalised) {
> +        error_report("arm-smmuv3 accel=on with 'auto' properties requires "
> +                     "at least one cold-plugged VFIO device");
> +        exit(1);
> +    }
> +}
> +
>  void smmuv3_accel_init(SMMUv3State *s)
>  {
>      SMMUState *bs = ARM_SMMU(s);
> @@ -924,4 +962,9 @@ void smmuv3_accel_init(SMMUv3State *s)
>      s->s_accel = g_new0(SMMUv3AccelState, 1);
>      bs->iommu_ops = &smmuv3_accel_ops;
>      smmuv3_accel_as_init(s);
> +
> +    if (s->s_accel->auto_mode) {
> +        s->machine_done.notify = smmuv3_machine_done;
> +        qemu_add_machine_init_done_notifier(&s->machine_done);
> +    }
>  }
> diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h
> index dba6c71de5..3c1cd55714 100644
> --- a/hw/arm/smmuv3-accel.h
> +++ b/hw/arm/smmuv3-accel.h
> @@ -26,6 +26,8 @@ typedef struct SMMUv3AccelState {
>      uint32_t bypass_hwpt_id;
>      uint32_t abort_hwpt_id;
>      QLIST_HEAD(, SMMUv3AccelDevice) device_list;
> +    bool auto_mode;
> +    bool auto_finalised;
>  } SMMUv3AccelState;
>  
>  typedef struct SMMUS1Hwpt {
> diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h
> index 82f18eb090..fe0493c1aa 100644
> --- a/include/hw/arm/smmuv3.h
> +++ b/include/hw/arm/smmuv3.h
> @@ -74,6 +74,8 @@ struct SMMUv3State {
>      OnOffAuto ats;
>      OasMode oas;
>      SsidSizeMode ssidsize;
> +
> +    Notifier machine_done;
>  };
>  
>  typedef enum {

Re: [PATCH v2 2/7] hw/arm/smmuv3-accel: Implement "auto" value for "ats"

[Eric Auger]

Hi Nathan,

On 4/22/26 10:43 PM, Nathan Chen wrote:
> Allow accelerated SMMUv3 Address Translation Services support property
> to be derived from host IOMMU capabilities. Derive host values using
> IOMMU_GET_HW_INFO, retrieving ATS capability from IDR0.
>
> Signed-off-by: Nathan Chen <nathanc@nvidia.com>
> ---
>  hw/arm/smmuv3-accel.c |  9 +++++++++
>  hw/arm/smmuv3.c       | 10 +++-------
>  2 files changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
> index 8b3bbf3ef6..b42d189d29 100644
> --- a/hw/arm/smmuv3-accel.c
> +++ b/hw/arm/smmuv3-accel.c
> @@ -52,6 +52,11 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,
>          return;
>      }
>  
> +    if (s->ats == ON_OFF_AUTO_AUTO) {
> +        s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS,
> +                               FIELD_EX32(info->idr[0], IDR0, ATS));
> +    }
> +
>      accel->auto_finalised = true;
>  }
>  
> @@ -963,6 +968,10 @@ void smmuv3_accel_init(SMMUv3State *s)
>      bs->iommu_ops = &smmuv3_accel_ops;
>      smmuv3_accel_as_init(s);
>  
> +    if (s->ats == ON_OFF_AUTO_AUTO) {
> +        s->s_accel->auto_mode = true;
> +    }
> +
>      if (s->s_accel->auto_mode) {
>          s->machine_done.notify = smmuv3_machine_done;
>          qemu_add_machine_init_done_notifier(&s->machine_done);
> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
> index 7fead1c3cf..5671649fee 100644
> --- a/hw/arm/smmuv3.c
> +++ b/hw/arm/smmuv3.c
> @@ -1972,10 +1972,6 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
>      }
>  #endif
>  
> -    if (s->ats == ON_OFF_AUTO_AUTO) {
> -        error_setg(errp, "ats auto mode is not supported");
> -        return false;
> -    }
>      if (s->ril == ON_OFF_AUTO_AUTO) {
>          error_setg(errp, "ril auto mode is not supported");
>          return false;
> @@ -2175,9 +2171,9 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)
>          "Disable range invalidation support (for accel=on). ril=auto "
>          "is not supported.");
>      object_class_property_set_description(klass, "ats",
> -        "Enable/disable ATS support (for accel=on). Please ensure host "
> -        "platform has ATS support before enabling this. ats=auto is not "
> -        "supported.");
> +        "Enable/disable ATS support (for accel=on). "
> +        "Valid values are on, off, and auto. Defaults to off. "
> +        "Please ensure host platform supports ATS before enabling.");
I would rather be more explicit.

s/before enabling/before setting it to 'on'.
>      object_class_property_set_description(klass, "oas",
>          "Specify Output Address Size (for accel=on). Supported values "
>          "are 44 or 48 bits. Defaults to 44 bits. oas=auto is not "
Otherwise
Reviewed-by: Eric Auger <eric.auger@redhat.com>

Eric

Re: [PATCH v2 3/7] hw/arm/smmuv3-accel: Implement "auto" value for "ril"

[Eric Auger]

On 4/22/26 10:43 PM, Nathan Chen wrote:
> Allow accelerated SMMUv3 Range Invalidation support property to be
> derived from host IOMMU capabilities. Derive host values using
> IOMMU_GET_HW_INFO, retrieving RIL capability from IDR3.
>
> Signed-off-by: Nathan Chen <nathanc@nvidia.com>

> ---
>  hw/arm/smmuv3-accel.c |  8 +++++++-
>  hw/arm/smmuv3.c       | 10 ++++------
>  2 files changed, 11 insertions(+), 7 deletions(-)
>
> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
> index b42d189d29..98c2cdcb5e 100644
> --- a/hw/arm/smmuv3-accel.c
> +++ b/hw/arm/smmuv3-accel.c
> @@ -57,6 +57,11 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,
>                                 FIELD_EX32(info->idr[0], IDR0, ATS));
>      }
>  
> +    if (s->ril == ON_OFF_AUTO_AUTO) {
> +        s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL,
> +                               FIELD_EX32(info->idr[3], IDR3, RIL));
> +    }
> +
>      accel->auto_finalised = true;
>  }
>  
> @@ -968,7 +973,8 @@ void smmuv3_accel_init(SMMUv3State *s)
>      bs->iommu_ops = &smmuv3_accel_ops;
>      smmuv3_accel_as_init(s);
>  
> -    if (s->ats == ON_OFF_AUTO_AUTO) {
> +    if (s->ats == ON_OFF_AUTO_AUTO ||
> +        s->ril == ON_OFF_AUTO_AUTO) {
>          s->s_accel->auto_mode = true;
>      }
>  
> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
> index 5671649fee..b7aa4122eb 100644
> --- a/hw/arm/smmuv3.c
> +++ b/hw/arm/smmuv3.c
> @@ -1972,10 +1972,6 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
>      }
>  #endif
>  
> -    if (s->ril == ON_OFF_AUTO_AUTO) {
> -        error_setg(errp, "ril auto mode is not supported");
> -        return false;
> -    }
>      if (s->ssidsize == SSID_SIZE_MODE_AUTO) {
>          error_setg(errp, "ssidsize auto mode is not supported");
>          return false;
> @@ -2168,8 +2164,10 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)
>          "Enable SMMUv3 accelerator support. Allows host SMMUv3 to be "
>          "configured in nested mode for vfio-pci dev assignment");
>      object_class_property_set_description(klass, "ril",
> -        "Disable range invalidation support (for accel=on). ril=auto "
> -        "is not supported.");
> +        "Enable/disable range invalidation support (for accel=on). "
> +        "Valid values are on, off, and auto. Defaults to on. "
> +        "Please enable if host platform supports RIL, and disable if "
suggest: any attempt to turn it 'on' while the host does not support it
would fail

Reviewed-by: Eric Auger <eric.auger@redhat.com>

Eric
> +        "host platform does not support RIL.");
>      object_class_property_set_description(klass, "ats",
>          "Enable/disable ATS support (for accel=on). "
>          "Valid values are on, off, and auto. Defaults to off. "

Re: [PATCH v2 4/7] hw/arm/smmuv3-accel: Implement "auto" value for "ssidsize"

[Eric Auger]

On 4/22/26 10:43 PM, Nathan Chen wrote:
> Allow accelerated SMMUv3 SSID size property to be derived from host
> IOMMU capabilities. Derive host values using IOMMU_GET_HW_INFO,
> retrieving SSID size from IDR1. When the auto SSID size is resolved
> to a non-zero value, PASID capability is advertised to the vIOMMU
> and accelerated use cases such as Shared Virtual Addressing (SVA)
> are supported.
>
> Signed-off-by: Nathan Chen <nathanc@nvidia.com>
> ---
>  hw/arm/smmuv3-accel.c | 18 ++++++++++++++++--
>  hw/arm/smmuv3.c       | 20 ++++++++++----------
>  2 files changed, 26 insertions(+), 12 deletions(-)
>
> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
> index 98c2cdcb5e..d13d15a11d 100644
> --- a/hw/arm/smmuv3-accel.c
> +++ b/hw/arm/smmuv3-accel.c
> @@ -62,6 +62,12 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,
>                                 FIELD_EX32(info->idr[3], IDR3, RIL));
>      }
>  
> +    if (s->ssidsize == SSID_SIZE_MODE_AUTO) {
> +        /* Store for get_viommu_flags() to determine PASID support */
> +        s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SSIDSIZE,
> +                               FIELD_EX32(info->idr[1], IDR1, SSIDSIZE));
> +    }
> +
>      accel->auto_finalised = true;
>  }
>  
> @@ -822,6 +828,13 @@ static AddressSpace *smmuv3_accel_find_add_as(PCIBus *bus, void *opaque,
>      }
>  }
>  
> +static inline bool smmuv3_pasid_supported(SMMUv3State *s)
> +{
> +    return s->ssidsize > SSID_SIZE_MODE_0 ||
> +           (s->ssidsize == SSID_SIZE_MODE_AUTO &&
> +            FIELD_EX32(s->idr[1], IDR1, SSIDSIZE));
> +}
> +
>  static uint64_t smmuv3_accel_get_viommu_flags(void *opaque)
>  {
>      /*
> @@ -834,7 +847,7 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *opaque)
>      SMMUState *bs = opaque;
>      SMMUv3State *s = ARM_SMMUV3(bs);
>  
> -    if (s->ssidsize > SSID_SIZE_MODE_0) {
> +    if (smmuv3_pasid_supported(s)) {
>          flags |= VIOMMU_FLAG_PASID_SUPPORTED;
>      }
>      return flags;
> @@ -974,7 +987,8 @@ void smmuv3_accel_init(SMMUv3State *s)
>      smmuv3_accel_as_init(s);
>  
>      if (s->ats == ON_OFF_AUTO_AUTO ||
> -        s->ril == ON_OFF_AUTO_AUTO) {
> +        s->ril == ON_OFF_AUTO_AUTO ||
> +        s->ssidsize == SSID_SIZE_MODE_AUTO) {
>          s->s_accel->auto_mode = true;
>      }
>  
> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
> index b7aa4122eb..07025245e2 100644
> --- a/hw/arm/smmuv3.c
> +++ b/hw/arm/smmuv3.c
> @@ -626,7 +626,10 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
>      }
>  
>      /* Multiple context descriptors require SubstreamID support */
> -    if (s->ssidsize == SSID_SIZE_MODE_0 && STE_S1CDMAX(ste) != 0) {
> +    if ((s->ssidsize == SSID_SIZE_MODE_0 ||
> +         (s->ssidsize == SSID_SIZE_MODE_AUTO &&
> +          !FIELD_EX32(s->idr[1], IDR1, SSIDSIZE))) &&
> +        STE_S1CDMAX(ste) != 0) {
>          qemu_log_mask(LOG_UNIMP,
>                  "SMMUv3: multiple S1 context descriptors require SubstreamID support. "
>                  "Configure ssidsize > 0 (requires accel=on)\n");
> @@ -1972,10 +1975,6 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
>      }
>  #endif
>  
> -    if (s->ssidsize == SSID_SIZE_MODE_AUTO) {
> -        error_setg(errp, "ssidsize auto mode is not supported");
> -        return false;
> -    }
>      if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48) {
>          error_setg(errp, "QEMU SMMUv3 model only implements 44 and 48 bit"
>                     "OAS; other OasMode values are not supported");
> @@ -1996,7 +1995,8 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
>              return false;
>          }
>          if (s->ssidsize > SSID_SIZE_MODE_0) {
> -            error_setg(errp, "ssidsize can only be set if accel=on");
> +            error_setg(errp, "ssidsize can only be greater than 0 "
> +                       "bits if accel=on");
>              return false;
>          }
>          return true;
> @@ -2177,11 +2177,11 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)
>          "are 44 or 48 bits. Defaults to 44 bits. oas=auto is not "
>          "supported.");
>      object_class_property_set_description(klass, "ssidsize",
> -        "Number of bits used to represent SubstreamIDs (SSIDs). "
> +        "Set number of bits used to represent SubstreamIDs (SSIDs). "
> +        "Valid values are 0-20 and auto. Defaults to 0. "
>          "A value of N allows SSIDs in the range [0 .. 2^N - 1]. "
> -        "Valid range is 0-20, where 0 disables SubstreamID support. "
> -        "Defaults to 0. A value greater than 0 is required to enable "
> -        "PASID support. ssidsize=auto is not supported.");
> +        "A value of 0 disables SubstreamID support. A value greater "
> +        "than 0 is required to enable PASID support.");
if 'auto', the host smmu value is used.

Besides
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Eric

>  }
>  
>  static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu,

Re: [PATCH v2 5/7] hw/arm/smmuv3-accel: Implement "auto" value for "oas"

[Eric Auger]

On 4/22/26 10:43 PM, Nathan Chen wrote:
> Allow accelerated SMMUv3 OAS property to be derived from host IOMMU
> capabilities. Derive host values using IOMMU_GET_HW_INFO, retrieving
> OAS from IDR5.
>
> This keeps the OAS value advertised by the virtual SMMU compatible with
> the capabilities of the host SMMUv3, so that the intermediate physical
> addresses (IPA) consumed by host SMMU for stage-2 translation do not
> exceed the host's max supported IPA size.
>
> Signed-off-by: Nathan Chen <nathanc@nvidia.com>
> ---
>  hw/arm/smmuv3-accel.c |  8 +++++++-
>  hw/arm/smmuv3.c       | 15 ++++++++-------
>  2 files changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c
> index d13d15a11d..f45e268bde 100644
> --- a/hw/arm/smmuv3-accel.c
> +++ b/hw/arm/smmuv3-accel.c
> @@ -68,6 +68,11 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,
>                                 FIELD_EX32(info->idr[1], IDR1, SSIDSIZE));
>      }
>  
> +    if (s->oas == OAS_MODE_AUTO) {
> +        s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS,
> +                               FIELD_EX32(info->idr[5], IDR5, OAS));
> +    }
> +
>      accel->auto_finalised = true;
>  }
>  
> @@ -988,7 +993,8 @@ void smmuv3_accel_init(SMMUv3State *s)
>  
>      if (s->ats == ON_OFF_AUTO_AUTO ||
>          s->ril == ON_OFF_AUTO_AUTO ||
> -        s->ssidsize == SSID_SIZE_MODE_AUTO) {
> +        s->ssidsize == SSID_SIZE_MODE_AUTO ||
> +        s->oas == OAS_MODE_AUTO) {
>          s->s_accel->auto_mode = true;
>      }
>  
> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
> index 07025245e2..39a6f72938 100644
> --- a/hw/arm/smmuv3.c
> +++ b/hw/arm/smmuv3.c
> @@ -1975,9 +1975,11 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
>      }
>  #endif
>  
> -    if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48) {
> -        error_setg(errp, "QEMU SMMUv3 model only implements 44 and 48 bit"
> -                   "OAS; other OasMode values are not supported");
> +    if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48 &&
> +        s->oas != OAS_MODE_AUTO) {
> +        error_setg(errp, "QEMU SMMUv3 model only implements auto, "
> +                   "44 bit, or 48 bit OAS. Other OasMode values are "
> +                   "not supported.");
>          return false;
>      }
>  
> @@ -1991,7 +1993,7 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)
>              return false;
>          }
>          if (s->oas > OAS_MODE_44) {
> -            error_setg(errp, "OAS must be 44 bits when accel=off");
> +            error_setg(errp, "oas must be 44 bits when accel=off");
>              return false;
>          }
>          if (s->ssidsize > SSID_SIZE_MODE_0) {
> @@ -2173,9 +2175,8 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)
>          "Valid values are on, off, and auto. Defaults to off. "
>          "Please ensure host platform supports ATS before enabling.");
>      object_class_property_set_description(klass, "oas",
> -        "Specify Output Address Size (for accel=on). Supported values "
> -        "are 44 or 48 bits. Defaults to 44 bits. oas=auto is not "
> -        "supported.");
> +        "Set Output Address Size in bits (for accel=on). "
> +        "Valid values are 44, 48, and auto. Defaults to 44 bits.");


same auto mode is not explained. It must be explainer either here of in
qemu-options.hx

when set to 'auto' the oas value is derived from host smmu value.

Besides
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Eric


>      object_class_property_set_description(klass, "ssidsize",
>          "Set number of bits used to represent SubstreamIDs (SSIDs). "
>          "Valid values are 0-20 and auto. Defaults to 0. "

Re: [PATCH v2 6/7] hw/arm/smmuv3: Set default ats, ril, ssidsize, oas to auto

[Eric Auger]

Hi Nathan,

On 4/22/26 10:43 PM, Nathan Chen wrote:
> Set the default value of ATS, RIL, SSIDSIZE, and OAS to auto, in order
> to match the host IOMMU properties when accel=on.
>
> If accel=off and these property values are set to auto, the default
> property values defined in smmuv3_init_id_regs() for OAS and RIL will
> remain unchanged, while SSIDSIZE and ATS values will remain initialized
> at 0.
>
> Introduce a new compat for the changed defaults.
>
> Signed-off-by: Nathan Chen <nathanc@nvidia.com>
> ---
>  hw/arm/smmuv3.c   | 14 +++++++-------
>  hw/core/machine.c |  8 ++++++++
>  2 files changed, 15 insertions(+), 7 deletions(-)
>
> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
> index 39a6f72938..e8ca6be34a 100644
> --- a/hw/arm/smmuv3.c
> +++ b/hw/arm/smmuv3.c
> @@ -2135,11 +2135,11 @@ static const Property smmuv3_properties[] = {
>      /* GPA of MSI doorbell, for SMMUv3 accel use. */
>      DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0),
>      /* RIL can be turned off for accel cases */
> -    DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON),
> -    DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF),
> -    DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_44),
> +    DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_AUTO),
> +    DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_AUTO),
> +    DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_AUTO),
The previous suggestions I gave wrt AUTO mode only held for accel mode.
So maybe we should put the consolidated info in qemu-options.hx and not in 

object_class_property_set_description. In this latter we shall only list valid value default.

Here I would add a comment reemphasizing that AUTO values for non accel
is ON/OFF/44/0

Thanks

Eric
>      DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize,
> -                              SSID_SIZE_MODE_0),
> +                              SSID_SIZE_MODE_AUTO),
>  };
>  
>  static void smmuv3_instance_init(Object *obj)
> @@ -2167,7 +2167,7 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)
>          "configured in nested mode for vfio-pci dev assignment");
>      object_class_property_set_description(klass, "ril",
>          "Enable/disable range invalidation support (for accel=on). "
> -        "Valid values are on, off, and auto. Defaults to on. "
> +        "Valid values are on, off, and auto. Defaults to auto. "
>          "Please enable if host platform supports RIL, and disable if "
>          "host platform does not support RIL.");
>      object_class_property_set_description(klass, "ats",
> @@ -2176,10 +2176,10 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)
>          "Please ensure host platform supports ATS before enabling.");
>      object_class_property_set_description(klass, "oas",
>          "Set Output Address Size in bits (for accel=on). "
> -        "Valid values are 44, 48, and auto. Defaults to 44 bits.");
> +        "Valid values are 44, 48, and auto. Defaults to auto.");
>      object_class_property_set_description(klass, "ssidsize",
>          "Set number of bits used to represent SubstreamIDs (SSIDs). "
> -        "Valid values are 0-20 and auto. Defaults to 0. "
> +        "Valid values are 0-20 and auto. Defaults to auto. "
>          "A value of N allows SSIDs in the range [0 .. 2^N - 1]. "
>          "A value of 0 disables SubstreamID support. A value greater "
>          "than 0 is required to enable PASID support.");
> diff --git a/hw/core/machine.c b/hw/core/machine.c
> index 0aa77a57e9..a668bb2ec3 100644
> --- a/hw/core/machine.c
> +++ b/hw/core/machine.c
> @@ -37,6 +37,14 @@
>  #include "hw/virtio/virtio-iommu.h"
>  #include "hw/acpi/generic_event_device.h"
>  #include "qemu/audio.h"
> +#include "hw/arm/smmuv3.h"
> +
> +GlobalProperty hw_compat_11_0[] = {
> +    { TYPE_ARM_SMMUV3, "ats", "off" },
> +    { TYPE_ARM_SMMUV3, "ril", "on" },
> +    { TYPE_ARM_SMMUV3, "ssidsize", "0" },
> +    { TYPE_ARM_SMMUV3, "oas", "44" },
> +};
>  
>  GlobalProperty hw_compat_10_2[] = {
>      { "scsi-block", "migrate-pr", "off" },

Re: [PATCH v2 7/7] qemu-options.hx: Support "auto" for accel SMMUv3 properties

[Eric Auger]

Hi Nathan,
On 4/22/26 10:43 PM, Nathan Chen wrote:
> Update documentation now that "auto" is supported for accelerated SMMUv3
> properties.
>
> Signed-off-by: Nathan Chen <nathanc@nvidia.com>
> ---
>  qemu-options.hx | 33 +++++++++++++++++++++++----------
>  1 file changed, 23 insertions(+), 10 deletions(-)
>
> diff --git a/qemu-options.hx b/qemu-options.hx
> index 21972f8326..2c6ba16a26 100644
> --- a/qemu-options.hx
> +++ b/qemu-options.hx
> @@ -1291,30 +1291,43 @@ SRST
>          Enabling accel configures the host SMMUv3 in nested mode to support
>          vfio-pci passthrough.
>  
> -     The following options are available when accel=on.
> -     Note: 'auto' mode is not currently supported.
> -
> -    ``ril=on|off`` (default: on)
> +     The following options will be set to auto by default if not manually
> +     set. When accel=on and these properties are set to auto, the value is
> +     derived from the host SMMUv3 capabilities via IOMMU_GET_HW_INFO. With
> +     accel=on, this requires at least one cold-plugged vfio-pci device; if
> +     none is present at machine init, QEMU will abort.
> +
> +     If accel=off and these property values are set to auto, the values will
> +     not be derived from the host SMMUv3 capabilities. Instead, they will
> +     resolve to the defaults described below, and a cold-plugged vfio-pci
> +     device is not required.
I would simply say:

If accel=off auto values resolve to the non accel default given below.


> +
> +    ``ril=on|off`` (default: auto)
ril=on|off|auto (default: auto)
          -------

I would rewrite it into:

Support for Range Invalidation, which allows the SMMUv3 driver to
invalidate TLB entries for a range of IOVAs at once instead of issuing
separate commands to invalidate each page. 
- with accel=on auto means the value is automatically derived from the host SMMU
  if explicitly set to 'on', the host must also support it.
- with accel=off auto is resolved into 'on'

If we have this explanation here in object_class_property_set_description()
just explain the basic semantic and list the valid values and default value.
No use to rexplain the auto mode semantic.



>          Support for Range Invalidation, which allows the SMMUv3 driver to
>          invalidate TLB entries for a range of IOVAs at once instead of issuing
>          separate commands to invalidate each page. Must match with host SMMUv3
> -        Range Invalidation support.
> +        Range Invalidation support. If accel=off and ril is set to auto, this
> +        property value will resolve to on.
Same for the others ...

Thanks

Eric
>  
> -    ``ats=on|off`` (default: off)
> +    ``ats=on|off`` (default: auto)
>          Support for Address Translation Services, which enables PCIe devices to
>          cache address translations in their local TLB and reduce latency. Host
>          SMMUv3 must support ATS in order to enable this feature for the vIOMMU.
> +        If accel=off and ats is set to auto, the property value will resolve to
> +        off.
>  
> -    ``oas=val`` (supported values are 44 and 48. default: 44)
> +    ``oas=val`` (supported values are 44 and 48. default: auto)
>          Sets the Output Address Size in bits. The value set here must be less
>          than or equal to the host SMMUv3's supported OAS, so that the
>          intermediate physical addresses (IPA) consumed by host SMMU for stage-2
> -        translation do not exceed the host's max supported IPA size.
> +        translation do not exceed the host's max supported IPA size. If
> +        accel=off and oas is set to auto, the property value will resolve to 44.
>  
> -    ``ssidsize=val`` (val between 0 and 20. default: 0)
> +    ``ssidsize=val`` (val between 0 and 20. default: auto)
>          Sets the Substream ID size in bits. When set to a non-zero value,
>          PASID capability is advertised to the vIOMMU and accelerated use cases
> -        such as Shared Virtual Addressing (SVA) are supported.
> +        such as Shared Virtual Addressing (SVA) are supported. If accel=off
> +        and ssidsize is set to auto, the property value will resolve to 0.
>  
>  ``-device amd-iommu[,option=...]``
>      Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU).

Re: [PATCH v2 7/7] qemu-options.hx: Support "auto" for accel SMMUv3 properties

[Nathan Chen]

Hi Eric,

On 5/8/2026 5:08 AM, Eric Auger wrote:
> Hi Nathan,
> On 4/22/26 10:43 PM, Nathan Chen wrote:
>> Update documentation now that "auto" is supported for accelerated SMMUv3
>> properties.
>>
>> Signed-off-by: Nathan Chen<nathanc@nvidia.com>
>> ---
>>   qemu-options.hx | 33 +++++++++++++++++++++++----------
>>   1 file changed, 23 insertions(+), 10 deletions(-)
>>
>> diff --git a/qemu-options.hx b/qemu-options.hx
>> index 21972f8326..2c6ba16a26 100644
>> --- a/qemu-options.hx
>> +++ b/qemu-options.hx
>> @@ -1291,30 +1291,43 @@ SRST
>>           Enabling accel configures the host SMMUv3 in nested mode to support
>>           vfio-pci passthrough.
>>   
>> -     The following options are available when accel=on.
>> -     Note: 'auto' mode is not currently supported.
>> -
>> -    ``ril=on|off`` (default: on)
>> +     The following options will be set to auto by default if not manually
>> +     set. When accel=on and these properties are set to auto, the value is
>> +     derived from the host SMMUv3 capabilities via IOMMU_GET_HW_INFO. With
>> +     accel=on, this requires at least one cold-plugged vfio-pci device; if
>> +     none is present at machine init, QEMU will abort.
>> +
>> +     If accel=off and these property values are set to auto, the values will
>> +     not be derived from the host SMMUv3 capabilities. Instead, they will
>> +     resolve to the defaults described below, and a cold-plugged vfio-pci
>> +     device is not required.
> I would simply say:
> 
> If accel=off auto values resolve to the non accel default given below.
> 
Got it, I will simplify the accel=off explanation accordingly.

> 
>> +
>> +    ``ril=on|off`` (default: auto)
> ril=on|off|auto (default: auto)
>            -------
> 
> I would rewrite it into:
> 
> Support for Range Invalidation, which allows the SMMUv3 driver to
> invalidate TLB entries for a range of IOVAs at once instead of issuing
> separate commands to invalidate each page.
> - with accel=on auto means the value is automatically derived from the host SMMU
>    if explicitly set to 'on', the host must also support it.
> - with accel=off auto is resolved into 'on'
> 
> If we have this explanation here in object_class_property_set_description()
> just explain the basic semantic and list the valid values and default value.
> No use to rexplain the auto mode semantic.
> 
> 
> 
>>           Support for Range Invalidation, which allows the SMMUv3 driver to
>>           invalidate TLB entries for a range of IOVAs at once instead of issuing
>>           separate commands to invalidate each page. Must match with host SMMUv3
>> -        Range Invalidation support.
>> +        Range Invalidation support. If accel=off and ril is set to auto, this
>> +        property value will resolve to on.
> Same for the others ...
Ok, I will leave the auto explanation out of 
object_class_property_set_description() and keep it here.

Thanks,
Nathan

Re: [PATCH v2 7/7] qemu-options.hx: Support "auto" for accel SMMUv3 properties

[Nathan Chen]

Hi Eric,

On 5/8/2026 5:08 AM, Eric Auger wrote:
> Hi Nathan,
> On 4/22/26 10:43 PM, Nathan Chen wrote:
>> Update documentation now that "auto" is supported for accelerated SMMUv3
>> properties.
>>
>> Signed-off-by: Nathan Chen<nathanc@nvidia.com>
>> ---
>>   qemu-options.hx | 33 +++++++++++++++++++++++----------
>>   1 file changed, 23 insertions(+), 10 deletions(-)
>>
>> diff --git a/qemu-options.hx b/qemu-options.hx
>> index 21972f8326..2c6ba16a26 100644
>> --- a/qemu-options.hx
>> +++ b/qemu-options.hx
>> @@ -1291,30 +1291,43 @@ SRST
>>           Enabling accel configures the host SMMUv3 in nested mode to support
>>           vfio-pci passthrough.
>>   
>> -     The following options are available when accel=on.
>> -     Note: 'auto' mode is not currently supported.
>> -
>> -    ``ril=on|off`` (default: on)
>> +     The following options will be set to auto by default if not manually
>> +     set. When accel=on and these properties are set to auto, the value is
>> +     derived from the host SMMUv3 capabilities via IOMMU_GET_HW_INFO. With
>> +     accel=on, this requires at least one cold-plugged vfio-pci device; if
>> +     none is present at machine init, QEMU will abort.
>> +
>> +     If accel=off and these property values are set to auto, the values will
>> +     not be derived from the host SMMUv3 capabilities. Instead, they will
>> +     resolve to the defaults described below, and a cold-plugged vfio-pci
>> +     device is not required.
> I would simply say:
> 
> If accel=off auto values resolve to the non accel default given below.
> 
Got it, I will simplify the accel=off explanation accordingly.

> 
>> +
>> +    ``ril=on|off`` (default: auto)
> ril=on|off|auto (default: auto)
>            -------
> 
> I would rewrite it into:
> 
> Support for Range Invalidation, which allows the SMMUv3 driver to
> invalidate TLB entries for a range of IOVAs at once instead of issuing
> separate commands to invalidate each page.
> - with accel=on auto means the value is automatically derived from the host SMMU
>    if explicitly set to 'on', the host must also support it.
> - with accel=off auto is resolved into 'on'
> 
> If we have this explanation here in object_class_property_set_description()
> just explain the basic semantic and list the valid values and default value.
> No use to rexplain the auto mode semantic.
> 
> 
> 
>>           Support for Range Invalidation, which allows the SMMUv3 driver to
>>           invalidate TLB entries for a range of IOVAs at once instead of issuing
>>           separate commands to invalidate each page. Must match with host SMMUv3
>> -        Range Invalidation support.
>> +        Range Invalidation support. If accel=off and ril is set to auto, this
>> +        property value will resolve to on.
> Same for the others ...
Ok, I will leave the auto explanation out of 
object_class_property_set_description() and keep it here.

Thanks,
Nathan