[PATCH v1 0/5] Split miscellaneous changes from AST2700 FC series

[PATCH v1 0/5] Split miscellaneous changes from AST2700 FC series

[Jamin Lin]

The original series contains both the AST2700 FC support and several unrelated
cleanups and preparatory changes. Since these changes are independent of the
FC functionality, they are moved into a separate series so they can be reviewed
and merged independently.

This series includes:

Fix the AST2700 FC hardware strap configuration.
Suppress noisy unhandled register read messages for the AST2700 SCU/SCUIO.
Add the AST2700 SCUIO RNG control and data registers.
Add unimplemented Privilege Controller MMIO regions for the SSP/TSP.
Add unimplemented OTP controller MMIO regions for the SSP/TSP.

The original AST2700 FC series can be found here:

https://patchwork.kernel.org/project/qemu-devel/cover/20260417032837.2664122-1-jamin_lin@aspeedtech.com/

Jamin Lin (5):
  hw/arm/aspeed_ast27x0-fc: Fix hardware strap settings
  hw/misc/aspeed_scu: Drop noisy unhandled read logs for AST2700
    SCU/SCUIO
  hw/misc/aspeed_scu: Add AST2700 SCUIO RNG control and data registers
  hw/arm/aspeed_ast27x0: Add unimplemented Privilege Controller MMIO
    regions for SSP/TSP
  hw/arm/aspeed_ast27x0: Add unimplemented OTP controller MMIO regions
    for SSP/TSP

 include/hw/arm/aspeed_coprocessor.h |  2 ++
 include/hw/arm/aspeed_soc.h         |  3 +++
 hw/arm/aspeed_ast27x0-fc.c          |  6 ++++--
 hw/arm/aspeed_ast27x0-ssp.c         | 19 +++++++++++++++++
 hw/arm/aspeed_ast27x0-tsp.c         | 19 +++++++++++++++++
 hw/misc/aspeed_scu.c                | 33 +++++++++++++++++++----------
 6 files changed, 69 insertions(+), 13 deletions(-)

-- 
2.43.0

[PATCH v1 1/5] hw/arm/aspeed_ast27x0-fc: Fix hardware strap settings

[Jamin Lin]

The hardware strap settings in the AST2700 FC machine model were incorrect.

Update HW_STRAP1 and HW_STRAP2 to match the values observed from the
real EVB dump. These values are also consistent with the current
aspeed_ast27x0_evb.c machine setup.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/arm/aspeed_ast27x0-fc.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 5eb6680da9..7d9fade68d 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -50,8 +50,10 @@ struct Ast2700FCState {
 
 #define AST2700FC_BMC_RAM_SIZE (2 * GiB)
 
-#define AST2700FC_HW_STRAP1 0x000000C0
-#define AST2700FC_HW_STRAP2 0x00000003
+/* SCU HW Strap1 */
+#define AST2700FC_HW_STRAP1 0x00000800
+/* SCUIO HW Strap1 */
+#define AST2700FC_HW_STRAP2 0x00000700
 #define AST2700FC_FMC_MODEL "w25q01jvq"
 #define AST2700FC_SPI_MODEL "w25q512jv"
 
-- 
2.43.0

[PATCH v1 2/5] hw/misc/aspeed_scu: Drop noisy unhandled read logs for AST2700 SCU/SCUIO

[Jamin Lin]

The AST2700 SCU/SCUIO read handlers currently emit LOG_GUEST_ERROR
messages for all registers that are not explicitly handled.

However, most SCU registers are simple read-back registers without
side effects, and do not require explicit handling in the read path.
Returning the stored register value is sufficient.

Emitting "Unhandled read" logs for these cases generates excessive
and misleading noise during normal guest operation, making it harder
to spot real issues.

Remove the default unhandled read logging from the SCU and SCUIO read
handlers to reduce log noise and align with common QEMU device model
behavior for passive registers.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/misc/aspeed_scu.c | 14 --------------
 1 file changed, 14 deletions(-)

diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index fe731a28bd..ed7f5e648d 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -849,13 +849,6 @@ static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,
         return 0;
     }
 
-    switch (reg) {
-    default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: Unhandled read at offset 0x%" HWADDR_PRIx "\n",
-                      __func__, offset);
-    }
-
     trace_aspeed_ast2700_scu_read(offset, size, s->regs[reg]);
     return s->regs[reg];
 }
@@ -961,13 +954,6 @@ static uint64_t aspeed_ast2700_scuio_read(void *opaque, hwaddr offset,
         return 0;
     }
 
-    switch (reg) {
-    default:
-        qemu_log_mask(LOG_GUEST_ERROR,
-                      "%s: Unhandled read at offset 0x%" HWADDR_PRIx "\n",
-                      __func__, offset);
-    }
-
     trace_aspeed_ast2700_scuio_read(offset, size, s->regs[reg]);
     return s->regs[reg];
 }
-- 
2.43.0

[PATCH v1 3/5] hw/misc/aspeed_scu: Add AST2700 SCUIO RNG control and data registers

[Jamin Lin]

Implement basic behavior for RNG_CTRL and RNG_DATA:

- RNG_CTRL allows guest to enable/disable the RNG via the DIS bit.
  Only bits [0:3] and bit 5 are writable; other bits are masked.
- The VLD bit (bit 31) is updated by the model to reflect the RNG
  enable state, and is not writable by the guest.
- When RNG is enabled, reads from RNG_DATA return a newly generated
  random value.
- When RNG is disabled, RNG_DATA return 0.

This provides a minimal functional model of the RNG sufficient for
software that expects readable random data without modeling full
hardware behavior.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/misc/aspeed_scu.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index ed7f5e648d..5dbf81c0ce 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -160,6 +160,11 @@
 #define AST2700_SCU_CPU_SCRATCH_1   TO_REG(0x784)
 #define AST2700_SCU_VGA_SCRATCH_0   TO_REG(0x900)
 
+#define AST2700_SCUIO_RNG_CTRL          TO_REG(0xF0)
+#define AST2700_SCUIO_RNG_CTRL_MASK     0x2F
+#define AST2700_SCUIO_RNG_CTRL_DIS      BIT(0)
+#define AST2700_SCUIO_RNG_CTRL_VLD      BIT(31)
+#define AST2700_SCUIO_RNG_DATA          TO_REG(0xF4)
 #define AST2700_SCUIO_CLK_STOP_CTL_1    TO_REG(0x240)
 #define AST2700_SCUIO_CLK_STOP_CLR_1    TO_REG(0x244)
 #define AST2700_SCUIO_CLK_STOP_CTL_2    TO_REG(0x260)
@@ -954,6 +959,14 @@ static uint64_t aspeed_ast2700_scuio_read(void *opaque, hwaddr offset,
         return 0;
     }
 
+    switch (reg) {
+    case AST2700_SCUIO_RNG_DATA:
+        if (!(s->regs[AST2700_SCUIO_RNG_CTRL] & AST2700_SCUIO_RNG_CTRL_DIS)) {
+            s->regs[AST2700_SCUIO_RNG_DATA] = aspeed_scu_get_random();
+        }
+        break;
+    }
+
     trace_aspeed_ast2700_scuio_read(offset, size, s->regs[reg]);
     return s->regs[reg];
 }
@@ -977,6 +990,18 @@ static void aspeed_ast2700_scuio_write(void *opaque, hwaddr offset,
     trace_aspeed_ast2700_scuio_write(offset, size, data);
 
     switch (reg) {
+    case AST2700_SCUIO_RNG_CTRL:
+        data &= AST2700_SCUIO_RNG_CTRL_MASK;
+        if (data & AST2700_SCUIO_RNG_CTRL_DIS) {
+            data &= ~AST2700_SCUIO_RNG_CTRL_VLD;
+            s->regs[AST2700_SCUIO_RNG_DATA] = 0;
+        } else {
+            s->regs[AST2700_SCUIO_RNG_DATA] = aspeed_scu_get_random();
+            data |= AST2700_SCUIO_RNG_CTRL_VLD;
+        }
+        s->regs[reg] = data;
+        updated = true;
+        break;
     case AST2700_SCUIO_CLK_STOP_CTL_1:
     case AST2700_SCUIO_CLK_STOP_CTL_2:
         s->regs[reg] |= data;
-- 
2.43.0

[PATCH v1 4/5] hw/arm/aspeed_ast27x0: Add unimplemented Privilege Controller MMIO regions for SSP/TSP

[Jamin Lin]

The AST2700 SSP/TSP firmware accesses Privilege Controller MMIO regions that
are not yet implemented in QEMU.

This change adds unimplemented MMIO devices for the Privilege Controller
blocks and maps them to their corresponding physical addresses in the SSP/TSP
address space. These stub devices allow QEMU to safely handle firmware
accesses and prevent spurious exceptions, while accurately reflecting
the hardware memory map.

No functional changes.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 include/hw/arm/aspeed_coprocessor.h |  1 +
 include/hw/arm/aspeed_soc.h         |  2 ++
 hw/arm/aspeed_ast27x0-ssp.c         | 13 +++++++++++++
 hw/arm/aspeed_ast27x0-tsp.c         | 13 +++++++++++++
 4 files changed, 29 insertions(+)

diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
index 4a50f688ec..700cbfb4bb 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -48,6 +48,7 @@ struct Aspeed27x0CoprocessorState {
     AspeedINTCState intc[2];
     UnimplementedDeviceState ipc[2];
     UnimplementedDeviceState scuio;
+    UnimplementedDeviceState pric[2];
 
     ARMv7MState armv7m;
 };
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 3aac144cd4..a0d2432620 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -295,6 +295,8 @@ enum {
     ASPEED_DEV_IOEXP1_INTCIO,
     ASPEED_DEV_IOEXP0_I3C,
     ASPEED_DEV_IOEXP1_I3C,
+    ASPEED_DEV_PRIC0,
+    ASPEED_DEV_PRIC1,
 };
 
 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index b3c4eb1915..1b68e4eb5f 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -22,10 +22,13 @@ static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
     [ASPEED_DEV_SDRAM]     =  0x00000000,
     [ASPEED_DEV_SRAM0]     =  0x70000000,
     [ASPEED_DEV_INTC]      =  0x72100000,
+    [ASPEED_DEV_PRIC0]     =  0x72140000,
     [ASPEED_DEV_SCU]       =  0x72C02000,
     [ASPEED_DEV_TIMER1]    =  0x72C10000,
     [ASPEED_DEV_UART4]     =  0x72C1A000,
     [ASPEED_DEV_IPC0]      =  0x72C1C000,
+    [ASPEED_DEV_FMC]       =  0x74000000,
+    [ASPEED_DEV_PRIC1]     =  0x74100000,
     [ASPEED_DEV_SCUIO]     =  0x74C02000,
     [ASPEED_DEV_INTCIO]    =  0x74C18000,
     [ASPEED_DEV_UART0]     =  0x74C33000,
@@ -141,6 +144,10 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj)
                             TYPE_UNIMPLEMENTED_DEVICE);
     object_initialize_child(obj, "scuio", &a->scuio,
                             TYPE_UNIMPLEMENTED_DEVICE);
+    object_initialize_child(obj, "pric0", &a->pric[0],
+                            TYPE_UNIMPLEMENTED_DEVICE);
+    object_initialize_child(obj, "pric1", &a->pric[1],
+                            TYPE_UNIMPLEMENTED_DEVICE);
 }
 
 static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
@@ -255,6 +262,12 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
     aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio),
                                   "aspeed.scuio",
                                   sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
+    aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[0]),
+                                  "aspeed.pric0",
+                                  sc->memmap[ASPEED_DEV_PRIC0], 0x1000);
+    aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[1]),
+                                  "aspeed.pric1",
+                                  sc->memmap[ASPEED_DEV_PRIC1], 0x1000);
 }
 
 static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 6098d1aae3..59dcccd511 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -22,10 +22,13 @@ static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
     [ASPEED_DEV_SDRAM]     =  0x00000000,
     [ASPEED_DEV_SRAM0]     =  0x70000000,
     [ASPEED_DEV_INTC]      =  0x72100000,
+    [ASPEED_DEV_PRIC0]     =  0x72140000,
     [ASPEED_DEV_SCU]       =  0x72C02000,
     [ASPEED_DEV_TIMER1]    =  0x72C10000,
     [ASPEED_DEV_UART4]     =  0x72C1A000,
     [ASPEED_DEV_IPC0]      =  0x72C1C000,
+    [ASPEED_DEV_FMC]       =  0x74000000,
+    [ASPEED_DEV_PRIC1]     =  0x74100000,
     [ASPEED_DEV_SCUIO]     =  0x74C02000,
     [ASPEED_DEV_INTCIO]    =  0x74C18000,
     [ASPEED_DEV_UART0]     =  0x74C33000,
@@ -141,6 +144,10 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj)
                             TYPE_UNIMPLEMENTED_DEVICE);
     object_initialize_child(obj, "scuio", &a->scuio,
                             TYPE_UNIMPLEMENTED_DEVICE);
+    object_initialize_child(obj, "pric0", &a->pric[0],
+                            TYPE_UNIMPLEMENTED_DEVICE);
+    object_initialize_child(obj, "pric1", &a->pric[1],
+                            TYPE_UNIMPLEMENTED_DEVICE);
 }
 
 static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
@@ -255,6 +262,12 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
     aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->scuio),
                                   "aspeed.scuio",
                                   sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
+    aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[0]),
+                                  "aspeed.pric0",
+                                  sc->memmap[ASPEED_DEV_PRIC0], 0x1000);
+    aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[1]),
+                                  "aspeed.pric1",
+                                  sc->memmap[ASPEED_DEV_PRIC1], 0x1000);
 }
 
 static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
-- 
2.43.0

[PATCH v1 5/5] hw/arm/aspeed_ast27x0: Add unimplemented OTP controller MMIO regions for SSP/TSP

[Jamin Lin]

The AST2700 SSP/TSP firmware accesses OTP MMIO regions that
are not yet implemented in QEMU.

This change adds unimplemented MMIO devices for the OTP and maps them to
their corresponding physical addresses in the SSP/TSP address space.
These stub devices allow QEMU to safely handle firmware
accesses and prevent spurious exceptions, while accurately reflecting
the hardware memory map.

No functional changes.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 include/hw/arm/aspeed_coprocessor.h | 1 +
 include/hw/arm/aspeed_soc.h         | 1 +
 hw/arm/aspeed_ast27x0-ssp.c         | 6 ++++++
 hw/arm/aspeed_ast27x0-tsp.c         | 6 ++++++
 4 files changed, 14 insertions(+)

diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
index 700cbfb4bb..ac58a5f424 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -49,6 +49,7 @@ struct Aspeed27x0CoprocessorState {
     UnimplementedDeviceState ipc[2];
     UnimplementedDeviceState scuio;
     UnimplementedDeviceState pric[2];
+    UnimplementedDeviceState otp;
 
     ARMv7MState armv7m;
 };
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index a0d2432620..41dc04e293 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -297,6 +297,7 @@ enum {
     ASPEED_DEV_IOEXP1_I3C,
     ASPEED_DEV_PRIC0,
     ASPEED_DEV_PRIC1,
+    ASPEED_DEV_OTP,
 };
 
 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 1b68e4eb5f..cb96a56d7a 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -30,6 +30,7 @@ static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
     [ASPEED_DEV_FMC]       =  0x74000000,
     [ASPEED_DEV_PRIC1]     =  0x74100000,
     [ASPEED_DEV_SCUIO]     =  0x74C02000,
+    [ASPEED_DEV_OTP]       =  0x74C07000,
     [ASPEED_DEV_INTCIO]    =  0x74C18000,
     [ASPEED_DEV_UART0]     =  0x74C33000,
     [ASPEED_DEV_UART1]     =  0x74C33100,
@@ -148,6 +149,8 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj)
                             TYPE_UNIMPLEMENTED_DEVICE);
     object_initialize_child(obj, "pric1", &a->pric[1],
                             TYPE_UNIMPLEMENTED_DEVICE);
+    object_initialize_child(obj, "otp", &a->otp,
+                            TYPE_UNIMPLEMENTED_DEVICE);
 }
 
 static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
@@ -268,6 +271,9 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
     aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[1]),
                                   "aspeed.pric1",
                                   sc->memmap[ASPEED_DEV_PRIC1], 0x1000);
+    aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->otp),
+                                  "aspeed.otp",
+                                  sc->memmap[ASPEED_DEV_OTP], 0x800);
 }
 
 static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 59dcccd511..f6d63115aa 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -30,6 +30,7 @@ static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
     [ASPEED_DEV_FMC]       =  0x74000000,
     [ASPEED_DEV_PRIC1]     =  0x74100000,
     [ASPEED_DEV_SCUIO]     =  0x74C02000,
+    [ASPEED_DEV_OTP]       =  0x74C07000,
     [ASPEED_DEV_INTCIO]    =  0x74C18000,
     [ASPEED_DEV_UART0]     =  0x74C33000,
     [ASPEED_DEV_UART1]     =  0x74C33100,
@@ -148,6 +149,8 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj)
                             TYPE_UNIMPLEMENTED_DEVICE);
     object_initialize_child(obj, "pric1", &a->pric[1],
                             TYPE_UNIMPLEMENTED_DEVICE);
+    object_initialize_child(obj, "otp", &a->otp,
+                            TYPE_UNIMPLEMENTED_DEVICE);
 }
 
 static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
@@ -268,6 +271,9 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
     aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->pric[1]),
                                   "aspeed.pric1",
                                   sc->memmap[ASPEED_DEV_PRIC1], 0x1000);
+    aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&a->otp),
+                                  "aspeed.otp",
+                                  sc->memmap[ASPEED_DEV_OTP], 0x800);
 }
 
 static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
-- 
2.43.0

Re: [PATCH v1 5/5] hw/arm/aspeed_ast27x0: Add unimplemented OTP controller MMIO regions for SSP/TSP

[Philippe Mathieu-Daudé]

On 3/7/26 08:45, Jamin Lin wrote:
> The AST2700 SSP/TSP firmware accesses OTP MMIO regions that
> are not yet implemented in QEMU.
> 
> This change adds unimplemented MMIO devices for the OTP and maps them to
> their corresponding physical addresses in the SSP/TSP address space.
> These stub devices allow QEMU to safely handle firmware
> accesses and prevent spurious exceptions, while accurately reflecting
> the hardware memory map.
> 
> No functional changes.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
>   include/hw/arm/aspeed_coprocessor.h | 1 +
>   include/hw/arm/aspeed_soc.h         | 1 +
>   hw/arm/aspeed_ast27x0-ssp.c         | 6 ++++++
>   hw/arm/aspeed_ast27x0-tsp.c         | 6 ++++++
>   4 files changed, 14 insertions(+)

Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>

Re: [PATCH v1 4/5] hw/arm/aspeed_ast27x0: Add unimplemented Privilege Controller MMIO regions for SSP/TSP

[Philippe Mathieu-Daudé]

On 3/7/26 08:45, Jamin Lin wrote:
> The AST2700 SSP/TSP firmware accesses Privilege Controller MMIO regions that
> are not yet implemented in QEMU.
> 
> This change adds unimplemented MMIO devices for the Privilege Controller
> blocks and maps them to their corresponding physical addresses in the SSP/TSP
> address space. These stub devices allow QEMU to safely handle firmware
> accesses and prevent spurious exceptions, while accurately reflecting
> the hardware memory map.
> 
> No functional changes.
> 
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
>   include/hw/arm/aspeed_coprocessor.h |  1 +
>   include/hw/arm/aspeed_soc.h         |  2 ++
>   hw/arm/aspeed_ast27x0-ssp.c         | 13 +++++++++++++
>   hw/arm/aspeed_ast27x0-tsp.c         | 13 +++++++++++++
>   4 files changed, 29 insertions(+)


> diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
> index b3c4eb1915..1b68e4eb5f 100644
> --- a/hw/arm/aspeed_ast27x0-ssp.c
> +++ b/hw/arm/aspeed_ast27x0-ssp.c
> @@ -22,10 +22,13 @@ static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
>       [ASPEED_DEV_SDRAM]     =  0x00000000,
>       [ASPEED_DEV_SRAM0]     =  0x70000000,
>       [ASPEED_DEV_INTC]      =  0x72100000,
> +    [ASPEED_DEV_PRIC0]     =  0x72140000,
>       [ASPEED_DEV_SCU]       =  0x72C02000,
>       [ASPEED_DEV_TIMER1]    =  0x72C10000,
>       [ASPEED_DEV_UART4]     =  0x72C1A000,
>       [ASPEED_DEV_IPC0]      =  0x72C1C000,
> +    [ASPEED_DEV_FMC]       =  0x74000000,
> +    [ASPEED_DEV_PRIC1]     =  0x74100000,
>       [ASPEED_DEV_SCUIO]     =  0x74C02000,
>       [ASPEED_DEV_INTCIO]    =  0x74C18000,
>       [ASPEED_DEV_UART0]     =  0x74C33000,


> diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
> index 6098d1aae3..59dcccd511 100644
> --- a/hw/arm/aspeed_ast27x0-tsp.c
> +++ b/hw/arm/aspeed_ast27x0-tsp.c
> @@ -22,10 +22,13 @@ static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
>       [ASPEED_DEV_SDRAM]     =  0x00000000,
>       [ASPEED_DEV_SRAM0]     =  0x70000000,
>       [ASPEED_DEV_INTC]      =  0x72100000,
> +    [ASPEED_DEV_PRIC0]     =  0x72140000,
>       [ASPEED_DEV_SCU]       =  0x72C02000,
>       [ASPEED_DEV_TIMER1]    =  0x72C10000,
>       [ASPEED_DEV_UART4]     =  0x72C1A000,
>       [ASPEED_DEV_IPC0]      =  0x72C1C000,
> +    [ASPEED_DEV_FMC]       =  0x74000000,
> +    [ASPEED_DEV_PRIC1]     =  0x74100000,
>       [ASPEED_DEV_SCUIO]     =  0x74C02000,
>       [ASPEED_DEV_INTCIO]    =  0x74C18000,
>       [ASPEED_DEV_UART0]     =  0x74C33000,
It would be clearer to set ASPEED_DEV_FMC in a distinct patch,
otherwise:
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>

RE: [PATCH v1 4/5] hw/arm/aspeed_ast27x0: Add unimplemented Privilege Controller MMIO regions for SSP/TSP

[Jamin Lin]

Hi Philippe

> Privilege Controller MMIO regions for SSP/TSP
> 
> On 3/7/26 08:45, Jamin Lin wrote:
> > The AST2700 SSP/TSP firmware accesses Privilege Controller MMIO
> > regions that are not yet implemented in QEMU.
> >
> > This change adds unimplemented MMIO devices for the Privilege
> > Controller blocks and maps them to their corresponding physical
> > addresses in the SSP/TSP address space. These stub devices allow QEMU
> > to safely handle firmware accesses and prevent spurious exceptions,
> > while accurately reflecting the hardware memory map.
> >
> > No functional changes.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> >   include/hw/arm/aspeed_coprocessor.h |  1 +
> >   include/hw/arm/aspeed_soc.h         |  2 ++
> >   hw/arm/aspeed_ast27x0-ssp.c         | 13 +++++++++++++
> >   hw/arm/aspeed_ast27x0-tsp.c         | 13 +++++++++++++
> >   4 files changed, 29 insertions(+)
> 
> 
> > diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
> > index b3c4eb1915..1b68e4eb5f 100644
> > --- a/hw/arm/aspeed_ast27x0-ssp.c
> > +++ b/hw/arm/aspeed_ast27x0-ssp.c
> > @@ -22,10 +22,13 @@ static const hwaddr
> aspeed_soc_ast27x0ssp_memmap[] = {
> >       [ASPEED_DEV_SDRAM]     =  0x00000000,
> >       [ASPEED_DEV_SRAM0]     =  0x70000000,
> >       [ASPEED_DEV_INTC]      =  0x72100000,
> > +    [ASPEED_DEV_PRIC0]     =  0x72140000,
> >       [ASPEED_DEV_SCU]       =  0x72C02000,
> >       [ASPEED_DEV_TIMER1]    =  0x72C10000,
> >       [ASPEED_DEV_UART4]     =  0x72C1A000,
> >       [ASPEED_DEV_IPC0]      =  0x72C1C000,
> > +    [ASPEED_DEV_FMC]       =  0x74000000,
> > +    [ASPEED_DEV_PRIC1]     =  0x74100000,
> >       [ASPEED_DEV_SCUIO]     =  0x74C02000,
> >       [ASPEED_DEV_INTCIO]    =  0x74C18000,
> >       [ASPEED_DEV_UART0]     =  0x74C33000,
> 
> 
> > diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
> > index 6098d1aae3..59dcccd511 100644
> > --- a/hw/arm/aspeed_ast27x0-tsp.c
> > +++ b/hw/arm/aspeed_ast27x0-tsp.c
> > @@ -22,10 +22,13 @@ static const hwaddr
> aspeed_soc_ast27x0tsp_memmap[] = {
> >       [ASPEED_DEV_SDRAM]     =  0x00000000,
> >       [ASPEED_DEV_SRAM0]     =  0x70000000,
> >       [ASPEED_DEV_INTC]      =  0x72100000,
> > +    [ASPEED_DEV_PRIC0]     =  0x72140000,
> >       [ASPEED_DEV_SCU]       =  0x72C02000,
> >       [ASPEED_DEV_TIMER1]    =  0x72C10000,
> >       [ASPEED_DEV_UART4]     =  0x72C1A000,
> >       [ASPEED_DEV_IPC0]      =  0x72C1C000,
> > +    [ASPEED_DEV_FMC]       =  0x74000000,
> > +    [ASPEED_DEV_PRIC1]     =  0x74100000,
> >       [ASPEED_DEV_SCUIO]     =  0x74C02000,
> >       [ASPEED_DEV_INTCIO]    =  0x74C18000,
> >       [ASPEED_DEV_UART0]     =  0x74C33000,
> It would be clearer to set ASPEED_DEV_FMC in a distinct patch,
Thanks for the review.
ASPEED_DEV_FMC should be removed.
Will fix it.

Jamin

> otherwise:
> Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>

Re: [PATCH v1 0/5] Split miscellaneous changes from AST2700 FC series

[Cédric Le Goater]

On 7/3/26 08:45, Jamin Lin wrote:
> The original series contains both the AST2700 FC support and several unrelated
> cleanups and preparatory changes. Since these changes are independent of the
> FC functionality, they are moved into a separate series so they can be reviewed
> and merged independently.
> 
> This series includes:
> 
> Fix the AST2700 FC hardware strap configuration.
> Suppress noisy unhandled register read messages for the AST2700 SCU/SCUIO.
> Add the AST2700 SCUIO RNG control and data registers.
> Add unimplemented Privilege Controller MMIO regions for the SSP/TSP.
> Add unimplemented OTP controller MMIO regions for the SSP/TSP.
> 
> The original AST2700 FC series can be found here:
> 
> https://patchwork.kernel.org/project/qemu-devel/cover/20260417032837.2664122-1-jamin_lin@aspeedtech.com/
> 
> Jamin Lin (5):
>    hw/arm/aspeed_ast27x0-fc: Fix hardware strap settings
>    hw/misc/aspeed_scu: Drop noisy unhandled read logs for AST2700
>      SCU/SCUIO
>    hw/misc/aspeed_scu: Add AST2700 SCUIO RNG control and data registers
>    hw/arm/aspeed_ast27x0: Add unimplemented Privilege Controller MMIO
>      regions for SSP/TSP
>    hw/arm/aspeed_ast27x0: Add unimplemented OTP controller MMIO regions
>      for SSP/TSP
> 
>   include/hw/arm/aspeed_coprocessor.h |  2 ++
>   include/hw/arm/aspeed_soc.h         |  3 +++
>   hw/arm/aspeed_ast27x0-fc.c          |  6 ++++--
>   hw/arm/aspeed_ast27x0-ssp.c         | 19 +++++++++++++++++
>   hw/arm/aspeed_ast27x0-tsp.c         | 19 +++++++++++++++++
>   hw/misc/aspeed_scu.c                | 33 +++++++++++++++++++----------
>   6 files changed, 69 insertions(+), 13 deletions(-)
> 

I thought I had reviewed all these already. Anyhow,


Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.