From: sashiko-bot@kernel.org
To: "Dapeng Mi" <dapeng1.mi@linux.intel.com>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [Patch v9 08/24] x86/fpu: Add update_fpu_state_and_flag() helper
Date: Mon, 06 Jul 2026 02:22:53 +0000 [thread overview]
Message-ID: <20260706022254.214481F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260706015439.3040804-9-dapeng1.mi@linux.intel.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Guest FPU state leaks to host perf samples because the NMI handler incorrectly bypasses the `__task_fpstate` check when `TIF_NEED_FPU_LOAD` is 0.
--
commit a7b6e478b8260eaf627518f9d19e511212779fab
Author: Dapeng Mi <dapeng1.mi@linux.intel.com>
x86/fpu: Add update_fpu_state_and_flag() helper
This commit introduces the update_fpu_state_and_flag() helper to save user
FPU state and set TIF_NEED_FPU_LOAD. It also adds memory barriers in the
host/guest FPU state switch path to ensure fpu->__task_fpstate is observed
correctly when non-NULL.
Link: https://lore.kernel.org/all/20251204154721.GB2619703@noisy.programming.kicks-ass.net/
> diff --git a/arch/x86/kernel/fpu/core.c b/arch/x86/kernel/fpu/core.c
> index 584fb9913be42..fb78e0ecd5fa8 100644
> --- a/arch/x86/kernel/fpu/core.c
> +++ b/arch/x86/kernel/fpu/core.c
[ ... ]
> @@ -383,13 +396,15 @@ int fpu_swap_kvm_fpstate(struct fpu_guest *guest_fpu, bool enter_guest)
>
> /* Swap fpstate */
> if (enter_guest) {
> - fpu->__task_fpstate = cur_fps;
> + WRITE_ONCE(fpu->__task_fpstate, cur_fps);
> + barrier();
> fpu->fpstate = guest_fps;
> guest_fps->in_use = true;
> } else {
> guest_fps->in_use = false;
> fpu->fpstate = fpu->__task_fpstate;
> - fpu->__task_fpstate = NULL;
> + barrier();
> + WRITE_ONCE(fpu->__task_fpstate, NULL);
[Severity: High]
Can guest FPU state leak into host perf samples during this window?
The commit message mentions that subsequent patches will use this guarantee
in NMI context by checking TIF_NEED_FPU_LOAD before retrieving user FPU
state from the saved task FPU state.
However, during KVM guest execution and within the VM-exit path here,
TIF_NEED_FPU_LOAD is 0 because it was cleared on guest entry and is not set
by KVM.
If an NMI hits here before restore_fpregs_from_fpstate() restores the host
state, would the NMI handler bypass the fpu->__task_fpstate check because
TIF_NEED_FPU_LOAD is 0?
arch/x86/events/core.c:x86_pmu_update_user_xregs() {
...
if (user_mask && test_thread_flag(TIF_NEED_FPU_LOAD)) {
perf_regs = container_of(data->regs_user.regs,
struct x86_perf_regs, regs);
fpu = x86_task_fpu(current);
/*
* If __task_fpstate is set, it holds the right pointer,
* otherwise fpstate will.
*/
fps = READ_ONCE(fpu->__task_fpstate);
...
}
If this memory check is skipped, wouldn't the NMI handler fall back to
reading directly from the hardware registers, which still contain the guest
FPU state at this point in fpu_swap_kvm_fpstate()?
> }
>
> cur_fps = fpu->fpstate;
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260706015439.3040804-1-dapeng1.mi@linux.intel.com?part=8
next prev parent reply other threads:[~2026-07-06 2:22 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-06 1:54 [Patch v9 00/24] Support SIMD/eGPRs/SSP registers sampling for perf Dapeng Mi
2026-07-06 1:54 ` [Patch v9 01/24] perf/x86: Fix two error-path and hybrid PMU guard issues Dapeng Mi
2026-07-06 2:21 ` sashiko-bot
2026-07-06 8:05 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 02/24] perf/x86: Move hybrid PMU initialization before x86_pmu_starting_cpu() Dapeng Mi
2026-07-06 2:18 ` sashiko-bot
2026-07-06 8:33 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 03/24] perf/x86/intel: Enable large PEBS sampling for XMMs Dapeng Mi
2026-07-06 1:54 ` [Patch v9 04/24] perf/x86/intel: Convert x86_perf_regs to per-cpu variables Dapeng Mi
2026-07-06 1:54 ` [Patch v9 05/24] perf: Eliminate duplicate arch-specific function definitions Dapeng Mi
2026-07-06 1:54 ` [Patch v9 06/24] perf/x86: Use x86_perf_regs in NMI handlers Dapeng Mi
2026-07-06 2:31 ` sashiko-bot
2026-07-06 8:43 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 07/24] x86/fpu/xstate: Add xsaves_nmi() helper Dapeng Mi
2026-07-06 2:18 ` sashiko-bot
2026-07-06 9:09 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 08/24] x86/fpu: Add update_fpu_state_and_flag() helper Dapeng Mi
2026-07-06 2:22 ` sashiko-bot [this message]
2026-07-06 9:15 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 09/24] perf: Move and enhance has_extended_regs() for arch-specific use Dapeng Mi
2026-07-06 1:54 ` [Patch v9 10/24] perf/x86/intel: Consolidate PMU capability updates Dapeng Mi
2026-07-06 1:54 ` [Patch v9 11/24] perf/x86: Enable XMM register sampling for non-PEBS events Dapeng Mi
2026-07-06 2:34 ` sashiko-bot
2026-07-06 9:47 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 12/24] perf/x86: Enable XMM register sampling for REGS_USER case Dapeng Mi
2026-07-06 2:35 ` sashiko-bot
2026-07-07 9:59 ` Mi, Dapeng
2026-07-08 0:56 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 13/24] perf: Add sampling support for SIMD registers Dapeng Mi
2026-07-06 2:34 ` sashiko-bot
2026-07-08 1:13 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 14/24] perf/x86: Support XMM sampling using sample_simd_vec_reg_* fields Dapeng Mi
2026-07-06 6:45 ` sashiko-bot
2026-07-08 1:27 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 15/24] perf/x86: Support YMM " Dapeng Mi
2026-07-06 1:54 ` [Patch v9 16/24] perf/x86: Support ZMM " Dapeng Mi
2026-07-06 1:54 ` [Patch v9 17/24] perf/x86: Support OPMASK sampling using sample_simd_pred_reg_* fields Dapeng Mi
2026-07-06 1:54 ` [Patch v9 18/24] perf: Enhance perf_reg_validate() with simd_enabled argument Dapeng Mi
2026-07-06 1:54 ` [Patch v9 19/24] perf/x86: Support eGPRs sampling using sample_regs_* fields Dapeng Mi
2026-07-06 1:54 ` [Patch v9 20/24] perf/x86: Support SSP " Dapeng Mi
2026-07-06 1:54 ` [Patch v9 21/24] perf/x86/intel: Support arch-PEBS based SIMD/eGPRs/SSP sampling Dapeng Mi
2026-07-06 1:54 ` [Patch v9 22/24] perf/x86/intel: Enable PERF_PMU_CAP_SIMD_REGS capability Dapeng Mi
2026-07-06 2:57 ` sashiko-bot
2026-07-08 1:51 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 23/24] perf/x86: Activate back-to-back NMI detection for arch-PEBS induced NMIs Dapeng Mi
2026-07-06 1:54 ` [Patch v9 24/24] perf/x86/intel: Add sanity check for PEBS fragment size Dapeng Mi
2026-07-06 5:04 ` sashiko-bot
2026-07-08 2:03 ` Mi, Dapeng
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260706022254.214481F000E9@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=dapeng1.mi@linux.intel.com \
--cc=linux-perf-users@vger.kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.