From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: sashiko-reviews@lists.linux.dev
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [Patch v9 14/24] perf/x86: Support XMM sampling using sample_simd_vec_reg_* fields
Date: Wed, 8 Jul 2026 09:27:22 +0800 [thread overview]
Message-ID: <73610adf-97b4-4144-87a3-3053be778cbf@linux.intel.com> (raw)
In-Reply-To: <20260706064600.6D7BA1F000E9@smtp.kernel.org>
On 7/6/2026 2:45 PM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
>
> New issues:
> - [Medium] Validation logic unconditionally evaluates flag-gated syscall parameters (`vec_mask_user`, `pred_mask_user`) without checking their respective flag gates, leading to validation bypasses due to uninitialized garbage.
>
> Pre-existing issues:
> - [Critical] The functions `perf_reg_value` and `perf_simd_reg_value` unsafely assume the provided `pt_regs *` is always embedded within an `x86_perf_regs` structure, leading to out-of-bounds reads and arbitrary pointer dereferences for software events and `PERF_SAMPLE_REGS_USER`.
> --
>
> commit 9c74aceec4401218b750679a5b08ba8009aa85a3
> Author: Dapeng Mi <dapeng1.mi@linux.intel.com>
>
> perf/x86: Support XMM sampling using sample_simd_vec_reg_* fields
>
> This commit adds support for sampling XMM registers by introducing a new ABI
> field and extracting XMM values through the sample_simd_vec_reg_* fields. It
> adds a new perf_simd_reg_value function to retrieve the values and updates
> the SIMD registration validation logic.
>
>> diff --git a/arch/x86/kernel/perf_regs.c b/arch/x86/kernel/perf_regs.c
>> index 81204cb7f7239..8514baefb400e 100644
>> --- a/arch/x86/kernel/perf_regs.c
>> +++ b/arch/x86/kernel/perf_regs.c
> [ ... ]
>
>> @@ -63,6 +63,9 @@ u64 perf_reg_value(struct pt_regs *regs, int idx)
>>
>> if (idx >= PERF_REG_X86_XMM0 && idx < PERF_REG_X86_XMM_MAX) {
>> perf_regs = container_of(regs, struct x86_perf_regs, regs);
>> + /* SIMD registers are moved to dedicated sample_simd_vec_reg */
>> + if (perf_regs->abi & PERF_SAMPLE_REGS_ABI_SIMD)
> [Severity: Critical]
> This isn't a bug introduced by this patch, but evaluating perf_regs->abi
> here relies on an unsafe cast.
>
> For tracepoints and PERF_SAMPLE_REGS_USER, regs points to a bare pt_regs
> instance rather than an embedded x86_perf_regs struct. The container_of()
> cast accesses memory outside the bounds of the pt_regs struct.
>
> Could this allow an attacker to control the out-of-bounds pointers (like
> xmm_regs) and read arbitrary kernel memory into the perf ring buffer?
This is not a bug. The software PMU has no such caps,
PERF_PMU_CAP_EXTENDED_REGS or PERF_PMU_CAP_SIMD_REGS, so if software events
want to sample these extended regs, the event creation would fail.
>
>> + return 0;
>> if (!perf_regs->xmm_regs)
>> return 0;
>> return perf_regs->xmm_regs[idx - PERF_REG_X86_XMM0];
> [ ... ]
>
>> @@ -74,6 +77,77 @@ u64 perf_reg_value(struct pt_regs *regs, int idx)
>> return regs_get_register(regs, pt_regs_offset[idx]);
>> }
>>
>> +u64 perf_simd_reg_value(struct pt_regs *regs, int idx,
>> + u16 qwords_idx, bool pred)
>> +{
>> + struct x86_perf_regs *perf_regs =
>> + container_of(regs, struct x86_perf_regs, regs);
>> +
>> + if (!(perf_regs->abi & PERF_SAMPLE_REGS_ABI_SIMD))
> [Severity: Critical]
> This is a pre-existing issue, but this new code copies the same unsafe
> container_of() cast pattern.
>
> Since regs is not actually embedded in an x86_perf_regs struct when
> called for PERF_SAMPLE_REGS_USER, reading perf_regs->abi reads
> out-of-bounds memory.
Ditto.
>
>> + return 0;
>> +
>> + if (pred)
>> + return 0;
> [ ... ]
>
>> +int perf_simd_reg_validate(u64 sample_type, u16 simd_enabled,
>> + u16 vec_qwords, u64 vec_mask_intr,
>> + u64 vec_mask_user, u16 pred_qwords,
>> + u32 pred_mask_intr, u32 pred_mask_user)
>> +{
>> + u64 size = 0;
>> +
>> + if (!(sample_type &
>> + (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)))
>> + return 0;
>> +
>> + if (!simd_enabled)
>> + return 0;
>> +
>> + if (vec_qwords) {
>> + if (vec_qwords != PERF_X86_XMM_QWORDS)
>> + return -EINVAL;
>> + if (!vec_mask_intr && !vec_mask_user)
>> + return -EINVAL;
> [Severity: Medium]
> Does this logic evaluate flag-gated parameters without checking their
> respective flag gates?
>
> PERF_SAMPLE_REGS_INTR and PERF_SAMPLE_REGS_USER are independent flags. If a
> user sets INTR but not USER, vec_mask_user is outside its flag gate and
> can contain arbitrary garbage from userspace.
>
> If vec_mask_intr is 0 (an invalid configuration), but the garbage in
> vec_mask_user is non-zero, this check passes and the validation is bypassed.
>
> Should these masks be validated against their respective sample_type flags
> before checking if they are both empty?
Yes, the perf_simd_reg_validate() would be enhanced to validate the
REGS_USER and REGS_INTR configuration separately.
Thanks.
>
>> + if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
>> + (vec_mask_intr & ~PERF_X86_SIMD_VEC_MASK))
>> + return -EINVAL;
next prev parent reply other threads:[~2026-07-08 1:27 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-06 1:54 [Patch v9 00/24] Support SIMD/eGPRs/SSP registers sampling for perf Dapeng Mi
2026-07-06 1:54 ` [Patch v9 01/24] perf/x86: Fix two error-path and hybrid PMU guard issues Dapeng Mi
2026-07-06 2:21 ` sashiko-bot
2026-07-06 8:05 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 02/24] perf/x86: Move hybrid PMU initialization before x86_pmu_starting_cpu() Dapeng Mi
2026-07-06 2:18 ` sashiko-bot
2026-07-06 8:33 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 03/24] perf/x86/intel: Enable large PEBS sampling for XMMs Dapeng Mi
2026-07-06 1:54 ` [Patch v9 04/24] perf/x86/intel: Convert x86_perf_regs to per-cpu variables Dapeng Mi
2026-07-06 1:54 ` [Patch v9 05/24] perf: Eliminate duplicate arch-specific function definitions Dapeng Mi
2026-07-06 1:54 ` [Patch v9 06/24] perf/x86: Use x86_perf_regs in NMI handlers Dapeng Mi
2026-07-06 2:31 ` sashiko-bot
2026-07-06 8:43 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 07/24] x86/fpu/xstate: Add xsaves_nmi() helper Dapeng Mi
2026-07-06 2:18 ` sashiko-bot
2026-07-06 9:09 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 08/24] x86/fpu: Add update_fpu_state_and_flag() helper Dapeng Mi
2026-07-06 2:22 ` sashiko-bot
2026-07-06 9:15 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 09/24] perf: Move and enhance has_extended_regs() for arch-specific use Dapeng Mi
2026-07-06 1:54 ` [Patch v9 10/24] perf/x86/intel: Consolidate PMU capability updates Dapeng Mi
2026-07-06 1:54 ` [Patch v9 11/24] perf/x86: Enable XMM register sampling for non-PEBS events Dapeng Mi
2026-07-06 2:34 ` sashiko-bot
2026-07-06 9:47 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 12/24] perf/x86: Enable XMM register sampling for REGS_USER case Dapeng Mi
2026-07-06 2:35 ` sashiko-bot
2026-07-07 9:59 ` Mi, Dapeng
2026-07-08 0:56 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 13/24] perf: Add sampling support for SIMD registers Dapeng Mi
2026-07-06 2:34 ` sashiko-bot
2026-07-08 1:13 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 14/24] perf/x86: Support XMM sampling using sample_simd_vec_reg_* fields Dapeng Mi
2026-07-06 6:45 ` sashiko-bot
2026-07-08 1:27 ` Mi, Dapeng [this message]
2026-07-06 1:54 ` [Patch v9 15/24] perf/x86: Support YMM " Dapeng Mi
2026-07-06 1:54 ` [Patch v9 16/24] perf/x86: Support ZMM " Dapeng Mi
2026-07-06 1:54 ` [Patch v9 17/24] perf/x86: Support OPMASK sampling using sample_simd_pred_reg_* fields Dapeng Mi
2026-07-06 1:54 ` [Patch v9 18/24] perf: Enhance perf_reg_validate() with simd_enabled argument Dapeng Mi
2026-07-06 1:54 ` [Patch v9 19/24] perf/x86: Support eGPRs sampling using sample_regs_* fields Dapeng Mi
2026-07-06 1:54 ` [Patch v9 20/24] perf/x86: Support SSP " Dapeng Mi
2026-07-06 1:54 ` [Patch v9 21/24] perf/x86/intel: Support arch-PEBS based SIMD/eGPRs/SSP sampling Dapeng Mi
2026-07-06 1:54 ` [Patch v9 22/24] perf/x86/intel: Enable PERF_PMU_CAP_SIMD_REGS capability Dapeng Mi
2026-07-06 2:57 ` sashiko-bot
2026-07-08 1:51 ` Mi, Dapeng
2026-07-06 1:54 ` [Patch v9 23/24] perf/x86: Activate back-to-back NMI detection for arch-PEBS induced NMIs Dapeng Mi
2026-07-06 1:54 ` [Patch v9 24/24] perf/x86/intel: Add sanity check for PEBS fragment size Dapeng Mi
2026-07-06 5:04 ` sashiko-bot
2026-07-08 2:03 ` Mi, Dapeng
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