Re: [PATCH v7 03/13] dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller - sashiko-bot

From: sashiko-bot@kernel.org
To: "Stefan Dösinger" <stefandoesinger@gmail.com>
Cc: vkoul@kernel.org, linux-phy@lists.infradead.org,
	neil.armstrong@linaro.org, olteanv@gmail.com, robh@kernel.org,
	conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v7 03/13] dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller
Date: Thu, 16 Jul 2026 22:25:23 +0000	[thread overview]
Message-ID: <20260716222523.BC76A1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260717-zx29clk-v7-3-408411cfcf36@gmail.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The newly added clock and reset macro definitions overlap with existing definitions for a different controller (topcrm) in the same header files, using the same `ZX297520V3_` prefix without disambiguation.
--

--- Patch [3]: [PATCH v7 03/13] dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller ---
commit 5ec0de6373fd034a146a7bae84009d3814552ed6
Author: Stefan Dösinger <stefandoesinger@gmail.com>

dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller

This controller contains clocks and resets for high speed devices on the
zx297520v3 board and hardware spinlocks that I expect will be necessary
to communicate correctly with the LTE DSP firmware blob. A simple MFD driver
will instantiate independent clock, reset and hwlock drivers.

> diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bindings/clock/zte,zx297520v3-clk.h
> index 1f010ff4e6ca6..09ee3de679d96 100644
> --- a/include/dt-bindings/clock/zte,zx297520v3-clk.h
> +++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h
> @@ -63,4 +63,45 @@
>  #define ZX297520V3_HSIC_WCLK			55
>  #define ZX297520V3_HSIC_PCLK			56
>  
> +#define ZX297520V3_SYS_TIMER_WCLK		1
> +#define ZX297520V3_CPU_WCLK			2

[Severity: Low]
Could these new clock macros overlap with the existing ones in this header
and cause confusion?

The existing topcrm clocks in this header also start at 1 and use the same
ZX297520V3_ prefix, for example ZX297520V3_M0_WCLK. Is there a risk that a
developer might accidentally use a matrixcrm clock macro for a topcrm node
or vice versa? If they do, the C preprocessor will substitute the
overlapping integer without error.

Would it be safer to add a distinct prefix for the matrixcrm clocks, such
as ZX297520V3_MATRIX_?

[ ... ]

> diff --git a/include/dt-bindings/reset/zte,zx297520v3-reset.h b/include/dt-bindings/reset/zte,zx297520v3-reset.h
> index 43db72bb59de0..4682d4a599c6a 100644
> --- a/include/dt-bindings/reset/zte,zx297520v3-reset.h
> +++ b/include/dt-bindings/reset/zte,zx297520v3-reset.h
> @@ -29,4 +29,16 @@
>  #define ZX297520V3_HSIC_PHY_RESET		20
>  #define ZX297520V3_HSIC_RESET			21
>  
> +#define ZX297520V3_CPU_RESET			0
> +#define ZX297520V3_DDR_CTRL_RESET		1

[Severity: Low]
Does this identical prefix also cause an overlap risk for reset definitions?

The new matrixcrm resets start at 0 and use the ZX297520V3_ prefix, which
overlaps with the existing topcrm resets like ZX297520V3_ZSP_RESET.

Could adding a matrixcrm-specific prefix here also help prevent potential
device tree configuration errors?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260717-zx29clk-v7-0-408411cfcf36@gmail.com?part=3

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