Re: [PATCH v7 09/13] clk: zte: Introduce a driver for zx297520v3 top clocks - sashiko-bot

From: sashiko-bot@kernel.org
To: "Stefan Dösinger" <stefandoesinger@gmail.com>
Cc: devicetree@vger.kernel.org, olteanv@gmail.com, robh@kernel.org,
	vkoul@kernel.org, neil.armstrong@linaro.org,
	linux-phy@lists.infradead.org, conor+dt@kernel.org
Subject: Re: [PATCH v7 09/13] clk: zte: Introduce a driver for zx297520v3 top clocks
Date: Thu, 16 Jul 2026 22:42:41 +0000	[thread overview]
Message-ID: <20260716224241.BAFFF1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260717-zx29clk-v7-9-408411cfcf36@gmail.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Using `clk_main[0]` to initialize the `.parent` field in the `zx297520v3_top_gates` static array is a violation of ISO C rules for constant expressions, resulting in a hard compile error.
--

--- Patch [9]: [PATCH v7 09/13] clk: zte: Introduce a driver for zx297520v3 top clocks ---
commit 8a7fee3879cf08b60157cde425eed4bbaa05fcb1
Author: Stefan Dösinger <stefandoesinger@gmail.com>

clk: zte: Introduce a driver for zx297520v3 top clocks

This commit introduces a clock driver for the ZTE zx297520v3 SoC top clocks.
It supports core devices such as PLLs, the AHB bus, timers, the USB
controller, and the Cortex M0 processor.

> diff --git a/drivers/clk/zte/clk-zx297520v3.c b/drivers/clk/zte/clk-zx297520v3.c
> new file mode 100644
> index 0000000000000..20ff00ba5f670
> --- /dev/null
> +++ b/drivers/clk/zte/clk-zx297520v3.c

[ ... ]

> +static const struct zx_gate_desc zx297520v3_top_gates[] = {

[ ... ]

> +	/* AHB clock gates: Disabling these cuts off the A53 from register access into 0x130000/
> +	 * 0x140000, including the topcrm region, so it can't be re-enabled. Mark them critical for
> +	 * that reason.
> +	 *
> +	 * Gating this off does not stop the M0 rproc, nor does it stop M0 from accessing topcrm. It
> +	 * does however gate off M0 from the AXI interconnect, so it can't read RAM, Matrix, etc. So
> +	 * these bits here merely gate the bus, not the actual devices.
> +	 */
> +	GATE(ZX297520V3_AHB_PCLK,          "ahb-pclk",       "ahb-mux",        0x54, 12,
> +		CLK_IS_CRITICAL),
> +	GATE(ZX297520V3_AHB_WCLK,          "ahb-wclk",       "m0-mux",         0x54, 13,
> +		CLK_IS_CRITICAL),
> +
> +	/* SRAM1 and 2 clocks. Leave them on for now, as turning them off carelessly hangs the M0 */
> +	GATE(ZX297520V3_SRAM1_PCLK,        "sram1-pclk",     clk_main[0],      0x54, 18,
> +		CLK_IS_CRITICAL),

[Severity: Low]
Does using clk_main[0] to initialize elements of a static array cause a build
failure?

In C, array accesses are not treated as constant expressions. Initializing the
zx297520v3_top_gates static array with clk_main[0] will cause the compiler
to fail with an "initializer element is not constant" error.

Could a string literal like "clock-26m" be used directly instead?

> +	GATE(ZX297520V3_SRAM2_PCLK,        "sram2-pclk",     clk_main[0],      0x54, 16,
> +		CLK_IS_CRITICAL),
> +
> +	/* Pinmux (AON, TOP, IOCFG but not PDCFG). Critical as well until we have a driver that
> +	 * consumes it. I don't think we'll realistically shut this off ever.
> +	 *
> +	 * Setting either bit 0 or 1 in register 0x58 makes the device work.
> +	 */
> +	GATE(ZX297520V3_PMM_WCLK,          "pmm-wclk",       clk_main[0],      0x58,  0,
> +		CLK_IS_CRITICAL),
> +	GATE(ZX297520V3_PMM_PCLK,          "pmm-pclk",       clk_main[0],      0x58,  1,
> +		CLK_IS_CRITICAL),

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260717-zx29clk-v7-0-408411cfcf36@gmail.com?part=9

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