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From: sashiko-bot@kernel.org
To: "Stefan Dösinger" <stefandoesinger@gmail.com>
Cc: vkoul@kernel.org, linux-phy@lists.infradead.org, robh@kernel.org,
	conor+dt@kernel.org, devicetree@vger.kernel.org,
	olteanv@gmail.com, neil.armstrong@linaro.org
Subject: Re: [PATCH v7 06/13] clk: zte: Add Clock registration infrastructure
Date: Thu, 16 Jul 2026 22:26:16 +0000	[thread overview]
Message-ID: <20260716222616.8612B1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260717-zx29clk-v7-6-408411cfcf36@gmail.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] In `zx_clk_common_probe()`, the error path for `data->init(map)` incorrectly returns `PTR_ERR(clk)` instead of propagating the actual error code `res`.
--

--- Patch [6]: [PATCH v7 06/13] clk: zte: Add Clock registration infrastructure ---
commit 377a6af7769b840d87a85b32af3001fd5f4431dd
Author: Stefan Dösinger <stefandoesinger@gmail.com>

clk: zte: Add Clock registration infrastructure

This commit adds the common clock registration infrastructure for ZTE SoCs.
It includes support for registering PLLs, muxes, dividers, and gates using
regmap, and introduces a common probe function to initialize them.

> diff --git a/drivers/clk/zte/clk-zx.c b/drivers/clk/zte/clk-zx.c
> new file mode 100644
> index 0000000000000..db4fad2b4b056
> --- /dev/null
> +++ b/drivers/clk/zte/clk-zx.c
[ ... ]
> @@ -0,0 +1,155 @@
[ ... ]
> +int zx_clk_common_probe(struct device *dev, struct device_node *of_node,
> +			const struct zx_clk_data *data)
> +{
[ ... ]
> +	if (data->init) {
> +		res = data->init(map);
> +		if (res)
> +			return dev_err_probe(dev, PTR_ERR(clk), "Controller init failure\n");

[Severity: High]
Does this code pass the wrong error code to dev_err_probe() in the
zx_clk_common_probe() error path?

When data->init(map) fails, it returns a non-zero error code into res.
However, the error handling block incorrectly evaluates and returns
PTR_ERR(clk).

Since clk is merely an iteration variable from the preceding loops, it could
be completely uninitialized if num_inputs_enable and num_inputs are 0, which
might trick the driver core into assuming the probe succeeded despite
initialization failing.

If the loops did execute successfully, clk holds a valid pointer, and
PTR_ERR(clk) will return a random large number depending on the pointer's
memory address, resulting in a meaningless error code.

Should this return res instead of PTR_ERR(clk)?

> +	}
> +
> +	res = zx_clk_register_plls(dev, map, data->plls, data->num_plls);
> +	if (res)
> +		return res;
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260717-zx29clk-v7-0-408411cfcf36@gmail.com?part=6

WARNING: multiple messages have this Message-ID (diff)
From: sashiko-bot@kernel.org
To: "Stefan Dösinger" <stefandoesinger@gmail.com>
Cc: vkoul@kernel.org, linux-phy@lists.infradead.org, robh@kernel.org,
	conor+dt@kernel.org, devicetree@vger.kernel.org,
	olteanv@gmail.com, neil.armstrong@linaro.org
Subject: Re: [PATCH v7 06/13] clk: zte: Add Clock registration infrastructure
Date: Thu, 16 Jul 2026 22:26:16 +0000	[thread overview]
Message-ID: <20260716222616.8612B1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260717-zx29clk-v7-6-408411cfcf36@gmail.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] In `zx_clk_common_probe()`, the error path for `data->init(map)` incorrectly returns `PTR_ERR(clk)` instead of propagating the actual error code `res`.
--

--- Patch [6]: [PATCH v7 06/13] clk: zte: Add Clock registration infrastructure ---
commit 377a6af7769b840d87a85b32af3001fd5f4431dd
Author: Stefan Dösinger <stefandoesinger@gmail.com>

clk: zte: Add Clock registration infrastructure

This commit adds the common clock registration infrastructure for ZTE SoCs.
It includes support for registering PLLs, muxes, dividers, and gates using
regmap, and introduces a common probe function to initialize them.

> diff --git a/drivers/clk/zte/clk-zx.c b/drivers/clk/zte/clk-zx.c
> new file mode 100644
> index 0000000000000..db4fad2b4b056
> --- /dev/null
> +++ b/drivers/clk/zte/clk-zx.c
[ ... ]
> @@ -0,0 +1,155 @@
[ ... ]
> +int zx_clk_common_probe(struct device *dev, struct device_node *of_node,
> +			const struct zx_clk_data *data)
> +{
[ ... ]
> +	if (data->init) {
> +		res = data->init(map);
> +		if (res)
> +			return dev_err_probe(dev, PTR_ERR(clk), "Controller init failure\n");

[Severity: High]
Does this code pass the wrong error code to dev_err_probe() in the
zx_clk_common_probe() error path?

When data->init(map) fails, it returns a non-zero error code into res.
However, the error handling block incorrectly evaluates and returns
PTR_ERR(clk).

Since clk is merely an iteration variable from the preceding loops, it could
be completely uninitialized if num_inputs_enable and num_inputs are 0, which
might trick the driver core into assuming the probe succeeded despite
initialization failing.

If the loops did execute successfully, clk holds a valid pointer, and
PTR_ERR(clk) will return a random large number depending on the pointer's
memory address, resulting in a meaningless error code.

Should this return res instead of PTR_ERR(clk)?

> +	}
> +
> +	res = zx_clk_register_plls(dev, map, data->plls, data->num_plls);
> +	if (res)
> +		return res;
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260717-zx29clk-v7-0-408411cfcf36@gmail.com?part=6

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

  reply	other threads:[~2026-07-16 22:26 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-16 21:35 [PATCH v7 00/13] ZTE zx297520v3 clock bindings and driver Stefan Dösinger
2026-07-16 21:35 ` Stefan Dösinger
2026-07-16 21:35 ` [PATCH v7 01/13] dt-bindings: phy: Add zx297520v3 USB phy documentation Stefan Dösinger
2026-07-16 21:35   ` Stefan Dösinger
2026-07-16 22:24   ` sashiko-bot
2026-07-16 22:24     ` sashiko-bot
2026-07-17  0:05   ` Rob Herring (Arm)
2026-07-17  0:05     ` Rob Herring (Arm)
2026-07-17  6:32   ` Krzysztof Kozlowski
2026-07-17  6:32     ` Krzysztof Kozlowski
2026-07-16 21:35 ` [PATCH v7 02/13] dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller Stefan Dösinger
2026-07-16 21:35   ` Stefan Dösinger
2026-07-17  0:05   ` Rob Herring (Arm)
2026-07-17  0:05     ` Rob Herring (Arm)
2026-07-17  6:36   ` Krzysztof Kozlowski
2026-07-17  6:36     ` Krzysztof Kozlowski
2026-07-16 21:35 ` [PATCH v7 03/13] dt-bindings: clk: zte: Add zx297520v3 matrix " Stefan Dösinger
2026-07-16 21:35   ` Stefan Dösinger
2026-07-16 22:25   ` sashiko-bot
2026-07-16 22:25     ` sashiko-bot
2026-07-16 21:35 ` [PATCH v7 04/13] dt-bindings: clk: zte: Add zx297520v3 LSP " Stefan Dösinger
2026-07-16 21:35   ` Stefan Dösinger
2026-07-16 21:35 ` [PATCH v7 05/13] mfd: zx297520v3: Add a clock and reset MFD driver Stefan Dösinger
2026-07-16 21:35   ` Stefan Dösinger
2026-07-16 22:24   ` sashiko-bot
2026-07-16 22:24     ` sashiko-bot
2026-07-16 21:35 ` [PATCH v7 06/13] clk: zte: Add Clock registration infrastructure Stefan Dösinger
2026-07-16 21:35   ` Stefan Dösinger
2026-07-16 22:26   ` sashiko-bot [this message]
2026-07-16 22:26     ` sashiko-bot
2026-07-16 21:35 ` [PATCH v7 07/13] clk: zte: Add regmap based clocks Stefan Dösinger
2026-07-16 21:35   ` Stefan Dösinger
2026-07-16 21:35 ` [PATCH v7 08/13] clk: zte: Add zx PLL support infrastructure Stefan Dösinger
2026-07-16 21:35   ` Stefan Dösinger
2026-07-16 22:34   ` sashiko-bot
2026-07-16 22:34     ` sashiko-bot
2026-07-16 21:35 ` [PATCH v7 09/13] clk: zte: Introduce a driver for zx297520v3 top clocks Stefan Dösinger
2026-07-16 21:35   ` Stefan Dösinger
2026-07-16 22:42   ` sashiko-bot
2026-07-16 22:42     ` sashiko-bot
2026-07-16 22:00 ` [PATCH v7 10/13] clk: zte: Introduce a driver for zx297520v3 matrix clocks Stefan Dösinger
2026-07-16 22:00 ` [PATCH v7 12/13] reset: zte: Add a zx297520v3 reset driver Stefan Dösinger
2026-07-16 22:00 ` [PATCH v7 13/13] ARM: dts: zte: Declare zx297520v3 CRM device nodes Stefan Dösinger
2026-07-16 22:17 ` [PATCH v7 11/13] clk: zte: Introduce a driver for zx297520v3 LSP clocks Stefan Dösinger
2026-07-17  6:37 ` [PATCH v7 00/13] ZTE zx297520v3 clock bindings and driver Krzysztof Kozlowski
2026-07-17  6:37   ` Krzysztof Kozlowski

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