[PATCH 00/13] cpus: Constify @cpu in SysemuCPUOps::has_work() handler

[PATCH 00/13] cpus: Constify @cpu in SysemuCPUOps::has_work() handler

[Philippe Mathieu-Daudé]

- Patches 1-8 trivially add const qualifier for various
  cpu_is/has() getters
- Patch 9 adds const-qualified variants of cpu_env() and
  env_archcpu(). Not sure if this is a good idea so marked
  as RFC.
- Patches 10-12 complete the cpu_is/has() getters const
  conversion using the new env_archcpu_const() variant
- Patch 13 finally convert the SysemuCPUOps::has_work
  hook and all target implementations.

No functional change; purely const-correctness improvment
to enforce has_work() callees don't mutate CPUState.

Build-tested.

Based-on: <20260819145649.23439-1-philmd@oss.qualcomm.com>
  "Make halt-to-exec transition explicit and remove cpu_exec_halt"

Philippe Mathieu-Daudé (13):
  target/avr: Constify CPUAVRState for some cpu_*() getters
  target/i386: Constify CPU*State for cpu_*_interrupt() getters
  target/loongarch: Constify CPULoongArchState for various cpu_*()
    getters
  target/mips: Constify CPUMIPSState for various cpu_*() getters
  target/s390x: Constify S390CPU for cpu_has_*() getters
  target/riscv: Constify @iprio argument in riscv_cpu_pending_to_irq()
  target/riscv: Constify CPURISCVState for various cpu_*() getters
  target/sparc: Constify CPUSPARCState for various cpu_*() getters
  cpus: Add const-qualified CPU environment accessors
  target/riscv: Constify CPURISCVState for various cpu_*() getters
  target/hexagon: Constify CPUHexagonState in
    hexagon_thread_is_enabled()
  target/mips: Constify CPUMIPSState in mips_vpe_active()
  cpus: Constify @cpu in SysemuCPUOps::has_work() handler

 include/exec/cpu-common.h        | 11 +++++++++++
 include/hw/core/cpu.h            |  6 ++++++
 include/hw/core/sysemu-cpu-ops.h |  4 ++--
 target/avr/cpu.h                 |  6 +++---
 target/hexagon/cpu.h             |  2 +-
 target/i386/cpu.h                |  4 ++--
 target/loongarch/cpu.h           |  6 +++---
 target/loongarch/internals.h     |  4 ++--
 target/mips/cpu.h                |  6 +++---
 target/mips/internal.h           | 10 +++++-----
 target/riscv/cpu.h               | 31 ++++++++++++++++---------------
 target/riscv/internals.h         |  2 +-
 target/s390x/cpu.h               |  2 +-
 target/s390x/s390x-internal.h    | 14 +++++++-------
 target/sparc/cpu.h               | 12 ++++++------
 target/alpha/cpu.c               |  2 +-
 target/arm/cpu.c                 |  4 ++--
 target/avr/cpu.c                 |  5 +++--
 target/hexagon/cpu.c             |  8 ++++----
 target/hppa/cpu.c                |  2 +-
 target/i386/cpu.c                |  8 ++++----
 target/loongarch/cpu.c           |  6 +++---
 target/m68k/cpu.c                |  2 +-
 target/microblaze/cpu.c          |  2 +-
 target/mips/cpu.c                |  4 ++--
 target/or1k/cpu.c                |  2 +-
 target/ppc/cpu_init.c            |  2 +-
 target/riscv/cpu.c               | 14 +++++++-------
 target/rx/cpu.c                  |  2 +-
 target/s390x/cpu-system.c        |  2 +-
 target/s390x/interrupt.c         | 22 +++++++++++-----------
 target/sh4/cpu.c                 |  2 +-
 target/sparc/cpu.c               |  4 ++--
 target/tricore/cpu.c             |  4 ++--
 target/xtensa/cpu.c              |  4 ++--
 35 files changed, 120 insertions(+), 101 deletions(-)

-- 
2.53.0

[PATCH 01/13] target/avr: Constify CPUAVRState for some cpu_*() getters

[Philippe Mathieu-Daudé]

Add the const qualifier to CPUAVRState when the
argument is accessed without modification.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
 target/avr/cpu.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index a818db753b2..1e4e839bd83 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -183,7 +183,7 @@ int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 int avr_print_insn(bfd_vma addr, disassemble_info *info);
 vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr);
 
-static inline int avr_feature(CPUAVRState *env, AVRFeature feature)
+static inline int avr_feature(const CPUAVRState *env, AVRFeature feature)
 {
     return (env->features & (1U << feature)) != 0;
 }
@@ -204,12 +204,12 @@ enum {
     TB_FLAGS_SKIP = 2,
 };
 
-static inline int cpu_interrupts_enabled(CPUAVRState *env)
+static inline int cpu_interrupts_enabled(const CPUAVRState *env)
 {
     return env->sregI != 0;
 }
 
-static inline uint8_t cpu_get_sreg(CPUAVRState *env)
+static inline uint8_t cpu_get_sreg(const CPUAVRState *env)
 {
     return (env->sregC) << 0
          | (env->sregZ) << 1
-- 
2.53.0

[PATCH 02/13] target/i386: Constify CPU*State for cpu_*_interrupt() getters

[Philippe Mathieu-Daudé]

x86_cpu_pending_interrupt() and x86_cpu_interrupts_enabled()
only read CPU state without modification, add the const
qualifiers to CPUState and CPUX86State parameters.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
 target/i386/cpu.h | 4 ++--
 target/i386/cpu.c | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e6a197602d8..72adf075bfd 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2584,7 +2584,7 @@ void x86_cpu_gdb_init(CPUState *cs);
 int cpu_x86_support_mca_broadcast(CPUX86State *env);
 
 #ifndef CONFIG_USER_ONLY
-int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
+int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request);
 
 bool x86_cpu_translate_for_debug(CPUState *cpu, vaddr addr,
                                  TranslateForDebugResult *result);
@@ -3092,7 +3092,7 @@ static inline bool ctl_has_irq(CPUX86State *env)
     return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
 }
 
-static inline bool x86_cpu_interrupts_enabled(CPUX86State *env)
+static inline bool x86_cpu_interrupts_enabled(const CPUX86State *env)
 {
     return ((env->eflags & IF_MASK) &&
             !(env->hflags & HF_INHIBIT_IRQ_MASK)) ||
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e5ffb10d156..8777bcbae85 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -10601,10 +10601,10 @@ static vaddr x86_cpu_get_pc(CPUState *cs)
 }
 
 #if !defined(CONFIG_USER_ONLY)
-int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
+int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request)
 {
-    X86CPU *cpu = X86_CPU(cs);
-    CPUX86State *env = &cpu->env;
+    const X86CPU *cpu = X86_CPU(cs);
+    const CPUX86State *env = &cpu->env;
 
     if (interrupt_request & CPU_INTERRUPT_POLL) {
         return CPU_INTERRUPT_POLL;
-- 
2.53.0

[PATCH 03/13] target/loongarch: Constify CPULoongArchState for various cpu_*() getters

[Philippe Mathieu-Daudé]

Add the const qualifier to CPULoongArchStatCPUMIPSStatee when
the argument is accessed without modification.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
 target/loongarch/cpu.h       | 6 +++---
 target/loongarch/internals.h | 2 +-
 target/loongarch/cpu.c       | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index ad30c73167e..494744788b8 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -485,7 +485,7 @@ struct LoongArchCPUClass {
 #define MMU_USER_IDX     MMU_PLV_USER
 #define MMU_DA_IDX       4
 
-static inline CPUSysState *env_sys(CPULoongArchState *env)
+static inline CPUSysState *env_sys(const CPULoongArchState *env)
 {
     return env->sys_state;
 }
@@ -495,12 +495,12 @@ static inline void set_sys_state(CPULoongArchState *env, CPUSysState *sys)
     env->sys_state = sys;
 }
 
-static inline bool is_la64(CPULoongArchState *env)
+static inline bool is_la64(const CPULoongArchState *env)
 {
     return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;
 }
 
-static inline bool is_va32(CPULoongArchState *env)
+static inline bool is_va32(const CPULoongArchState *env)
 {
     /* VA32 if !LA64 or VA32L[1-3] */
     bool va32 = !is_la64(env);
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index e01dbed40f6..6a733e6c3a5 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -39,7 +39,7 @@ uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu);
 void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
                                                uint64_t value);
 bool loongarch_cpu_has_work(CPUState *cs);
-bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env);
+bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env);
 #endif /* !CONFIG_USER_ONLY */
 
 uint64_t read_fcc(CPULoongArchState *env);
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 8cd5bc18a3c..82ec35e081f 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -82,7 +82,7 @@ void loongarch_cpu_set_irq(void *opaque, int irq, int level)
 }
 
 /* Check if there is pending and not masked out interrupt */
-bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env)
+bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env)
 {
     uint32_t pending;
     uint32_t status;
-- 
2.53.0

[PATCH 04/13] target/mips: Constify CPUMIPSState for various cpu_*() getters

[Philippe Mathieu-Daudé]

Add the const qualifier to CPUMIPSState when
the argument is accessed without modification.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
 target/mips/cpu.h      | 6 +++---
 target/mips/internal.h | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 319147a948c..6404b342a5d 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1372,19 +1372,19 @@ static inline bool ase_3d_available(const CPUMIPSState *env)
 }
 
 /* Check presence of MSA implementation */
-static inline bool ase_msa_available(CPUMIPSState *env)
+static inline bool ase_msa_available(const CPUMIPSState *env)
 {
     return env->CP0_Config3 & (1 << CP0C3_MSAP);
 }
 
 /* Check presence of Loongson CSR instructions */
-static inline bool ase_lcsr_available(CPUMIPSState *env)
+static inline bool ase_lcsr_available(const CPUMIPSState *env)
 {
     return env->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP);
 }
 
 /* Check presence of multi-threading ASE implementation */
-static inline bool ase_mt_available(CPUMIPSState *env)
+static inline bool ase_mt_available(const CPUMIPSState *env)
 {
     return env->CP0_Config3 & (1 << CP0C3_MT);
 }
diff --git a/target/mips/internal.h b/target/mips/internal.h
index c5c286872eb..66e8c599b43 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -165,7 +165,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
 
 extern const VMStateDescription vmstate_mips_cpu;
 
-static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
+static inline bool cpu_mips_hw_interrupts_enabled(const CPUMIPSState *env)
 {
     return (env->CP0_Status & (1 << CP0St_IE)) &&
         !(env->CP0_Status & (1 << CP0St_EXL)) &&
@@ -180,7 +180,7 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
 }
 
 /* Check if there is pending and not masked out interrupt */
-static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
+static inline bool cpu_mips_hw_interrupts_pending(const CPUMIPSState *env)
 {
     int32_t pending;
     int32_t status;
@@ -281,7 +281,7 @@ static inline int mips_vpe_active(CPUMIPSState *env)
     return active;
 }
 
-static inline int mips_vp_active(CPUMIPSState *env)
+static inline int mips_vp_active(const CPUMIPSState *env)
 {
     CPUState *cs;
 
-- 
2.53.0

[PATCH 05/13] target/s390x: Constify S390CPU for cpu_has_*() getters

[Philippe Mathieu-Daudé]

Add the const qualifier to S390CPU when the argument
is accessed without modification.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
 target/s390x/cpu.h            |  2 +-
 target/s390x/s390x-internal.h | 12 ++++++------
 target/s390x/interrupt.c      | 22 +++++++++++-----------
 3 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index f55b79ef8ac..998bbb0d7ff 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -854,7 +854,7 @@ static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
     return 0;
 }
 #endif /* CONFIG_USER_ONLY */
-static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
+static inline uint8_t s390_cpu_get_state(const S390CPU *cpu)
 {
     return cpu->env.cpu_state;
 }
diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h
index 35d1e34ef4d..54b62808d83 100644
--- a/target/s390x/s390x-internal.h
+++ b/target/s390x/s390x-internal.h
@@ -334,12 +334,12 @@ void cpu_inject_clock_comparator(S390CPU *cpu);
 void cpu_inject_cpu_timer(S390CPU *cpu);
 void cpu_inject_emergency_signal(S390CPU *cpu, uint16_t src_cpu_addr);
 int cpu_inject_external_call(S390CPU *cpu, uint16_t src_cpu_addr);
-bool s390_cpu_has_io_int(S390CPU *cpu);
-bool s390_cpu_has_ext_int(S390CPU *cpu);
-bool s390_cpu_has_mcck_int(S390CPU *cpu);
-bool s390_cpu_has_int(S390CPU *cpu);
-bool s390_cpu_has_restart_int(S390CPU *cpu);
-bool s390_cpu_has_stop_int(S390CPU *cpu);
+bool s390_cpu_has_io_int(const S390CPU *cpu);
+bool s390_cpu_has_ext_int(const S390CPU *cpu);
+bool s390_cpu_has_mcck_int(const S390CPU *cpu);
+bool s390_cpu_has_int(const S390CPU *cpu);
+bool s390_cpu_has_restart_int(const S390CPU *cpu);
+bool s390_cpu_has_stop_int(const S390CPU *cpu);
 void cpu_inject_restart(S390CPU *cpu);
 void cpu_inject_stop(S390CPU *cpu);
 #endif /* CONFIG_USER_ONLY */
diff --git a/target/s390x/interrupt.c b/target/s390x/interrupt.c
index 1dca835c5d8..d7e3fd45e4b 100644
--- a/target/s390x/interrupt.c
+++ b/target/s390x/interrupt.c
@@ -139,10 +139,10 @@ void s390_crw_mchk(void)
     fsc->inject_crw_mchk(fs);
 }
 
-bool s390_cpu_has_mcck_int(S390CPU *cpu)
+bool s390_cpu_has_mcck_int(const S390CPU *cpu)
 {
     QEMUS390FLICState *flic = s390_get_qemu_flic(s390_get_flic());
-    CPUS390XState *env = &cpu->env;
+    const CPUS390XState *env = &cpu->env;
 
     if (!(env->psw.mask & PSW_MASK_MCHECK)) {
         return false;
@@ -157,10 +157,10 @@ bool s390_cpu_has_mcck_int(S390CPU *cpu)
     return false;
 }
 
-bool s390_cpu_has_ext_int(S390CPU *cpu)
+bool s390_cpu_has_ext_int(const S390CPU *cpu)
 {
     QEMUS390FLICState *flic = s390_get_qemu_flic(s390_get_flic());
-    CPUS390XState *env = &cpu->env;
+    const CPUS390XState *env = &cpu->env;
 
     if (!(env->psw.mask & PSW_MASK_EXT)) {
         return false;
@@ -199,10 +199,10 @@ bool s390_cpu_has_ext_int(S390CPU *cpu)
     return false;
 }
 
-bool s390_cpu_has_io_int(S390CPU *cpu)
+bool s390_cpu_has_io_int(const S390CPU *cpu)
 {
     QEMUS390FLICState *flic = s390_get_qemu_flic(s390_get_flic());
-    CPUS390XState *env = &cpu->env;
+    const CPUS390XState *env = &cpu->env;
 
     if (!(env->psw.mask & PSW_MASK_IO)) {
         return false;
@@ -211,21 +211,21 @@ bool s390_cpu_has_io_int(S390CPU *cpu)
     return qemu_s390_flic_has_io(flic, env->cregs[6]);
 }
 
-bool s390_cpu_has_restart_int(S390CPU *cpu)
+bool s390_cpu_has_restart_int(const S390CPU *cpu)
 {
-    CPUS390XState *env = &cpu->env;
+    const CPUS390XState *env = &cpu->env;
 
     return env->pending_int & INTERRUPT_RESTART;
 }
 
-bool s390_cpu_has_stop_int(S390CPU *cpu)
+bool s390_cpu_has_stop_int(const S390CPU *cpu)
 {
-    CPUS390XState *env = &cpu->env;
+    const CPUS390XState *env = &cpu->env;
 
     return env->pending_int & INTERRUPT_STOP;
 }
 
-bool s390_cpu_has_int(S390CPU *cpu)
+bool s390_cpu_has_int(const S390CPU *cpu)
 {
     if (!tcg_enabled()) {
         return false;
-- 
2.53.0

[PATCH 06/13] target/riscv: Constify @iprio argument in riscv_cpu_pending_to_irq()

[Philippe Mathieu-Daudé]

@iprio[] is an array only accessed read-only.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
 target/riscv/cpu.h | 2 +-
 target/riscv/cpu.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 376cff656fa..bb4c8563554 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -642,7 +642,7 @@ int riscv_cpu_sirq_pending(CPURISCVState *env);
 int riscv_cpu_vsirq_pending(CPURISCVState *env);
 int riscv_cpu_pending_to_irq(CPURISCVState *env,
                              int extirq, unsigned int extirq_def_prio,
-                             uint64_t pending, uint8_t *iprio);
+                             uint64_t pending, const uint8_t *iprio);
 
 
 bool riscv_cpu_fp_enabled(CPURISCVState *env);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e73ff53159c..68f5a620402 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -866,7 +866,7 @@ uint8_t riscv_cpu_default_priority(int irq)
 
 int riscv_cpu_pending_to_irq(CPURISCVState *env,
                              int extirq, unsigned int extirq_def_prio,
-                             uint64_t pending, uint8_t *iprio)
+                             uint64_t pending, const uint8_t *iprio)
 {
     int irq, best_irq = RISCV_EXCP_NONE;
     unsigned int prio, best_prio = UINT_MAX;
-- 
2.53.0

[PATCH 07/13] target/riscv: Constify CPURISCVState for various cpu_*() getters

[Philippe Mathieu-Daudé]

Add the const qualifier to CPURISCVState when the
argument is accessed without modification.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
 target/riscv/cpu.h | 17 +++++++++--------
 target/riscv/cpu.c |  2 +-
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bb4c8563554..2333dcecd8a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -636,7 +636,7 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
 uint8_t riscv_cpu_default_priority(int irq);
-uint64_t riscv_cpu_all_pending(CPURISCVState *env);
+uint64_t riscv_cpu_all_pending(const CPURISCVState *env);
 int riscv_cpu_mirq_pending(CPURISCVState *env);
 int riscv_cpu_sirq_pending(CPURISCVState *env);
 int riscv_cpu_vsirq_pending(CPURISCVState *env);
@@ -746,7 +746,7 @@ FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1)
 #ifdef TARGET_RISCV32
 #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
 #else
-static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
+static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env)
 {
     return env->misa_mxl;
 }
@@ -759,7 +759,7 @@ static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)
 }
 
 #if !defined(CONFIG_USER_ONLY)
-static inline privilege_mode_t cpu_address_mode(CPURISCVState *env)
+static inline privilege_mode_t cpu_address_mode(const CPURISCVState *env)
 {
     privilege_mode_t mode = env->priv;
 
@@ -769,7 +769,8 @@ static inline privilege_mode_t cpu_address_mode(CPURISCVState *env)
     return mode;
 }
 
-static inline RISCVMXL cpu_get_xl(CPURISCVState *env, privilege_mode_t mode)
+static inline RISCVMXL cpu_get_xl(const CPURISCVState *env,
+                                  privilege_mode_t mode)
 {
     RISCVMXL xl = env->misa_mxl;
     /*
@@ -797,7 +798,7 @@ static inline RISCVMXL cpu_get_xl(CPURISCVState *env, privilege_mode_t mode)
 #if defined(TARGET_RISCV32)
 #define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
 #else
-static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
+static inline RISCVMXL cpu_recompute_xl(const CPURISCVState *env)
 {
 #if !defined(CONFIG_USER_ONLY)
     return cpu_get_xl(env, env->priv);
@@ -810,7 +811,7 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env)
 #if defined(TARGET_RISCV32)
 #define cpu_address_xl(env)  ((void)(env), MXL_RV32)
 #else
-static inline RISCVMXL cpu_address_xl(CPURISCVState *env)
+static inline RISCVMXL cpu_address_xl(const CPURISCVState *env)
 {
 #ifdef CONFIG_USER_ONLY
     return env->xl;
@@ -822,7 +823,7 @@ static inline RISCVMXL cpu_address_xl(CPURISCVState *env)
 }
 #endif
 
-static inline uint16_t riscv_cpu_xlen(CPURISCVState *env)
+static inline uint16_t riscv_cpu_xlen(const CPURISCVState *env)
 {
     return 16 << env->xl;
 }
@@ -830,7 +831,7 @@ static inline uint16_t riscv_cpu_xlen(CPURISCVState *env)
 #ifdef TARGET_RISCV32
 #define riscv_cpu_sxl(env)  ((void)(env), MXL_RV32)
 #else
-static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
+static inline RISCVMXL riscv_cpu_sxl(const CPURISCVState *env)
 {
 #ifdef CONFIG_USER_ONLY
     return env->misa_mxl;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 68f5a620402..a344daf62f8 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -908,7 +908,7 @@ int riscv_cpu_pending_to_irq(CPURISCVState *env,
  * using hvip bits 13:63 from HS-mode. Those are returned in
  * riscv_cpu_sirq_pending() and riscv_cpu_vsirq_pending().
  */
-uint64_t riscv_cpu_all_pending(CPURISCVState *env)
+uint64_t riscv_cpu_all_pending(const CPURISCVState *env)
 {
     uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN);
     uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0;
-- 
2.53.0

[PATCH 08/13] target/sparc: Constify CPUSPARCState for various cpu_*() getters

[Philippe Mathieu-Daudé]

Add the const qualifier to CPUSPARCState when
the argument is accessed without modification.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
 target/sparc/cpu.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 5f583ed9de2..31a16c2af03 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -680,28 +680,28 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
 #endif
 
 #if defined (TARGET_SPARC64)
-static inline int cpu_has_hypervisor(CPUSPARCState *env1)
+static inline int cpu_has_hypervisor(const CPUSPARCState *env1)
 {
     return env1->def.features & CPU_FEATURE_HYPV;
 }
 
-static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
+static inline int cpu_hypervisor_mode(const CPUSPARCState *env1)
 {
     return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
 }
 
-static inline int cpu_supervisor_mode(CPUSPARCState *env1)
+static inline int cpu_supervisor_mode(const CPUSPARCState *env1)
 {
     return env1->pstate & PS_PRIV;
 }
 #else
-static inline int cpu_supervisor_mode(CPUSPARCState *env1)
+static inline int cpu_supervisor_mode(const CPUSPARCState *env1)
 {
     return env1->psrs;
 }
 #endif
 
-static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
+static inline int cpu_interrupts_enabled(const CPUSPARCState *env1)
 {
 #if !defined (TARGET_SPARC64)
     if (env1->psret != 0)
@@ -715,7 +715,7 @@ static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
     return 0;
 }
 
-static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
+static inline int cpu_pil_allowed(const CPUSPARCState *env1, int pil)
 {
 #if !defined(TARGET_SPARC64)
     /* level 15 is non-maskable on sparc v8 */
-- 
2.53.0

[RFC PATCH 09/13] cpus: Add const-qualified CPU environment accessors

[Philippe Mathieu-Daudé]

Introduce const-qualified variants of cpu_env() and
env_archcpu(), to safely access CPU architecture
state when it should not be modified.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
 include/exec/cpu-common.h | 11 +++++++++++
 include/hw/core/cpu.h     |  6 ++++++
 2 files changed, 17 insertions(+)

diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 6594f7fa1be..f3a3799f451 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -79,6 +79,17 @@ static inline bool cpu_loop_exit_requested(const CPUState *cpu)
 }
 #endif /* CONFIG_TCG */
 
+/**
+ * env_archcpu_const(env)
+ * @env: The architecture environment (const).
+ *
+ * Return the const ArchCPU associated with the environment.
+ */
+static inline const ArchCPU *env_archcpu_const(const CPUArchState *env)
+{
+    return (const void *)env - sizeof(CPUState);
+}
+
 /**
  * env_archcpu(env)
  * @env: The architecture environment
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 81af7b9ee1a..59f777f3f15 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -594,6 +594,12 @@ struct CPUState {
 QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) !=
                   sizeof(CPUState) - sizeof(CPUNegativeOffsetState));
 
+static inline const CPUArchState *cpu_env_const(const CPUState *cpu)
+{
+    /* We validate that CPUArchState follows CPUState in cpu-target.c */
+    return (const CPUArchState *)(cpu + 1);
+}
+
 static inline CPUArchState *cpu_env(CPUState *cpu)
 {
     /* We validate that CPUArchState follows CPUState in cpu-target.c */
-- 
2.53.0

[RFC PATCH 10/13] target/riscv: Constify CPURISCVState for various cpu_*() getters

[Philippe Mathieu-Daudé]

Add the const qualifier to CPURISCVState when the
argument is accessed without modification.

Note we have to use the recently introduced
env_archcpu_const() helper in riscv_cpu_cfg().

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
 target/riscv/cpu.h | 12 ++++++------
 target/riscv/cpu.c |  8 ++++----
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2333dcecd8a..9fd9ba54147 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -637,10 +637,10 @@ int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero);
 uint8_t riscv_cpu_default_priority(int irq);
 uint64_t riscv_cpu_all_pending(const CPURISCVState *env);
-int riscv_cpu_mirq_pending(CPURISCVState *env);
-int riscv_cpu_sirq_pending(CPURISCVState *env);
-int riscv_cpu_vsirq_pending(CPURISCVState *env);
-int riscv_cpu_pending_to_irq(CPURISCVState *env,
+int riscv_cpu_mirq_pending(const CPURISCVState *env);
+int riscv_cpu_sirq_pending(const CPURISCVState *env);
+int riscv_cpu_vsirq_pending(const CPURISCVState *env);
+int riscv_cpu_pending_to_irq(const CPURISCVState *env,
                              int extirq, unsigned int extirq_def_prio,
                              uint64_t pending, const uint8_t *iprio);
 
@@ -753,9 +753,9 @@ static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env)
 #endif
 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
 
-static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)
+static inline const RISCVCPUConfig *riscv_cpu_cfg(const CPURISCVState *env)
 {
-    return &env_archcpu(env)->cfg;
+    return &env_archcpu_const(env)->cfg;
 }
 
 #if !defined(CONFIG_USER_ONLY)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a344daf62f8..ab2868dc1e2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -864,7 +864,7 @@ uint8_t riscv_cpu_default_priority(int irq)
     return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO;
 };
 
-int riscv_cpu_pending_to_irq(CPURISCVState *env,
+int riscv_cpu_pending_to_irq(const CPURISCVState *env,
                              int extirq, unsigned int extirq_def_prio,
                              uint64_t pending, const uint8_t *iprio)
 {
@@ -917,7 +917,7 @@ uint64_t riscv_cpu_all_pending(const CPURISCVState *env)
     return (env->mip | vsgein | vstip) & env->mie;
 }
 
-int riscv_cpu_mirq_pending(CPURISCVState *env)
+int riscv_cpu_mirq_pending(const CPURISCVState *env)
 {
     uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg &
                     ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
@@ -926,7 +926,7 @@ int riscv_cpu_mirq_pending(CPURISCVState *env)
                                     irqs, env->miprio);
 }
 
-int riscv_cpu_sirq_pending(CPURISCVState *env)
+int riscv_cpu_sirq_pending(const CPURISCVState *env)
 {
     uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & ~env->hideleg;
     uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie;
@@ -935,7 +935,7 @@ int riscv_cpu_sirq_pending(CPURISCVState *env)
                                     irqs | irqs_f, env->siprio);
 }
 
-int riscv_cpu_vsirq_pending(CPURISCVState *env)
+int riscv_cpu_vsirq_pending(const CPURISCVState *env)
 {
     uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & env->hideleg;
     uint64_t irqs_f_vs = env->hvip & env->hvien & ~env->hideleg & env->vsie;
-- 
2.53.0

[RFC PATCH 11/13] target/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled()

[Philippe Mathieu-Daudé]

Use the recently introduced env_archcpu_const() helper and
qualify @env as being const in hexagon_thread_is_enabled().

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
 target/hexagon/cpu.h | 2 +-
 target/hexagon/cpu.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index c50fbb3f72a..e4f120eda17 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -216,7 +216,7 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
  * @return true if the @a thread_env hardware thread is
  * not stopped.
  */
-bool hexagon_thread_is_enabled(CPUHexagonState *thread_env);
+bool hexagon_thread_is_enabled(const CPUHexagonState *thread_env);
 uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg);
 void hexagon_cpu_soft_reset(CPUHexagonState *env);
 #endif
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 9765716b516..7ae5740899b 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -345,9 +345,9 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
 }
 
 #ifndef CONFIG_USER_ONLY
-bool hexagon_thread_is_enabled(CPUHexagonState *env)
+bool hexagon_thread_is_enabled(const CPUHexagonState *env)
 {
-    HexagonCPU *cpu = env_archcpu(env);
+    const HexagonCPU *cpu = env_archcpu_const(env);
     uint32_t modectl;
     uint32_t thread_enabled_mask;
     bool E_bit;
-- 
2.53.0

[RFC PATCH 12/13] target/mips: Constify CPUMIPSState in mips_vpe_active()

[Philippe Mathieu-Daudé]

Use the recently introduced env_archcpu_const() helper
and qualify @env as being const in mips_vpe_active().

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
 target/mips/internal.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 66e8c599b43..88459539866 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -247,9 +247,9 @@ static inline void restore_pamask(CPUMIPSState *env)
     }
 }
 
-static inline int mips_vpe_active(CPUMIPSState *env)
+static inline int mips_vpe_active(const CPUMIPSState *env)
 {
-    MIPSCPU *cpu = env_archcpu(env);
+    const MIPSCPU *cpu = env_archcpu_const(env);
     int active = 1;
 
     /* Check that the VPE is enabled.  */
-- 
2.53.0

[RFC PATCH 13/13] cpus: Constify @cpu in SysemuCPUOps::has_work() handler

[Philippe Mathieu-Daudé]

All functions called by target has_work() handler take a const @cpu
argument. We can now fulfill the comment added in commit c2804566f6
("target/arm: do not clear halting reason in has_work helper"),
qualifying the handler const to denote its idempotency.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
 include/hw/core/sysemu-cpu-ops.h | 4 ++--
 target/loongarch/internals.h     | 2 +-
 target/riscv/internals.h         | 2 +-
 target/s390x/s390x-internal.h    | 2 +-
 target/alpha/cpu.c               | 2 +-
 target/arm/cpu.c                 | 4 ++--
 target/avr/cpu.c                 | 5 +++--
 target/hexagon/cpu.c             | 4 ++--
 target/hppa/cpu.c                | 2 +-
 target/i386/cpu.c                | 2 +-
 target/loongarch/cpu.c           | 4 ++--
 target/m68k/cpu.c                | 2 +-
 target/microblaze/cpu.c          | 2 +-
 target/mips/cpu.c                | 4 ++--
 target/or1k/cpu.c                | 2 +-
 target/ppc/cpu_init.c            | 2 +-
 target/riscv/cpu.c               | 2 +-
 target/rx/cpu.c                  | 2 +-
 target/s390x/cpu-system.c        | 2 +-
 target/sh4/cpu.c                 | 2 +-
 target/sparc/cpu.c               | 4 ++--
 target/tricore/cpu.c             | 4 ++--
 target/xtensa/cpu.c              | 4 ++--
 23 files changed, 33 insertions(+), 32 deletions(-)

diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
index 9a45596169a..095bdcd997a 100644
--- a/include/hw/core/sysemu-cpu-ops.h
+++ b/include/hw/core/sysemu-cpu-ops.h
@@ -19,10 +19,10 @@ typedef struct SysemuCPUOps {
     /**
      * @has_work: Callback for checking if there is work to do.
      *
-     * This function should be idempotent (i.e. not change state) as
+     * This function is idempotent (i.e. not change state) as
      * it will likely be queried multiple times before a CPU resumes.
      */
-    bool (*has_work)(CPUState *cpu); /* MANDATORY NON-NULL */
+    bool (*has_work)(const CPUState *cpu); /* MANDATORY NON-NULL */
     /**
      * @get_memory_mapping: Callback for obtaining the memory mappings.
      */
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index 6a733e6c3a5..d86029bcb31 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -38,7 +38,7 @@ uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu);
 uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu);
 void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
                                                uint64_t value);
-bool loongarch_cpu_has_work(CPUState *cs);
+bool loongarch_cpu_has_work(const CPUState *cs);
 bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env);
 #endif /* !CONFIG_USER_ONLY */
 
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 5d84e4de960..782f12abfaf 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -203,7 +203,7 @@ static inline target_ulong get_xepc_mask(CPURISCVState *env)
 
 #ifndef CONFIG_USER_ONLY
 /* Our implementation of SysemuCPUOps::has_work */
-bool riscv_cpu_has_work(CPUState *cs);
+bool riscv_cpu_has_work(const CPUState *cs);
 #endif
 
 /* Zjpm addr masking routine */
diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h
index 54b62808d83..00917473a54 100644
--- a/target/s390x/s390x-internal.h
+++ b/target/s390x/s390x-internal.h
@@ -248,7 +248,7 @@ bool s390_cpu_system_realize(DeviceState *dev, Error **errp);
 void s390_cpu_finalize(Object *obj);
 void s390_cpu_system_class_init(CPUClass *cc);
 void s390_cpu_machine_reset_cb(void *opaque);
-bool s390_cpu_has_work(CPUState *cs);
+bool s390_cpu_has_work(const CPUState *cs);
 #endif /* CONFIG_USER_ONLY */
 
 
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 7d1d036e1d3..21d4f8ac23b 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -77,7 +77,7 @@ static void alpha_restore_state_to_opc(CPUState *cs,
 }
 
 #ifndef CONFIG_USER_ONLY
-static bool alpha_cpu_has_work(CPUState *cs)
+static bool alpha_cpu_has_work(const CPUState *cs)
 {
     /* Here we are checking to see if the CPU should wake up from HALT.
        We will have gotten into this state only for WTINT from PALmode.  */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 9761bb173c1..ba66359d410 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -141,9 +141,9 @@ int arm_cpu_mmu_index(CPUState *cs, bool ifetch)
  * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here
  * unconditionally.
  */
-static bool arm_cpu_has_work(CPUState *cs)
+static bool arm_cpu_has_work(const CPUState *cs)
 {
-    ARMCPU *cpu = ARM_CPU(cs);
+    const ARMCPU *cpu = ARM_CPU(cs);
 
     /*
      * Only another PSCI call can wake the CPU up in which case the
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index a01e6fa4751..1024c0ae9a2 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -23,6 +23,7 @@
 #include "qemu/qemu-print.h"
 #include "exec/translation-block.h"
 #include "system/address-spaces.h"
+#include "hw/core/cpu.h"
 #include "cpu.h"
 #include "disas/dis-asm.h"
 #include "tcg/debug-assert.h"
@@ -43,10 +44,10 @@ static vaddr avr_cpu_get_pc(CPUState *cs)
     return cpu->env.pc_w * 2;
 }
 
-static bool avr_cpu_has_work(CPUState *cs)
+static bool avr_cpu_has_work(const CPUState *cs)
 {
     return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET)
-            && cpu_interrupts_enabled(cpu_env(cs));
+            && cpu_interrupts_enabled(cpu_env_const(cs));
 }
 
 static int avr_cpu_mmu_index(CPUState *cs, bool ifetch)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 7ae5740899b..4ad1cae354a 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -364,9 +364,9 @@ bool hexagon_thread_is_enabled(const CPUHexagonState *env)
     return E_bit;
 }
 
-static bool hexagon_cpu_has_work(CPUState *cs)
+static bool hexagon_cpu_has_work(const CPUState *cs)
 {
-    CPUHexagonState *env = cpu_env(cs);
+    const CPUHexagonState *env = cpu_env_const(cs);
 
     return hexagon_thread_is_enabled(env) &&
         (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 7b1309a7c38..dbf58466c24 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -134,7 +134,7 @@ static void hppa_restore_state_to_opc(CPUState *cs,
 }
 
 #ifndef CONFIG_USER_ONLY
-static bool hppa_cpu_has_work(CPUState *cs)
+static bool hppa_cpu_has_work(const CPUState *cs)
 {
     return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
 }
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8777bcbae85..93b617f94dc 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -10639,7 +10639,7 @@ int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request)
     return 0;
 }
 
-static bool x86_cpu_has_work(CPUState *cs)
+static bool x86_cpu_has_work(const CPUState *cs)
 {
     return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
 }
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 82ec35e081f..4c1aae4fb01 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -96,12 +96,12 @@ bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env)
 #endif
 
 #ifndef CONFIG_USER_ONLY
-bool loongarch_cpu_has_work(CPUState *cs)
+bool loongarch_cpu_has_work(const CPUState *cs)
 {
     bool has_work = false;
 
     if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) &&
-        cpu_loongarch_hw_interrupts_pending(cpu_env(cs))) {
+        cpu_loongarch_hw_interrupts_pending(cpu_env_const(cs))) {
         has_work = true;
     }
 
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 523694d8fbf..da3681fab1f 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -76,7 +76,7 @@ static void m68k_restore_state_to_opc(CPUState *cs,
 }
 
 #ifndef CONFIG_USER_ONLY
-static bool m68k_cpu_has_work(CPUState *cs)
+static bool m68k_cpu_has_work(const CPUState *cs)
 {
     return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD);
 }
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 6013a8def8e..d1d2f0ec7e3 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -127,7 +127,7 @@ static void mb_restore_state_to_opc(CPUState *cs,
 }
 
 #ifndef CONFIG_USER_ONLY
-static bool mb_cpu_has_work(CPUState *cs)
+static bool mb_cpu_has_work(const CPUState *cs)
 {
     return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
 }
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index c069aa1c0b7..0f9374d98a9 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -134,9 +134,9 @@ static vaddr mips_cpu_get_pc(CPUState *cs)
 }
 
 #if !defined(CONFIG_USER_ONLY)
-static bool mips_cpu_has_work(CPUState *cs)
+static bool mips_cpu_has_work(const CPUState *cs)
 {
-    CPUMIPSState *env = cpu_env(cs);
+    const CPUMIPSState *env = cpu_env_const(cs);
     bool has_work = false;
 
     /*
diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c
index 42d9351b6d7..10b13ae69cd 100644
--- a/target/or1k/cpu.c
+++ b/target/or1k/cpu.c
@@ -76,7 +76,7 @@ static void openrisc_restore_state_to_opc(CPUState *cs,
 }
 
 #ifndef CONFIG_USER_ONLY
-static bool openrisc_cpu_has_work(CPUState *cs)
+static bool openrisc_cpu_has_work(const CPUState *cs)
 {
     return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER);
 }
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 85a91ff4bb6..fd63cd6ab09 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7224,7 +7224,7 @@ static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch)
 #endif /* CONFIG_TCG */
 
 #ifndef CONFIG_USER_ONLY
-static bool ppc_cpu_has_work(CPUState *cs)
+static bool ppc_cpu_has_work(const CPUState *cs)
 {
     return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD);
 }
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ab2868dc1e2..b455b997561 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -950,7 +950,7 @@ int riscv_cpu_vsirq_pending(const CPURISCVState *env)
                                     (irqs | irqs_f_vs), env->hviprio);
 }
 
-bool riscv_cpu_has_work(CPUState *cs)
+bool riscv_cpu_has_work(const CPUState *cs)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 69946928995..dfa09a85bce 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -73,7 +73,7 @@ static void rx_restore_state_to_opc(CPUState *cs,
     cpu->env.pc = data[0];
 }
 
-static bool rx_cpu_has_work(CPUState *cs)
+static bool rx_cpu_has_work(const CPUState *cs)
 {
     return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
 }
diff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c
index cc9685221ae..22ed2b097bb 100644
--- a/target/s390x/cpu-system.c
+++ b/target/s390x/cpu-system.c
@@ -39,7 +39,7 @@
 #include "system/tcg.h"
 #include "hw/core/sysemu-cpu-ops.h"
 
-bool s390_cpu_has_work(CPUState *cs)
+bool s390_cpu_has_work(const CPUState *cs)
 {
     S390CPU *cpu = S390_CPU(cs);
 
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 55c73a1da35..b0ed356d0f7 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -107,7 +107,7 @@ static bool superh_io_recompile_replay_branch(CPUState *cs,
     return false;
 }
 
-static bool superh_cpu_has_work(CPUState *cs)
+static bool superh_cpu_has_work(const CPUState *cs)
 {
     return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD);
 }
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 2baa5036871..f7c04daf0c9 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -783,10 +783,10 @@ static void sparc_restore_state_to_opc(CPUState *cs,
 }
 
 #ifndef CONFIG_USER_ONLY
-static bool sparc_cpu_has_work(CPUState *cs)
+static bool sparc_cpu_has_work(const CPUState *cs)
 {
     return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) &&
-           cpu_interrupts_enabled(cpu_env(cs));
+           cpu_interrupts_enabled(cpu_env_const(cs));
 }
 #endif /* !CONFIG_USER_ONLY */
 
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 6d448727005..33a5875ef24 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -111,9 +111,9 @@ static void tricore_cpu_reset_hold(Object *obj, ResetType type)
     cpu_state_reset(cpu_env(cs));
 }
 
-static bool tricore_cpu_has_work(CPUState *cs)
+static bool tricore_cpu_has_work(const CPUState *cs)
 {
-    return true;
+    return true; /* XXX */
 }
 
 static int tricore_cpu_mmu_index(CPUState *cs, bool ifetch)
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 99c8bd4b5fb..fe7965651f4 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -140,9 +140,9 @@ static void xtensa_restore_state_to_opc(CPUState *cs,
 }
 
 #ifndef CONFIG_USER_ONLY
-static bool xtensa_cpu_has_work(CPUState *cs)
+static bool xtensa_cpu_has_work(const CPUState *cs)
 {
-    CPUXtensaState *env = cpu_env(cs);
+    const CPUXtensaState *env = cpu_env_const(cs);
 
     return !env->runstall && env->pending_irq_level;
 }
-- 
2.53.0

Re: [RFC PATCH 13/13] cpus: Constify @cpu in SysemuCPUOps::has_work() handler

[Philippe Mathieu-Daudé]

On 20/8/26 12:47, Philippe Mathieu-Daudé wrote:
> All functions called by target has_work() handler take a const @cpu
> argument. We can now fulfill the comment added in commit c2804566f6
> ("target/arm: do not clear halting reason in has_work helper"),
> qualifying the handler const to denote its idempotency.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
> ---
>   include/hw/core/sysemu-cpu-ops.h | 4 ++--
>   target/loongarch/internals.h     | 2 +-
>   target/riscv/internals.h         | 2 +-
>   target/s390x/s390x-internal.h    | 2 +-
>   target/alpha/cpu.c               | 2 +-
>   target/arm/cpu.c                 | 4 ++--
>   target/avr/cpu.c                 | 5 +++--
>   target/hexagon/cpu.c             | 4 ++--
>   target/hppa/cpu.c                | 2 +-
>   target/i386/cpu.c                | 2 +-
>   target/loongarch/cpu.c           | 4 ++--
>   target/m68k/cpu.c                | 2 +-
>   target/microblaze/cpu.c          | 2 +-
>   target/mips/cpu.c                | 4 ++--
>   target/or1k/cpu.c                | 2 +-
>   target/ppc/cpu_init.c            | 2 +-
>   target/riscv/cpu.c               | 2 +-
>   target/rx/cpu.c                  | 2 +-
>   target/s390x/cpu-system.c        | 2 +-
>   target/sh4/cpu.c                 | 2 +-
>   target/sparc/cpu.c               | 4 ++--
>   target/tricore/cpu.c             | 4 ++--
>   target/xtensa/cpu.c              | 4 ++--
>   23 files changed, 33 insertions(+), 32 deletions(-)


> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 9761bb173c1..ba66359d410 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -141,9 +141,9 @@ int arm_cpu_mmu_index(CPUState *cs, bool ifetch)
>    * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here
>    * unconditionally.
>    */
> -static bool arm_cpu_has_work(CPUState *cs)
> +static bool arm_cpu_has_work(const CPUState *cs)
>   {
> -    ARMCPU *cpu = ARM_CPU(cs);
> +    const ARMCPU *cpu = ARM_CPU(cs);
BTW this is why I said "Not sure if this is a good idea so marked as
RFC" in the cover letter. While the left assignment is correct, the
right QOM-generated macros happily cast without checking const-ness.
We can see that as a pre-existing risk.

Still overall enforcing const-ness on has_work() is a long-term win.
Maybe a simple comment here is sufficient to warn.

Re: [PATCH 05/13] target/s390x: Constify S390CPU for cpu_has_*() getters

[Ilya Leoshkevich]

On 8/20/26 12:47, Philippe Mathieu-Daudé wrote:
> Add the const qualifier to S390CPU when the argument
> is accessed without modification.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
> ---
>   target/s390x/cpu.h            |  2 +-
>   target/s390x/s390x-internal.h | 12 ++++++------
>   target/s390x/interrupt.c      | 22 +++++++++++-----------
>   3 files changed, 18 insertions(+), 18 deletions(-)

Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>

Re: [PATCH 01/13] target/avr: Constify CPUAVRState for some cpu_*() getters

[marcandre.lureau]

On Thu, 20 Aug 2026 12:47:17 +0200, Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> wrote:
> Add the const qualifier to CPUAVRState when the
> argument is accessed without modification.

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>

-- 
Marc-André Lureau <marcandre.lureau@redhat.com>

Re: [PATCH 03/13] target/loongarch: Constify CPULoongArchState for various cpu_*() getters

[marcandre.lureau]

On Thu, 20 Aug 2026 12:47:19 +0200, Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> wrote:
> Add the const qualifier to CPULoongArchStatCPUMIPSStatee when
> the argument is accessed without modification.

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>

-- 
Marc-André Lureau <marcandre.lureau@redhat.com>

Re: [PATCH 02/13] target/i386: Constify CPU*State for cpu_*_interrupt() getters

[marcandre.lureau]

On Thu, 20 Aug 2026 12:47:18 +0200, Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> wrote:
> x86_cpu_pending_interrupt() and x86_cpu_interrupts_enabled()
> only read CPU state without modification, add the const
> qualifiers to CPUState and CPUX86State parameters.

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>

-- 
Marc-André Lureau <marcandre.lureau@redhat.com>

Re: [PATCH 05/13] target/s390x: Constify S390CPU for cpu_has_*() getters

[marcandre.lureau]

On Thu, 20 Aug 2026 12:47:21 +0200, Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> wrote:
> Add the const qualifier to S390CPU when the argument
> is accessed without modification.

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>

-- 
Marc-André Lureau <marcandre.lureau@redhat.com>

Re: [PATCH 04/13] target/mips: Constify CPUMIPSState for various cpu_*() getters

[marcandre.lureau]

On Thu, 20 Aug 2026 12:47:20 +0200, Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> wrote:
> Add the const qualifier to CPUMIPSState when
> the argument is accessed without modification.

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>

-- 
Marc-André Lureau <marcandre.lureau@redhat.com>

Re: [PATCH 06/13] target/riscv: Constify @iprio argument in riscv_cpu_pending_to_irq()

[marcandre.lureau]

On Thu, 20 Aug 2026 12:47:22 +0200, Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> wrote:
> @iprio[] is an array only accessed read-only.

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>

-- 
Marc-André Lureau <marcandre.lureau@redhat.com>

Re: [PATCH 07/13] target/riscv: Constify CPURISCVState for various cpu_*() getters

[marcandre.lureau]

On Thu, 20 Aug 2026 12:47:23 +0200, Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> wrote:
> Add the const qualifier to CPURISCVState when the
> argument is accessed without modification.

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>

-- 
Marc-André Lureau <marcandre.lureau@redhat.com>

Re: [PATCH 08/13] target/sparc: Constify CPUSPARCState for various cpu_*() getters

[marcandre.lureau]

On Thu, 20 Aug 2026 12:47:24 +0200, Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> wrote:
> Add the const qualifier to CPUSPARCState when
> the argument is accessed without modification.

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>

-- 
Marc-André Lureau <marcandre.lureau@redhat.com>

Re: [RFC PATCH 11/13] target/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled()

[marcandre.lureau]

On Thu, 20 Aug 2026 12:47:27 +0200, Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> wrote:
> Use the recently introduced env_archcpu_const() helper and
> qualify @env as being const in hexagon_thread_is_enabled().

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>

-- 
Marc-André Lureau <marcandre.lureau@redhat.com>

Re: [RFC PATCH 09/13] cpus: Add const-qualified CPU environment accessors

[marcandre.lureau]

On Thu, 20 Aug 2026 12:47:25 +0200, Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> wrote:
> Introduce const-qualified variants of cpu_env() and
> env_archcpu(), to safely access CPU architecture
> state when it should not be modified.

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>

-- 
Marc-André Lureau <marcandre.lureau@redhat.com>

Re: [RFC PATCH 13/13] cpus: Constify @cpu in SysemuCPUOps::has_work() handler

[marcandre.lureau]

> All functions called by target has_work() handler take a const @cpu
> argument. We can now fulfill the comment added in commit c2804566f6
> ("target/arm: do not clear halting reason in has_work helper"),
> qualifying the handler const to denote its idempotency.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
> Message-ID: <20260820104730.25462-14-philmd@oss.qualcomm.com>
>
> diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h
> index 9a45596169a3..095bdcd997aa 100644
> --- a/include/hw/core/sysemu-cpu-ops.h
> +++ b/include/hw/core/sysemu-cpu-ops.h
> @@ -19,10 +19,10 @@ typedef struct SysemuCPUOps {
>      /**
>       * @has_work: Callback for checking if there is work to do.
>       *
> -     * This function should be idempotent (i.e. not change state) as
> +     * This function is idempotent (i.e. not change state) as
>       * it will likely be queried multiple times before a CPU resumes.
>       */
> -    bool (*has_work)(CPUState *cpu); /* MANDATORY NON-NULL */
> +    bool (*has_work)(const CPUState *cpu); /* MANDATORY NON-NULL */
>      /**
>       * @get_memory_mapping: Callback for obtaining the memory mappings.
>       */
> diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
> index 12e860216634..991dfd8c38a9 100644
> --- a/target/alpha/cpu.c
> +++ b/target/alpha/cpu.c
> @@ -77,7 +77,7 @@ static void alpha_restore_state_to_opc(CPUState *cs,
>  }
>  
>  #ifndef CONFIG_USER_ONLY
> -static bool alpha_cpu_has_work(CPUState *cs)
> +static bool alpha_cpu_has_work(const CPUState *cs)
>  {
>      /* Here we are checking to see if the CPU should wake up from HALT.
>         We will have gotten into this state only for WTINT from PALmode.  */
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 77aa78f00e2f..7ee701d5d138 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -141,9 +141,9 @@ int arm_cpu_mmu_index(CPUState *cs, bool ifetch)
>   * CPU_INTERRUPT_*NMI anyway. So we might as well accept NMI here
>   * unconditionally.
>   */
> -static bool arm_cpu_has_work(CPUState *cs)
> +static bool arm_cpu_has_work(const CPUState *cs)
>  {
> -    ARMCPU *cpu = ARM_CPU(cs);
> +    const ARMCPU *cpu = ARM_CPU(cs);
>  
>      /*
>       * Only another PSCI call can wake the CPU up in which case the
> diff --git a/target/avr/cpu.c b/target/avr/cpu.c
> index f8409f32ab98..00f06d71eaae 100644
> --- a/target/avr/cpu.c
> +++ b/target/avr/cpu.c
> @@ -23,6 +23,7 @@
>  #include "qemu/qemu-print.h"
>  #include "exec/translation-block.h"
>  #include "system/address-spaces.h"
> +#include "hw/core/cpu.h"
>  #include "cpu.h"
>  #include "disas/dis-asm.h"
>  #include "tcg/debug-assert.h"
> @@ -43,10 +44,10 @@ static vaddr avr_cpu_get_pc(CPUState *cs)
>      return cpu->env.pc_w * 2;
>  }
>  
> -static bool avr_cpu_has_work(CPUState *cs)
> +static bool avr_cpu_has_work(const CPUState *cs)
>  {
>      return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET)
> -            && cpu_interrupts_enabled(cpu_env(cs));
> +            && cpu_interrupts_enabled(cpu_env_const(cs));
>  }
>  
>  static int avr_cpu_mmu_index(CPUState *cs, bool ifetch)
> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
> index da11d266c351..3139fcb695de 100644
> --- a/target/hexagon/cpu.c
> +++ b/target/hexagon/cpu.c
> @@ -364,9 +364,9 @@ bool hexagon_thread_is_enabled(const CPUHexagonState *env)
>      return E_bit;
>  }
>  
> -static bool hexagon_cpu_has_work(CPUState *cs)
> +static bool hexagon_cpu_has_work(const CPUState *cs)
>  {
> -    CPUHexagonState *env = cpu_env(cs);
> +    const CPUHexagonState *env = cpu_env_const(cs);
>  
>      return hexagon_thread_is_enabled(env) &&
>          (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI
> diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
> index 07b49e513263..28a1f1143166 100644
> --- a/target/hppa/cpu.c
> +++ b/target/hppa/cpu.c
> @@ -134,7 +134,7 @@ static void hppa_restore_state_to_opc(CPUState *cs,
>  }
>  
>  #ifndef CONFIG_USER_ONLY
> -static bool hppa_cpu_has_work(CPUState *cs)
> +static bool hppa_cpu_has_work(const CPUState *cs)
>  {
>      return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
>  }
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 8777bcbae858..93b617f94dce 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -10639,7 +10639,7 @@ int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request)
>      return 0;
>  }
>  
> -static bool x86_cpu_has_work(CPUState *cs)
> +static bool x86_cpu_has_work(const CPUState *cs)
>  {
>      return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
>  }
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 82ec35e081fd..4c1aae4fb013 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -96,12 +96,12 @@ bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env)
>  #endif
>  
>  #ifndef CONFIG_USER_ONLY
> -bool loongarch_cpu_has_work(CPUState *cs)
> +bool loongarch_cpu_has_work(const CPUState *cs)
>  {
>      bool has_work = false;
>  
>      if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) &&
> -        cpu_loongarch_hw_interrupts_pending(cpu_env(cs))) {
> +        cpu_loongarch_hw_interrupts_pending(cpu_env_const(cs))) {
>          has_work = true;
>      }
>  
> diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
> index 6a733e6c3a58..d86029bcb31d 100644
> --- a/target/loongarch/internals.h
> +++ b/target/loongarch/internals.h
> @@ -38,7 +38,7 @@ uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu);
>  uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu);
>  void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
>                                                 uint64_t value);
> -bool loongarch_cpu_has_work(CPUState *cs);
> +bool loongarch_cpu_has_work(const CPUState *cs);
>  bool cpu_loongarch_hw_interrupts_pending(const CPULoongArchState *env);
>  #endif /* !CONFIG_USER_ONLY */
>  
> diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
> index 6012dc3186c7..49ef822cbd9a 100644
> --- a/target/m68k/cpu.c
> +++ b/target/m68k/cpu.c
> @@ -76,7 +76,7 @@ static void m68k_restore_state_to_opc(CPUState *cs,
>  }
>  
>  #ifndef CONFIG_USER_ONLY
> -static bool m68k_cpu_has_work(CPUState *cs)
> +static bool m68k_cpu_has_work(const CPUState *cs)
>  {
>      return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD);
>  }
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 389a5124b124..86692239a1e8 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -127,7 +127,7 @@ static void mb_restore_state_to_opc(CPUState *cs,
>  }
>  
>  #ifndef CONFIG_USER_ONLY
> -static bool mb_cpu_has_work(CPUState *cs)
> +static bool mb_cpu_has_work(const CPUState *cs)
>  {
>      return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
>  }
> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
> index 0fead20d6515..07129731e75c 100644
> --- a/target/mips/cpu.c
> +++ b/target/mips/cpu.c
> @@ -134,9 +134,9 @@ static vaddr mips_cpu_get_pc(CPUState *cs)
>  }
>  
>  #if !defined(CONFIG_USER_ONLY)
> -static bool mips_cpu_has_work(CPUState *cs)
> +static bool mips_cpu_has_work(const CPUState *cs)
>  {
> -    CPUMIPSState *env = cpu_env(cs);
> +    const CPUMIPSState *env = cpu_env_const(cs);
>      bool has_work = false;
>  
>      /*
> diff --git a/target/or1k/cpu.c b/target/or1k/cpu.c
> index 66c00c0930cd..d4d81d0c3512 100644
> --- a/target/or1k/cpu.c
> +++ b/target/or1k/cpu.c
> @@ -76,7 +76,7 @@ static void openrisc_restore_state_to_opc(CPUState *cs,
>  }
>  
>  #ifndef CONFIG_USER_ONLY
> -static bool openrisc_cpu_has_work(CPUState *cs)
> +static bool openrisc_cpu_has_work(const CPUState *cs)
>  {
>      return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER);
>  }
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index e3a1075aad3f..c5a29cfee856 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -7224,7 +7224,7 @@ static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch)
>  #endif /* CONFIG_TCG */
>  
>  #ifndef CONFIG_USER_ONLY
> -static bool ppc_cpu_has_work(CPUState *cs)
> +static bool ppc_cpu_has_work(const CPUState *cs)
>  {
>      return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD);
>  }
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index ab2868dc1e2f..b455b997561d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -950,7 +950,7 @@ int riscv_cpu_vsirq_pending(const CPURISCVState *env)
>                                      (irqs | irqs_f_vs), env->hviprio);
>  }
>  
> -bool riscv_cpu_has_work(CPUState *cs)
> +bool riscv_cpu_has_work(const CPUState *cs)
>  {
>      RISCVCPU *cpu = RISCV_CPU(cs);
>      CPURISCVState *env = &cpu->env;

I guess you should make them const

> diff --git a/target/riscv/internals.h b/target/riscv/internals.h
> index 5d84e4de960a..782f12abfaf0 100644
> --- a/target/riscv/internals.h
> +++ b/target/riscv/internals.h
> @@ -203,7 +203,7 @@ static inline target_ulong get_xepc_mask(CPURISCVState *env)
>  
>  #ifndef CONFIG_USER_ONLY
>  /* Our implementation of SysemuCPUOps::has_work */
> -bool riscv_cpu_has_work(CPUState *cs);
> +bool riscv_cpu_has_work(const CPUState *cs);
>  #endif
>  
>  /* Zjpm addr masking routine */
> diff --git a/target/rx/cpu.c b/target/rx/cpu.c
> index 9b8473d71cf6..bc18dd250cf3 100644
> --- a/target/rx/cpu.c
> +++ b/target/rx/cpu.c
> @@ -73,7 +73,7 @@ static void rx_restore_state_to_opc(CPUState *cs,
>      cpu->env.pc = data[0];
>  }
>  
> -static bool rx_cpu_has_work(CPUState *cs)
> +static bool rx_cpu_has_work(const CPUState *cs)
>  {
>      return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
>  }
> diff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c
> index cc9685221ae8..22ed2b097bbd 100644
> --- a/target/s390x/cpu-system.c
> +++ b/target/s390x/cpu-system.c
> @@ -39,7 +39,7 @@
>  #include "system/tcg.h"
>  #include "hw/core/sysemu-cpu-ops.h"
>  
> -bool s390_cpu_has_work(CPUState *cs)
> +bool s390_cpu_has_work(const CPUState *cs)
>  {
>      S390CPU *cpu = S390_CPU(cs);

same

>  
> diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h
> index 54b62808d834..00917473a544 100644
> --- a/target/s390x/s390x-internal.h
> +++ b/target/s390x/s390x-internal.h
> @@ -248,7 +248,7 @@ bool s390_cpu_system_realize(DeviceState *dev, Error **errp);
>  void s390_cpu_finalize(Object *obj);
>  void s390_cpu_system_class_init(CPUClass *cc);
>  void s390_cpu_machine_reset_cb(void *opaque);
> -bool s390_cpu_has_work(CPUState *cs);
> +bool s390_cpu_has_work(const CPUState *cs);
>  #endif /* CONFIG_USER_ONLY */
>  
>  
> diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
> index 3bbdee301d5d..36e8b4725aae 100644
> --- a/target/sh4/cpu.c
> +++ b/target/sh4/cpu.c
> @@ -107,7 +107,7 @@ static bool superh_io_recompile_replay_branch(CPUState *cs,
>      return false;
>  }
>  
> -static bool superh_cpu_has_work(CPUState *cs)
> +static bool superh_cpu_has_work(const CPUState *cs)
>  {
>      return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD);
>  }
> diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
> index 1bc14b586bb9..0ecb573129b1 100644
> --- a/target/sparc/cpu.c
> +++ b/target/sparc/cpu.c
> @@ -783,10 +783,10 @@ static void sparc_restore_state_to_opc(CPUState *cs,
>  }
>  
>  #ifndef CONFIG_USER_ONLY
> -static bool sparc_cpu_has_work(CPUState *cs)
> +static bool sparc_cpu_has_work(const CPUState *cs)
>  {
>      return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) &&
> -           cpu_interrupts_enabled(cpu_env(cs));
> +           cpu_interrupts_enabled(cpu_env_const(cs));
>  }
>  #endif /* !CONFIG_USER_ONLY */
>  
> diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
> index dcd5c5065bcd..837ecb9b343f 100644
> --- a/target/tricore/cpu.c
> +++ b/target/tricore/cpu.c
> @@ -111,9 +111,9 @@ static void tricore_cpu_reset_hold(Object *obj, ResetType type)
>      cpu_state_reset(cpu_env(cs));
>  }
>  
> -static bool tricore_cpu_has_work(CPUState *cs)
> +static bool tricore_cpu_has_work(const CPUState *cs)
>  {
> -    return true;
> +    return true; /* XXX */
>  }

Add more explicit FIXME?

-- 
Marc-André Lureau <marcandre.lureau@redhat.com>

Re: [RFC PATCH 10/13] target/riscv: Constify CPURISCVState for various cpu_*() getters

[marcandre.lureau]

On Thu, 20 Aug 2026 12:47:26 +0200, Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> wrote:
> Add the const qualifier to CPURISCVState when the
> argument is accessed without modification.
> 
> Note we have to use the recently introduced
> env_archcpu_const() helper in riscv_cpu_cfg().
> 
> 
> [...]

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>

-- 
Marc-André Lureau <marcandre.lureau@redhat.com>

Re: [RFC PATCH 12/13] target/mips: Constify CPUMIPSState in mips_vpe_active()

[marcandre.lureau]

On Thu, 20 Aug 2026 12:47:28 +0200, Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> wrote:
> Use the recently introduced env_archcpu_const() helper
> and qualify @env as being const in mips_vpe_active().

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>

-- 
Marc-André Lureau <marcandre.lureau@redhat.com>

Re: [RFC PATCH 13/13] cpus: Constify @cpu in SysemuCPUOps::has_work() handler

[Philippe Mathieu-Daudé]

On 20/8/26 15:22, marcandre.lureau@redhat.com wrote:
>> All functions called by target has_work() handler take a const @cpu
>> argument. We can now fulfill the comment added in commit c2804566f6
>> ("target/arm: do not clear halting reason in has_work helper"),
>> qualifying the handler const to denote its idempotency.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
>> Message-ID: <20260820104730.25462-14-philmd@oss.qualcomm.com>


>> diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
>> index dcd5c5065bcd..837ecb9b343f 100644
>> --- a/target/tricore/cpu.c
>> +++ b/target/tricore/cpu.c
>> @@ -111,9 +111,9 @@ static void tricore_cpu_reset_hold(Object *obj, ResetType type)
>>       cpu_state_reset(cpu_env(cs));
>>   }
>>   
>> -static bool tricore_cpu_has_work(CPUState *cs)
>> +static bool tricore_cpu_has_work(const CPUState *cs)
>>   {
>> -    return true;
>> +    return true; /* XXX */
>>   }
> 
> Add more explicit FIXME?

Oops this was a dev comment for myself ("this is dubious, better
review"), I forgot about it :/ As mentioned Peter in commit
de680286b52 ("accel/tcg: Make cpu_exec_interrupt hook mandatory")
"Tricore doesn't currently implement the architectural interrupt
handling" so here I'll simply add:

   /* Interrupts are not implemented */

Thanks for the reviews!

Re: [RFC PATCH 09/13] cpus: Add const-qualified CPU environment accessors

[Richard Henderson]

On 8/20/26 03:47, Philippe Mathieu-Daudé wrote:
> Introduce const-qualified variants of cpu_env() and
> env_archcpu(), to safely access CPU architecture
> state when it should not be modified.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
> ---
>   include/exec/cpu-common.h | 11 +++++++++++
>   include/hw/core/cpu.h     |  6 ++++++
>   2 files changed, 17 insertions(+)
> 
> diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
> index 6594f7fa1be..f3a3799f451 100644
> --- a/include/exec/cpu-common.h
> +++ b/include/exec/cpu-common.h
> @@ -79,6 +79,17 @@ static inline bool cpu_loop_exit_requested(const CPUState *cpu)
>   }
>   #endif /* CONFIG_TCG */
>   
> +/**
> + * env_archcpu_const(env)
> + * @env: The architecture environment (const).
> + *
> + * Return the const ArchCPU associated with the environment.
> + */
> +static inline const ArchCPU *env_archcpu_const(const CPUArchState *env)
> +{
> +    return (const void *)env - sizeof(CPUState);
> +}
> +
>   /**
>    * env_archcpu(env)
>    * @env: The architecture environment
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 81af7b9ee1a..59f777f3f15 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -594,6 +594,12 @@ struct CPUState {
>   QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) !=
>                     sizeof(CPUState) - sizeof(CPUNegativeOffsetState));
>   
> +static inline const CPUArchState *cpu_env_const(const CPUState *cpu)
> +{
> +    /* We validate that CPUArchState follows CPUState in cpu-target.c */
> +    return (const CPUArchState *)(cpu + 1);
> +}
> +
>   static inline CPUArchState *cpu_env(CPUState *cpu)
>   {
>       /* We validate that CPUArchState follows CPUState in cpu-target.c */

I wonder if we can use _Generic to make this automatic, rather than have to choose between 
two different function names.


r~

Re: [RFC PATCH 11/13] target/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled()

[Brian Cain]

On 8/20/2026 5:47 AM, Philippe Mathieu-Daudé wrote:
> Use the recently introduced env_archcpu_const() helper and
> qualify @env as being const in hexagon_thread_is_enabled().
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
> ---


Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>


>   target/hexagon/cpu.h | 2 +-
>   target/hexagon/cpu.c | 4 ++--
>   2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
> index c50fbb3f72a..e4f120eda17 100644
> --- a/target/hexagon/cpu.h
> +++ b/target/hexagon/cpu.h
> @@ -216,7 +216,7 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
>    * @return true if the @a thread_env hardware thread is
>    * not stopped.
>    */
> -bool hexagon_thread_is_enabled(CPUHexagonState *thread_env);
> +bool hexagon_thread_is_enabled(const CPUHexagonState *thread_env);
>   uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg);
>   void hexagon_cpu_soft_reset(CPUHexagonState *env);
>   #endif
> diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
> index 9765716b516..7ae5740899b 100644
> --- a/target/hexagon/cpu.c
> +++ b/target/hexagon/cpu.c
> @@ -345,9 +345,9 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
>   }
>   
>   #ifndef CONFIG_USER_ONLY
> -bool hexagon_thread_is_enabled(CPUHexagonState *env)
> +bool hexagon_thread_is_enabled(const CPUHexagonState *env)
>   {
> -    HexagonCPU *cpu = env_archcpu(env);
> +    const HexagonCPU *cpu = env_archcpu_const(env);
>       uint32_t modectl;
>       uint32_t thread_enabled_mask;
>       bool E_bit;

Re: [RFC PATCH 09/13] cpus: Add const-qualified CPU environment accessors

[Philippe Mathieu-Daudé]

On 2026-08-20 17:21, Richard Henderson wrote:
> On 8/20/26 03:47, Philippe Mathieu-Daudé wrote:
>> Introduce const-qualified variants of cpu_env() and
>> env_archcpu(), to safely access CPU architecture
>> state when it should not be modified.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
>> ---
>>   include/exec/cpu-common.h | 11 +++++++++++
>>   include/hw/core/cpu.h     |  6 ++++++
>>   2 files changed, 17 insertions(+)
>>
>> diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
>> index 6594f7fa1be..f3a3799f451 100644
>> --- a/include/exec/cpu-common.h
>> +++ b/include/exec/cpu-common.h
>> @@ -79,6 +79,17 @@ static inline bool cpu_loop_exit_requested(const 
>> CPUState *cpu)
>>   }
>>   #endif /* CONFIG_TCG */
>> +/**
>> + * env_archcpu_const(env)
>> + * @env: The architecture environment (const).
>> + *
>> + * Return the const ArchCPU associated with the environment.
>> + */
>> +static inline const ArchCPU *env_archcpu_const(const CPUArchState *env)
>> +{
>> +    return (const void *)env - sizeof(CPUState);
>> +}
>> +
>>   /**
>>    * env_archcpu(env)
>>    * @env: The architecture environment
>> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
>> index 81af7b9ee1a..59f777f3f15 100644
>> --- a/include/hw/core/cpu.h
>> +++ b/include/hw/core/cpu.h
>> @@ -594,6 +594,12 @@ struct CPUState {
>>   QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) !=
>>                     sizeof(CPUState) - sizeof(CPUNegativeOffsetState));
>> +static inline const CPUArchState *cpu_env_const(const CPUState *cpu)
>> +{
>> +    /* We validate that CPUArchState follows CPUState in cpu-target.c */
>> +    return (const CPUArchState *)(cpu + 1);
>> +}
>> +
>>   static inline CPUArchState *cpu_env(CPUState *cpu)
>>   {
>>       /* We validate that CPUArchState follows CPUState in cpu- 
>> target.c */
> 
> I wonder if we can use _Generic to make this automatic, rather than have 
> to choose between two different function names.
Eh clever :) This seems to work:

   #define env_archcpu_(p) _Generic(*(p), \
                               CPUArchState: (void *)p, \
                               const CPUArchState: (const void *)p)