All of lore.kernel.org
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Animesh Manna" <animesh.manna@intel.com>
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v5 09/15] drm/i915/alpm: Modify LFPS cycle count for DP ALPM
Date: Tue, 25 Aug 2026 06:33:49 +0000	[thread overview]
Message-ID: <20260825063349.A2FEC1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260825054536.3455704-10-animesh.manna@intel.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incorrect register bit mask selection for LFPS cycle count based on connector type instead of hardware IP version.
--

--- Patch [9]: [PATCH v5 09/15] drm/i915/alpm: Modify LFPS cycle count for DP ALPM ---
commit f40607bd1107960e9e7fba56539c2f142247127f
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: Modify LFPS cycle count for DP ALPM
    
This commit modifies the display driver to set a minimum LFPS cycle
count of 16 for external DP on newer display IPs.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 98aa418a6ff77..890bf24885547 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
[ ... ]
> @@ -622,12 +635,21 @@ void intel_alpm_port_configure(struct intel_dp *intel_dp,
>  		return;
>  
>  	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
> +		int lfps_cycle = get_lfps_cycle_count(crtc_state);
> +		u32 lfps_cycle_val;
> +
> +		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> +			lfps_cycle_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(lfps_cycle);
> +		else
> +			lfps_cycle_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(lfps_cycle);
                ^^^^

[Severity: Medium]
Does this code incorrectly conflate the sink type with the display IP version?

In intel_alpm_port_configure(), branching on the connector type
(INTEL_OUTPUT_EDP) rather than the hardware IP version causes eDP panels on
Xe3LPD to be programmed using the legacy 4-bit register mask instead of the
expanded 7-bit Xe3LPD mask.

While the current default value for eDP (10 cycles) happens to fit within the
lower 4 bits, if the eDP LFPS cycle count is ever tuned to a value > 22, the
legacy 4-bit mask will truncate it and could corrupt the hardware configuration.

Should this logic check the display version instead of the output type?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054536.3455704-1-animesh.manna@intel.com?part=9

  reply	other threads:[~2026-08-25  6:33 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-25  5:45 [PATCH v5 00/15] Enable DP2.1 alpm Animesh Manna
2026-08-25  5:45 ` [PATCH v5 01/15] drm/i915/alpm: Add DPCD definition for DP2.1 ALPM capability Animesh Manna
2026-08-25  7:55   ` Kandpal, Suraj
2026-08-27 10:51     ` Manna, Animesh
2026-08-25  5:45 ` [PATCH v5 02/15] drm/i915/alpm: Move alpm sink capabality readout in separate function Animesh Manna
2026-08-25  6:28   ` sashiko-bot
2026-08-25  7:57   ` Kandpal, Suraj
2026-09-02  5:30     ` Hogander, Jouni
2026-08-25  5:45 ` [PATCH v5 03/15] drm/i915/alpm: alpm_init() for DP2.1 Animesh Manna
2026-08-25  7:44   ` sashiko-bot
2026-09-02  6:09   ` Hogander, Jouni
2026-08-25  5:45 ` [PATCH v5 04/15] drm/i915/alpm: Enable debugfs " Animesh Manna
2026-08-25  6:38   ` sashiko-bot
2026-09-02  6:14   ` Hogander, Jouni
2026-08-25  5:45 ` [PATCH v5 05/15] drm/i915/alpm: Refactor Auxless wake time calculation Animesh Manna
2026-08-25  5:45 ` [PATCH v5 06/15] drm/i915/alpm: Auxless wake time calculation for Xe3p Animesh Manna
2026-08-25  6:30   ` sashiko-bot
2026-09-02  7:22   ` Hogander, Jouni
2026-08-25  5:45 ` [PATCH v5 07/15] drm/i915/alpm: table based establishment period Animesh Manna
2026-08-25  6:34   ` sashiko-bot
2026-09-02  7:24   ` Hogander, Jouni
2026-08-25  5:45 ` [PATCH v5 08/15] drm/i915/alpm: Half LFPS cycle calculation Animesh Manna
2026-08-25  6:31   ` sashiko-bot
2026-09-02  8:41   ` Hogander, Jouni
2026-09-02  9:30     ` Hogander, Jouni
2026-08-25  5:45 ` [PATCH v5 09/15] drm/i915/alpm: Modify LFPS cycle count for DP ALPM Animesh Manna
2026-08-25  6:33   ` sashiko-bot [this message]
2026-09-02  8:49   ` Hogander, Jouni
2026-08-25  5:45 ` [PATCH v5 10/15] drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM Animesh Manna
2026-08-25  6:32   ` sashiko-bot
2026-09-02  9:27   ` Hogander, Jouni
2026-09-15  2:58     ` Manna, Animesh
2026-08-25  5:45 ` [PATCH v5 11/15] drm/i915/alpm: Enable MAC Transmitting LFPS for LT PHY Animesh Manna
2026-09-02  9:37   ` Hogander, Jouni
2026-09-15  3:34     ` Manna, Animesh
2026-08-25  5:45 ` [PATCH v5 12/15] drm/i915/alpm: Replace is_edp() with alpm_is_possible() Animesh Manna
2026-08-25  6:43   ` sashiko-bot
2026-09-02  9:49   ` Hogander, Jouni
2026-09-15  4:15     ` Manna, Animesh
2026-08-25  5:45 ` [PATCH v5 13/15] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf Animesh Manna
2026-08-25  6:35   ` sashiko-bot
2026-09-02 10:04   ` Hogander, Jouni
2026-08-25  5:45 ` [PATCH v5 14/15] drm/i915/alpm: Compute and program switch to active latency Animesh Manna
2026-08-25  6:39   ` sashiko-bot
2026-09-02 10:10   ` Hogander, Jouni
2026-08-25  5:45 ` [PATCH v5 15/15] drm/i915/alpm: Program zero-based LFPS half cycle duration Animesh Manna
2026-08-25  6:40   ` sashiko-bot
2026-09-02 10:17   ` Hogander, Jouni
2026-08-25  7:11 ` ✓ i915.CI.BAT: success for Enable DP2.1 alpm (rev5) Patchwork
2026-08-25 11:12 ` ✗ i915.CI.Full: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260825063349.A2FEC1F000E9@smtp.kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=animesh.manna@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=sashiko-reviews@lists.linux.dev \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.