Re: [PATCH v5 09/15] drm/i915/alpm: Modify LFPS cycle count for DP ALPM

["Hogander, Jouni" <jouni.hogander@intel.com>]

On Tue, 2026-08-25 at 11:15 +0530, Animesh Manna wrote:
> For DP minimum LFPS count is set to minimum 16.
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c     | 28
> +++++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_psr_regs.h |  2 ++
>  2 files changed, 27 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 98aa418a6ff7..890bf2488554 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -24,7 +24,8 @@
>  				(SILENCE_PERIOD_MAX_TIME -	\
>  				 SILENCE_PERIOD_MIN_TIME) / 2)
>  
> -#define LFPS_CYCLE_COUNT 10
> +#define LFPS_CYCLE_COUNT	10
> +#define LFPS_CYCLE_COUNT_DP	16
>  
>  bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)
>  {
> @@ -105,10 +106,22 @@ static int get_lfps_cycle_time(const struct
> intel_crtc_state *crtc_state)
>  	return tlfps_cycle_min +  (tlfps_cycle_max -
> tlfps_cycle_min) / 2;
>  }
>  
> +static int get_lfps_cycle_count(const struct intel_crtc_state
> *crtc_state)
> +{
> +	struct intel_display *display =
> to_intel_display(crtc_state);
> +
> +	/* External DP on Xe3lpd+ uses a minimum of 16 LFPS cycles.
> */
> +	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
> +	    DISPLAY_VER(display) >= 35)
> +		return LFPS_CYCLE_COUNT_DP;

I think it is enough to differentiate between eDP and DP. No need to
check display version.

> +
> +	return LFPS_CYCLE_COUNT;
> +}
> +
>  static int get_lfps_half_cycle_clocks(const struct intel_crtc_state
> *crtc_state)
>  {
>  	return get_lfps_cycle_time(crtc_state) * crtc_state-
> >port_clock / 1000 /
> -		1000 / (2 * LFPS_CYCLE_COUNT);
> +		1000 / (2 * get_lfps_cycle_count(crtc_state));
>  }
>  
>  #define ML_PHY_LOCK_LEN		252
> @@ -622,12 +635,21 @@ void intel_alpm_port_configure(struct intel_dp
> *intel_dp,
>  		return;
>  
>  	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
> +		int lfps_cycle = get_lfps_cycle_count(crtc_state);
> +		u32 lfps_cycle_val;
> +
> +		if (intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_EDP))

Here the difference is dependent on display version. Also split this as
a separate patch.

BR,
Jouni Högander

> +			lfps_cycle_val =
> PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(lfps_cycle);
> +		else
> +			lfps_cycle_val =
> PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(lfps_cycle);
> +
>  		alpm_ctl_val = PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
>  			PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
>  			PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
>  			PORT_ALPM_CTL_SILENCE_PERIOD(
>  				crtc_state-
> >alpm_state.silence_period_sym_clocks);
> -		lfps_ctl_val =
> PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(LFPS_CYCLE_COUNT) |
> +
> +		lfps_ctl_val = lfps_cycle_val |
>  			PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
>  				crtc_state-
> >alpm_state.lfps_half_cycle_num_of_syms) |
>  			PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DUR
> ATION(
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 8ec99bbd84b6..d33e9b0a81d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -333,8 +333,10 @@
>  #define
> PORT_ALPM_LFPS_CTL(port)				_MMIO_PORT(port, _PORT_ALPM_LFPS_CTL_A, _PORT_ALPM_LFPS_CTL_B)
>  #define 
> PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY			REG_BIT(31)
>  #define 
> PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK		REG_GENMASK(27, 24)
> +#define 
> PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK_XE3LPD	REG_GENMASK(30, 24)
>  #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN		7
>  #define 
> PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val)		REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK,(val)-PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
> +#define 
> PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK_XE3LPD,(val)-PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
>  #define 
> PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(20, 16)
>  #define 
> PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK,val)
>  #define 
> PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(12
> , 8)