From: sashiko-bot@kernel.org
To: "Animesh Manna" <animesh.manna@intel.com>
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v5 07/15] drm/i915/alpm: table based establishment period
Date: Tue, 25 Aug 2026 06:34:19 +0000 [thread overview]
Message-ID: <20260825063420.635F31F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260825054536.3455704-8-animesh.manna@intel.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
New issues:
- [High] Unchecked negative error codes from drm_dp_lttpr_count() cause an out-of-bounds array read and integer underflow.
Pre-existing issues:
- [High] 32-bit signed integer overflow in `tml_phy_lock` calculation corrupts ALPM wake time.
--
--- Patch [7]: [PATCH v5 07/15] drm/i915/alpm: table based establishment period ---
commit 39688e03d0da05abea5d53e9441ff2410c77a69c
Author: Animesh Manna <animesh.manna@intel.com>
Subject: drm/i915/alpm: table based establishment period
This patch introduces a table-based lookup for the establishment period
in intel_alpm.c. It uses the link rate and LTTPR count to find the period
from a 2D array, falling back to a computed value if not found.
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index af2733805505e..078e04bb69d29 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
[ ... ]
> @@ -129,8 +215,17 @@ static int get_establishment_period(struct intel_dp *intel_dp,
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
[Severity: High]
This isn't a bug introduced by this patch, but does the calculation for
tml_phy_lock suffer from a 32-bit signed integer overflow?
Looking earlier in get_establishment_period():
int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock / 10;
The expression 1000 * 1000 * tps4 evaluates using 32-bit signed integer
math. For both DP (tps4 = 2520) and UHBR (tps4 = 12672), the intermediate
result exceeds INT_MAX (2,147,483,647) and overflows (to -212643840 for
UHBR). This negative value propagates into tml_phy_lock and causes tcds to
subtract time instead of adding it, which could corrupt the ALPM wake time.
> } else {
> + int idx = get_link_rate_index(crtc_state->port_clock);
> +
> tcds = 7 * tml_phy_lock;
> lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
> +
> + if (idx != LINK_RATE_INVALID &&
> + lttpr_count < DEFAULT_MAX_LTTPR_COUNT &&
[Severity: High]
If a buggy or malicious DP sink returns an invalid LTTPR configuration,
drm_dp_lttpr_count() can return a negative error code (e.g., -ERANGE
or -EINVAL). Since lttpr_count is signed, will it incorrectly pass this
lttpr_count < DEFAULT_MAX_LTTPR_COUNT check?
> + establishment_periods[lttpr_count][idx]) {
> + establishment_period = establishment_periods[lttpr_count][idx];
Could this negative lttpr_count then be used as an array index on this
line, causing an out-of-bounds memory read? If the out-of-bounds read
accesses an unmapped page it could trigger a kernel oops.
Furthermore, if the lookup is bypassed, the negative lttpr_count could cause
severe integer underflow in the fallback calculation later in this function:
int tdcs = (SILENCE_PERIOD_TIME + t1 + tcs +
(lttpr_count - 1) * (tlw + tlfps_period));
> + return establishment_period;
> + }
> }
>
> if (lttpr_count) {
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260825054536.3455704-1-animesh.manna@intel.com?part=7
next prev parent reply other threads:[~2026-08-25 6:34 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-25 5:45 [PATCH v5 00/15] Enable DP2.1 alpm Animesh Manna
2026-08-25 5:45 ` [PATCH v5 01/15] drm/i915/alpm: Add DPCD definition for DP2.1 ALPM capability Animesh Manna
2026-08-25 7:55 ` Kandpal, Suraj
2026-08-27 10:51 ` Manna, Animesh
2026-08-25 5:45 ` [PATCH v5 02/15] drm/i915/alpm: Move alpm sink capabality readout in separate function Animesh Manna
2026-08-25 6:28 ` sashiko-bot
2026-08-25 7:57 ` Kandpal, Suraj
2026-09-02 5:30 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 03/15] drm/i915/alpm: alpm_init() for DP2.1 Animesh Manna
2026-08-25 7:44 ` sashiko-bot
2026-09-02 6:09 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 04/15] drm/i915/alpm: Enable debugfs " Animesh Manna
2026-08-25 6:38 ` sashiko-bot
2026-09-02 6:14 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 05/15] drm/i915/alpm: Refactor Auxless wake time calculation Animesh Manna
2026-08-25 5:45 ` [PATCH v5 06/15] drm/i915/alpm: Auxless wake time calculation for Xe3p Animesh Manna
2026-08-25 6:30 ` sashiko-bot
2026-09-02 7:22 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 07/15] drm/i915/alpm: table based establishment period Animesh Manna
2026-08-25 6:34 ` sashiko-bot [this message]
2026-09-02 7:24 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 08/15] drm/i915/alpm: Half LFPS cycle calculation Animesh Manna
2026-08-25 6:31 ` sashiko-bot
2026-09-02 8:41 ` Hogander, Jouni
2026-09-02 9:30 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 09/15] drm/i915/alpm: Modify LFPS cycle count for DP ALPM Animesh Manna
2026-08-25 6:33 ` sashiko-bot
2026-09-02 8:49 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 10/15] drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM Animesh Manna
2026-08-25 6:32 ` sashiko-bot
2026-09-02 9:27 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 11/15] drm/i915/alpm: Enable MAC Transmitting LFPS for LT PHY Animesh Manna
2026-09-02 9:37 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 12/15] drm/i915/alpm: Replace is_edp() with alpm_is_possible() Animesh Manna
2026-08-25 6:43 ` sashiko-bot
2026-09-02 9:49 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 13/15] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf Animesh Manna
2026-08-25 6:35 ` sashiko-bot
2026-09-02 10:04 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 14/15] drm/i915/alpm: Compute and program switch to active latency Animesh Manna
2026-08-25 6:39 ` sashiko-bot
2026-09-02 10:10 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 15/15] drm/i915/alpm: Program zero-based LFPS half cycle duration Animesh Manna
2026-08-25 6:40 ` sashiko-bot
2026-09-02 10:17 ` Hogander, Jouni
2026-08-25 7:11 ` ✓ i915.CI.BAT: success for Enable DP2.1 alpm (rev5) Patchwork
2026-08-25 7:59 ` ✗ CI.checkpatch: warning " Patchwork
2026-08-25 8:01 ` ✓ CI.KUnit: success " Patchwork
2026-08-25 8:41 ` ✓ Xe.CI.BAT: " Patchwork
2026-08-25 11:12 ` ✗ i915.CI.Full: failure " Patchwork
2026-08-25 12:23 ` ✓ Xe.CI.FULL: success " Patchwork
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