From: "Hogander, Jouni" <jouni.hogander@intel.com>
To: "intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
"Manna, Animesh" <animesh.manna@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "Kandpal, Suraj" <suraj.kandpal@intel.com>,
"Nikula, Jani" <jani.nikula@intel.com>
Subject: Re: [PATCH v5 10/15] drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM
Date: Wed, 2 Sep 2026 09:27:14 +0000 [thread overview]
Message-ID: <fa29aad5aaab3725d9653def18afa6407002b67d.camel@intel.com> (raw)
In-Reply-To: <20260825054536.3455704-11-animesh.manna@intel.com>
On Tue, 2026-08-25 at 11:15 +0530, Animesh Manna wrote:
> Issue a AUX write transaction to DPCD DP_TOTAL_LTTPR_CNT (0xf000a)
> with total number of LTTPR before link training.
>
> v2: Cosmetic changes. [Suraj]
>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_alpm.c | 9 ++++++++-
> .../drm/i915/display/intel_dp_link_training.c | 16
> ++++++++++++++++
> 2 files changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 890bf2488554..d23f3bdf1339 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -563,7 +563,7 @@ static void lnl_alpm_configure(struct intel_dp
> *intel_dp,
> {
> struct intel_display *display = to_intel_display(intel_dp);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> - u32 alpm_ctl;
> + u32 alpm_ctl, alpm_ctl2, lttpr_count;
>
> if (DISPLAY_VER(display) < 20 ||
> (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
> !crtc_state->has_lobf))
> @@ -613,6 +613,13 @@ static void lnl_alpm_configure(struct intel_dp
> *intel_dp,
>
> alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(crtc_state-
> >alpm_state.check_entry_lines);
>
> + lttpr_count = drm_dp_lttpr_count(intel_dp-
> >lttpr_common_caps);
> +
> + alpm_ctl2 = intel_de_read(display, ALPM_CTL2(display,
> cpu_transcoder));
Why you are reading this. Can't we just configure alpm_ctl2 as we want
and then write that one?
> + alpm_ctl2 &= ~ALPM_CTL2_NUMBER_OF_LTTPR_MASK;
> + alpm_ctl2 |= ALPM_CTL2_NUMBER_OF_LTTPR(lttpr_count);
> +
> + intel_de_write(display, ALPM_CTL2(display, cpu_transcoder),
> alpm_ctl2);
> intel_de_write(display, ALPM_CTL(display, cpu_transcoder),
> alpm_ctl);
> mutex_unlock(&intel_dp->alpm.lock);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index cb92cff90614..1d5873cb64f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -2265,6 +2265,20 @@ intel_dp_128b132b_link_train(struct intel_dp
> *intel_dp,
> return passed;
> }
>
> +static void intel_dp_update_lttpr_count(struct intel_dp *intel_dp,
> + int lttpr_count)
> +{
> + /*
> + * Program only for DP2.1 and return if LTTPR revison is
> less than 0x20
> + * where 0:3 represents minor rev and 4:7 represent major
> rev
> + */
> + if (!intel_dp_is_edp(intel_dp) ||
> + intel_dp->lttpr_common_caps[0] <= 0x20)
> + return;
> +
"The DPTX shall issue an AUX write transaction to the DPCD register
with the value
determined from the PHY_REPEATER_CNT and same encoding defined for DPCD
F0002h."
I.e. You can't just write count as it is.
> + drm_dp_dpcd_writeb(&intel_dp->aux, DP_TOTAL_LTTPR_CNT,
> lttpr_count);
> +}
> +
> /**
> * intel_dp_start_link_train - start link training
> * @state: Atomic state
> @@ -2304,6 +2318,8 @@ void intel_dp_start_link_train(struct
> intel_atomic_state *state,
>
> intel_dp_prepare_link_train(intel_dp, crtc_state);
>
> + intel_dp_update_lttpr_count(intel_dp, lttpr_count);
How about having this in intel_alpm_enable_sink?
BR,
Jouni Högander
> +
> if (intel_dp_is_uhbr(crtc_state))
> passed = intel_dp_128b132b_link_train(intel_dp,
> crtc_state, lttpr_count);
> else
next prev parent reply other threads:[~2026-09-02 9:27 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-25 5:45 [PATCH v5 00/15] Enable DP2.1 alpm Animesh Manna
2026-08-25 5:45 ` [PATCH v5 01/15] drm/i915/alpm: Add DPCD definition for DP2.1 ALPM capability Animesh Manna
2026-08-25 7:55 ` Kandpal, Suraj
2026-08-27 10:51 ` Manna, Animesh
2026-08-25 5:45 ` [PATCH v5 02/15] drm/i915/alpm: Move alpm sink capabality readout in separate function Animesh Manna
2026-08-25 6:28 ` sashiko-bot
2026-08-25 7:57 ` Kandpal, Suraj
2026-09-02 5:30 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 03/15] drm/i915/alpm: alpm_init() for DP2.1 Animesh Manna
2026-08-25 7:44 ` sashiko-bot
2026-09-02 6:09 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 04/15] drm/i915/alpm: Enable debugfs " Animesh Manna
2026-08-25 6:38 ` sashiko-bot
2026-09-02 6:14 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 05/15] drm/i915/alpm: Refactor Auxless wake time calculation Animesh Manna
2026-08-25 5:45 ` [PATCH v5 06/15] drm/i915/alpm: Auxless wake time calculation for Xe3p Animesh Manna
2026-08-25 6:30 ` sashiko-bot
2026-09-02 7:22 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 07/15] drm/i915/alpm: table based establishment period Animesh Manna
2026-08-25 6:34 ` sashiko-bot
2026-09-02 7:24 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 08/15] drm/i915/alpm: Half LFPS cycle calculation Animesh Manna
2026-08-25 6:31 ` sashiko-bot
2026-09-02 8:41 ` Hogander, Jouni
2026-09-02 9:30 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 09/15] drm/i915/alpm: Modify LFPS cycle count for DP ALPM Animesh Manna
2026-08-25 6:33 ` sashiko-bot
2026-09-02 8:49 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 10/15] drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM Animesh Manna
2026-08-25 6:32 ` sashiko-bot
2026-09-02 9:27 ` Hogander, Jouni [this message]
2026-09-15 2:58 ` Manna, Animesh
2026-08-25 5:45 ` [PATCH v5 11/15] drm/i915/alpm: Enable MAC Transmitting LFPS for LT PHY Animesh Manna
2026-09-02 9:37 ` Hogander, Jouni
2026-09-15 3:34 ` Manna, Animesh
2026-08-25 5:45 ` [PATCH v5 12/15] drm/i915/alpm: Replace is_edp() with alpm_is_possible() Animesh Manna
2026-08-25 6:43 ` sashiko-bot
2026-09-02 9:49 ` Hogander, Jouni
2026-09-15 4:15 ` Manna, Animesh
2026-08-25 5:45 ` [PATCH v5 13/15] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf Animesh Manna
2026-08-25 6:35 ` sashiko-bot
2026-09-02 10:04 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 14/15] drm/i915/alpm: Compute and program switch to active latency Animesh Manna
2026-08-25 6:39 ` sashiko-bot
2026-09-02 10:10 ` Hogander, Jouni
2026-08-25 5:45 ` [PATCH v5 15/15] drm/i915/alpm: Program zero-based LFPS half cycle duration Animesh Manna
2026-08-25 6:40 ` sashiko-bot
2026-09-02 10:17 ` Hogander, Jouni
2026-08-25 7:11 ` ✓ i915.CI.BAT: success for Enable DP2.1 alpm (rev5) Patchwork
2026-08-25 7:59 ` ✗ CI.checkpatch: warning " Patchwork
2026-08-25 8:01 ` ✓ CI.KUnit: success " Patchwork
2026-08-25 8:41 ` ✓ Xe.CI.BAT: " Patchwork
2026-08-25 11:12 ` ✗ i915.CI.Full: failure " Patchwork
2026-08-25 12:23 ` ✓ Xe.CI.FULL: success " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=fa29aad5aaab3725d9653def18afa6407002b67d.camel@intel.com \
--to=jouni.hogander@intel.com \
--cc=animesh.manna@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
--cc=suraj.kandpal@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.