All of lore.kernel.org
 help / color / mirror / Atom feed
From: Jason Gunthorpe <jgg@nvidia.com>
To: Will Deacon <will@kernel.org>
Cc: Robin Murphy <robin.murphy@arm.com>,
	Vijayanand Jitta <vijayanand.jitta@oss.qualcomm.com>,
	Mostafa Saleh <smostafa@google.com>,
	iommu@lists.linux.dev, "Joerg Roedel (AMD)" <joro@8bytes.org>,
	Jean-Philippe Brucker <jpb@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	David Matlack <dmatlack@google.com>,
	Pasha Tatashin <pasha.tatashin@soleen.com>,
	patches@lists.linux.dev, Pranjal Shrivastava <praan@google.com>,
	Samiullah Khawaja <skhawaja@google.com>
Subject: Re: [PATCH v2 3/8] iommu/arm-smmu-v3: Optimize range invalidation for latency
Date: Tue, 25 Aug 2026 14:20:09 -0300	[thread overview]
Message-ID: <20260825172009.GC3325090@nvidia.com> (raw)
In-Reply-To: <ao3LpdSgK7ZBrLza@willie-the-truck>

On Tue, Aug 25, 2026 at 06:06:45PM +0100, Will Deacon wrote:
> The documentation for 3673557 gives a possible workaround of:
> 
>   - When invalidating a contiguous set of page tables, perform the
>     invalidation sequence twice. Only the invalidation sequence needs to
>     be performed twice, not the SYNC.
> 
> and we just merged something very similar from Ashish. Could we use that
> for domains that want to use contiguous ptes?

I figured out a way to bound it to at most 3 RILs (and that is rare,
mostly it is two RILs), so double invalidation would be at least 4
RILs using Robin's trick and way more using the existing algorithm.

So it would work but I'm happy enough with the 3 RIL path + SVA over
invalidation. I was just waiting for one testing result before posting
the series but it is on my github..

https://github.com/jgunthorpe/linux/tree/iommu_pt_arm64 

Jason


  reply	other threads:[~2026-08-25 17:20 UTC|newest]

Thread overview: 63+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-06 16:26 [PATCH v2 0/8] Organize the SMMUv3 invalidation flow so iommupt can use it Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 1/8] iommu/arm-smmu-v3: Pass the parameters for the invalidation in a struct Jason Gunthorpe
2026-07-07  3:04   ` Nicolin Chen
2026-07-07 11:18   ` Mostafa Saleh
2026-07-06 16:26 ` [PATCH v2 2/8] iommu/arm-smmu-v3: Move pgsize out of arm_smmu_inv Jason Gunthorpe
2026-07-07  3:57   ` Nicolin Chen
2026-07-07 16:15     ` Jason Gunthorpe
2026-07-07 17:21       ` Nicolin Chen
2026-07-08 18:43         ` Jason Gunthorpe
2026-07-07 11:24   ` Mostafa Saleh
2026-07-07 18:08     ` Jason Gunthorpe
2026-07-11 17:38       ` Daniel Mentz
2026-07-14 18:41         ` Jason Gunthorpe
2026-07-10  4:06   ` Daniel Mentz
2026-07-10 14:28     ` Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 3/8] iommu/arm-smmu-v3: Optimize range invalidation for latency Jason Gunthorpe
2026-07-07  7:27   ` Nicolin Chen
2026-07-07 19:13     ` Jason Gunthorpe
2026-07-07 21:07       ` Nicolin Chen
2026-07-07 11:45   ` Mostafa Saleh
2026-07-08  0:10     ` Jason Gunthorpe
2026-08-13 13:53       ` Mostafa Saleh
2026-08-13 14:13         ` Jason Gunthorpe
2026-08-13 15:12           ` Mostafa Saleh
2026-08-13 17:05             ` Jason Gunthorpe
2026-08-13 17:25             ` Robin Murphy
2026-08-13 18:01               ` Jason Gunthorpe
2026-08-14  8:39                 ` Will Deacon
2026-08-14 12:34                   ` Jason Gunthorpe
2026-08-18 18:43                     ` Jason Gunthorpe
2026-08-25 17:06                       ` Will Deacon
2026-08-25 17:20                         ` Jason Gunthorpe [this message]
2026-07-06 16:26 ` [PATCH v2 4/8] iommu/arm-smmu-v3: Keep track in the arm_smmu_invs if RIL is used Jason Gunthorpe
2026-07-07  7:27   ` Nicolin Chen
2026-07-07 11:46   ` Mostafa Saleh
2026-07-06 16:26 ` [PATCH v2 5/8] iommu/arm-smmu-v3: Precompute the invalidation commands Jason Gunthorpe
2026-07-07 11:52   ` Mostafa Saleh
2026-07-07 14:58     ` Jason Gunthorpe
2026-07-08  9:00       ` Mostafa Saleh
2026-07-08 13:15         ` Jason Gunthorpe
2026-07-07 20:31   ` Nicolin Chen
2026-07-09 12:07     ` Jason Gunthorpe
2026-07-09 19:10       ` Nicolin Chen
2026-07-06 16:26 ` [PATCH v2 6/8] iommu/arm-smmu-v3: Populate the tlbi at the top of the call chain Jason Gunthorpe
2026-07-07 11:57   ` Mostafa Saleh
2026-07-08 18:09     ` Jason Gunthorpe
2026-07-07 21:51   ` Nicolin Chen
2026-07-08 18:40     ` Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 7/8] iommu/arm-smmu-v3: Change how the tlbi describes the invalidation Jason Gunthorpe
2026-07-06 18:00   ` Robin Murphy
2026-07-06 19:45     ` Jason Gunthorpe
2026-07-08  1:41   ` Nicolin Chen
2026-07-08 18:27     ` Jason Gunthorpe
2026-07-08  5:29   ` Nicolin Chen
2026-07-09 18:25     ` Jason Gunthorpe
2026-07-09 21:32       ` Nicolin Chen
2026-07-06 16:26 ` [PATCH v2 8/8] iommu/arm-smmu-v3: Support the DS expansion of RIL's SCALE Jason Gunthorpe
2026-07-07 23:20   ` Nicolin Chen
2026-07-08  0:02     ` Jason Gunthorpe
2026-07-08  2:10       ` Nicolin Chen
2026-07-08 13:05         ` Jason Gunthorpe
2026-07-07 12:25 ` [PATCH v2 0/8] Organize the SMMUv3 invalidation flow so iommupt can use it Mostafa Saleh
2026-07-07 15:00   ` Jason Gunthorpe

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260825172009.GC3325090@nvidia.com \
    --to=jgg@nvidia.com \
    --cc=dmatlack@google.com \
    --cc=iommu@lists.linux.dev \
    --cc=joro@8bytes.org \
    --cc=jpb@kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=pasha.tatashin@soleen.com \
    --cc=patches@lists.linux.dev \
    --cc=praan@google.com \
    --cc=robin.murphy@arm.com \
    --cc=skhawaja@google.com \
    --cc=smostafa@google.com \
    --cc=vijayanand.jitta@oss.qualcomm.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.