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From: Chinmay Rath <rathc@linux.ibm.com>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
	harshpb@linux.ibm.com, milesg@linux.ibm.com
Cc: npiggin@gmail.com, richard.henderson@linaro.org,
	vishalc@linux.ibm.com, tshah@linux.ibm.com,
	shivangu@linux.ibm.com, ojaswin@linux.ibm.com,
	aboorvad@linux.ibm.com, amachhiw@linux.ibm.com,
	shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com,
	nikhilks@linux.ibm.com, Chinmay Rath <rathc@linux.ibm.com>
Subject: [PATCH v2 19/37] target/ppc: Refactor sleep and its variants to use a common helper
Date: Wed, 26 Aug 2026 10:38:45 +0530	[thread overview]
Message-ID: <20260826050923.74756-20-rathc@linux.ibm.com> (raw)
In-Reply-To: <20260826050923.74756-1-rathc@linux.ibm.com>

From: Ojaswin Mujoo <ojaswin@linux.ibm.com>

With sleep, doze, nap, rvwinkle and stop instructions moved to
decodetree, the helper these instructions used : gen_helper_pminsn,
should now be renamed to gen_helper_PMINSN, abiding by the decodetree
standards. Do the same.
Also refactor their translation routine to use a common do_sleep routine
since they share majority of the code.

Signed-off-by: Ojaswin Mujoo <ojaswin@linux.ibm.com>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
---
 target/ppc/helper.h                           |  2 +-
 target/ppc/tcg-excp_helper.c                  |  2 +-
 .../ppc/translate/processor-ctrl-impl.c.inc   | 99 +++----------------
 3 files changed, 16 insertions(+), 87 deletions(-)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index cd2a0948a3..7e15676122 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -18,7 +18,7 @@ DEF_HELPER_1(rfdi, void, env)
 DEF_HELPER_1(rfmci, void, env)
 #if defined(TARGET_PPC64)
 DEF_HELPER_2(scv, noreturn, env, i32)
-DEF_HELPER_2(pminsn, void, env, i32)
+DEF_HELPER_2(PMINSN, void, env, i32)
 DEF_HELPER_1(rfid, void, env)
 DEF_HELPER_1(rfscv, void, env)
 DEF_HELPER_1(hrfid, void, env)
diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c
index b04f07a637..c4ffa2dfbb 100644
--- a/target/ppc/tcg-excp_helper.c
+++ b/target/ppc/tcg-excp_helper.c
@@ -459,7 +459,7 @@ void helper_scv(CPUPPCState *env, uint32_t lev)
     }
 }
 
-void helper_pminsn(CPUPPCState *env, uint32_t insn)
+void helper_PMINSN(CPUPPCState *env, uint32_t insn)
 {
     CPUState *cs = env_cpu(env);
 
diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc b/target/ppc/translate/processor-ctrl-impl.c.inc
index bdbc195294..3b3ed3019a 100644
--- a/target/ppc/translate/processor-ctrl-impl.c.inc
+++ b/target/ppc/translate/processor-ctrl-impl.c.inc
@@ -104,103 +104,32 @@ static bool trans_MSGSYNC(DisasContext *ctx, arg_MSGSYNC *a)
     return true;
 }
 
-static bool do_doze(DisasContext *ctx, arg_DOZE *a)
-{
-    REQUIRE_64BIT(ctx);
-
-#if defined(CONFIG_USER_ONLY)
-    gen_priv_opc(ctx);
-#else
-    TCGv_i32 t;
-
-    REQUIRE_HV(ctx);
-    translator_io_start(&ctx->base);
-    t = tcg_constant_i32(PPC_PM_DOZE);
-    gen_helper_pminsn(tcg_env, t);
-    /* Stop translation, as the CPU is supposed to sleep from now */
-    gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
-#endif /* defined(CONFIG_USER_ONLY) */
-
-    return true;
-}
-TRANS_FLAGS2(PM_ISA206, DOZE, do_doze);
-
-static bool do_nap(DisasContext *ctx, arg_NAP *a)
-{
-    REQUIRE_64BIT(ctx);
-
-#if defined(CONFIG_USER_ONLY)
-    gen_priv_opc(ctx);
-#else
-    TCGv_i32 t;
-
-    REQUIRE_HV(ctx);
-    translator_io_start(&ctx->base);
-    t = tcg_constant_i32(PPC_PM_NAP);
-    gen_helper_pminsn(tcg_env, t);
-    /* Stop translation, as the CPU is supposed to sleep from now */
-    gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
-#endif /* defined(CONFIG_USER_ONLY) */
-    return true;
-}
-TRANS_FLAGS2(PM_ISA206, NAP, do_nap);
-
-static bool do_sleep(DisasContext *ctx, arg_SLEEP *a)
-{
-    REQUIRE_64BIT(ctx);
-
-#if defined(CONFIG_USER_ONLY)
-    gen_priv_opc(ctx);
-#else
-    TCGv_i32 t;
-
-    REQUIRE_HV(ctx);
-    translator_io_start(&ctx->base);
-    t = tcg_constant_i32(PPC_PM_SLEEP);
-    gen_helper_pminsn(tcg_env, t);
-    /* Stop translation, as the CPU is supposed to sleep from now */
-    gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
-#endif /* defined(CONFIG_USER_ONLY) */
-    return true;
-}
-TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep);
-
-static bool do_rvwinkle(DisasContext *ctx, arg_RVWINKLE *a)
+/*
+ * Helper to handle DOZE, NAP, SLEEP, RVWINKLE & STOP. Since none of them use
+ * any arguments just use a placeholder arg_SLEEP.
+ */
+static bool do_sleep(DisasContext *ctx, arg_SLEEP *a, powerpc_pm_insn_t type)
 {
     REQUIRE_64BIT(ctx);
 
 #if defined(CONFIG_USER_ONLY)
     gen_priv_opc(ctx);
-#else
+#elif defined(TARGET_PPC64)
     TCGv_i32 t;
 
     REQUIRE_HV(ctx);
     translator_io_start(&ctx->base);
-    t = tcg_constant_i32(PPC_PM_RVWINKLE);
-    gen_helper_pminsn(tcg_env, t);
+    t = tcg_constant_i32(type);
+    gen_helper_PMINSN(tcg_env, t);
     /* Stop translation, as the CPU is supposed to sleep from now */
     gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
-#endif /* defined(CONFIG_USER_ONLY) */
-    return true;
-}
-TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_rvwinkle);
-
-static bool do_stop(DisasContext *ctx, arg_STOP *a)
-{
-    REQUIRE_64BIT(ctx);
-
-#if defined(CONFIG_USER_ONLY)
-    gen_priv_opc(ctx);
 #else
-    TCGv_i32 t;
-
-    REQUIRE_HV(ctx);
-    translator_io_start(&ctx->base);
-    t = tcg_constant_i32(PPC_PM_STOP);
-    gen_helper_pminsn(tcg_env, t);
-    /* Stop translation, as the CPU is supposed to sleep from now */
-    gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next);
+    qemu_build_not_reached();
 #endif
     return true;
 }
-TRANS_FLAGS2(ISA300, STOP, do_stop);
+TRANS_FLAGS2(PM_ISA206, DOZE, do_sleep, PPC_PM_DOZE);
+TRANS_FLAGS2(PM_ISA206, NAP, do_sleep, PPC_PM_NAP);
+TRANS_FLAGS2(PM_ISA206, SLEEP, do_sleep, PPC_PM_SLEEP);
+TRANS_FLAGS2(PM_ISA206, RVWINKLE, do_sleep, PPC_PM_RVWINKLE);
+TRANS_FLAGS2(ISA300, STOP, do_sleep, PPC_PM_STOP);
-- 
2.55.0



  parent reply	other threads:[~2026-08-26  5:11 UTC|newest]

Thread overview: 83+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-26  5:08 [PATCH v2 00/37] target/ppc: PPC TCG Improvements (decodetree migrations + ISA 2.07 flag updates) Chinmay Rath
2026-08-26  5:08 ` [PATCH v2 01/37] target/ppc: Migrate extswsli to decodetree Chinmay Rath
2026-08-26  7:33   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 02/37] target/ppc: Migrate atomic loads " Chinmay Rath
2026-08-26  9:20   ` Amit Machhiwal
2026-08-26 12:28     ` Chinmay Rath
2026-08-26 12:30       ` Chinmay Rath
2026-08-26  5:08 ` [PATCH v2 03/37] target/ppc: Convert cache instructions " Chinmay Rath
2026-08-26 10:20   ` Amit Machhiwal
2026-08-26 13:09     ` Chinmay Rath
2026-08-26 13:17       ` Amit Machhiwal
2026-08-27  9:13       ` Chinmay Rath
2026-08-27  8:37     ` Chinmay Rath
2026-08-26  5:08 ` [PATCH v2 04/37] target/ppc: Move vector merge " Chinmay Rath
2026-08-26 10:57   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 05/37] target/ppc: Move vector pack " Chinmay Rath
2026-08-26 11:04   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 06/37] target/ppc: Move st{b, h, w, d, q}cx " Chinmay Rath
2026-08-26 11:18   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 07/37] target/ppc: convert slw, srw instruction via decode spec Chinmay Rath
2026-08-26 11:28   ` Amit Machhiwal
2026-08-26 11:30     ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 08/37] target/ppc: convert sraw[i] " Chinmay Rath
2026-08-26 11:41   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 09/37] target/ppc: Convert mcrf to decode tree Chinmay Rath
2026-08-26 11:52   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 10/37] target/ppc: Move fixed-point Shift insns to decodetree Chinmay Rath
2026-08-26  5:08 ` [PATCH v2 11/37] target/ppc: Move fixed-point byte-reversal store " Chinmay Rath
2026-08-26  5:08 ` [PATCH v2 12/37] target/ppc: Move GPR atomic load/store instructions " Chinmay Rath
2026-08-26 12:05   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 13/37] target/ppc: Move isync instruction " Chinmay Rath
2026-08-26 12:20   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 14/37] target/ppc: Convert b{a, l, la} to decode tree Chinmay Rath
2026-08-26 12:24   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 15/37] target/ppc: move various conditional branch insns to decodetree Chinmay Rath
2026-08-26 12:38   ` Amit Machhiwal
2026-08-26 12:45   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 16/37] target/ppc: Fix TRANS* macro variadic arguments handling Chinmay Rath
2026-08-26 12:50   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 17/37] target/ppc: Move wait instruction to decodetree Chinmay Rath
2026-08-26 13:12   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 18/37] target/ppc: Move sleep & friends " Chinmay Rath
2026-08-26 13:26   ` Amit Machhiwal
2026-08-26  5:08 ` Chinmay Rath [this message]
2026-08-26 13:38   ` [PATCH v2 19/37] target/ppc: Refactor sleep and its variants to use a common helper Amit Machhiwal
2026-08-26 14:30   ` Miles Glenn
2026-08-26  5:08 ` [PATCH v2 20/37] target/ppc: Move Condition Register access instructions to decodetree Chinmay Rath
2026-08-26 14:24   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 21/37] target/ppc: Move Condition Register logical " Chinmay Rath
2026-08-26 14:43   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 22/37] target/ppc: make do_ea_calc_ra available for 32 bit builds Chinmay Rath
2026-08-26 14:48   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 23/37] target/ppc: Move Fixed-Point Load/Store String instructions to decodetree Chinmay Rath
2026-08-26 15:19   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 24/37] target/ppc: Move VMX integer arithmetic and BCD " Chinmay Rath
2026-08-26 15:30   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 25/37] target/ppc: Move rlwimi, rlwinm " Chinmay Rath
2026-08-26 15:41   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 26/37] target/ppc: Move lmw, stmw " Chinmay Rath
2026-08-26 15:44   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 27/37] target/ppc: Move mfmsr, mtmsr[d] " Chinmay Rath
2026-08-26 15:49   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 28/37] target/ppc: Move byte-reverse " Chinmay Rath
2026-08-26 15:54   ` Amit Machhiwal
2026-08-27 10:52     ` Chinmay Rath
2026-08-26  5:08 ` [PATCH v2 29/37] target/ppc: Move system call and rfi " Chinmay Rath
2026-08-26 16:54   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 30/37] target/ppc: Replace PPC2_VSX207 flag with PPC2_ISA207 Chinmay Rath
2026-08-26 16:56   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 31/37] target/ppc: Use PPC2_ISA207 instead of PPC2_BCTAR_ISA207 Chinmay Rath
2026-08-26 16:58   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 32/37] target/ppc: Use PPC2_ISA207 instead of PPC2_LSQ_ISA207 Chinmay Rath
2026-08-26 17:01   ` Amit Machhiwal
2026-08-26  5:08 ` [PATCH v2 33/37] target/ppc: Use PPC2_ISA207 instead of PPC2_ALTIVEC_207 Chinmay Rath
2026-08-26 17:23   ` Amit Machhiwal
2026-08-26  5:09 ` [PATCH v2 34/37] target/ppc: Use PPC2_ISA207 instead of PPC2_ISA207S Chinmay Rath
2026-08-26  5:09 ` [PATCH v2 35/37] target/ppc: Reorder PPC2 flags Chinmay Rath
2026-08-26  5:09 ` [PATCH v2 36/37] target/ppc: Add ICBT support for ISA version 2.07 Chinmay Rath
2026-08-26  5:09 ` [PATCH v2 37/37] target/ppc: Add self as maintainer for PowerPC TCG CPUs Chinmay Rath
2026-08-26  5:41   ` Amit Machhiwal
2026-08-26  6:25   ` Gautam Menghani
2026-08-26  9:37   ` Aditya Gupta
2026-08-27  9:50 ` [PATCH v2 00/37] target/ppc: PPC TCG Improvements (decodetree migrations + ISA 2.07 flag updates) Aniket Sahu

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