From: Chinmay Rath <rathc@linux.ibm.com>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
harshpb@linux.ibm.com, milesg@linux.ibm.com
Cc: npiggin@gmail.com, richard.henderson@linaro.org,
vishalc@linux.ibm.com, tshah@linux.ibm.com,
shivangu@linux.ibm.com, ojaswin@linux.ibm.com,
aboorvad@linux.ibm.com, amachhiw@linux.ibm.com,
shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com,
nikhilks@linux.ibm.com, Chinmay Rath <rathc@linux.ibm.com>
Subject: [PATCH v2 33/37] target/ppc: Use PPC2_ISA207 instead of PPC2_ALTIVEC_207
Date: Wed, 26 Aug 2026 10:38:59 +0530 [thread overview]
Message-ID: <20260826050923.74756-34-rathc@linux.ibm.com> (raw)
In-Reply-To: <20260826050923.74756-1-rathc@linux.ibm.com>
PPC2_ALTIVEC_207 is only ever set in the CPUPPCState's insns_flags2
alongside PPC2_ISA207. Checks made by PPC2_ALTIVEC_207 could be
replaced with PPC2_ISA207, hence rendering it useless and apt for
removal. This patch does the same.
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
---
linux-user/ppc/elfload.c | 3 +-
target/ppc/cpu.h | 4 +-
target/ppc/cpu_init.c | 2 +-
target/ppc/cpu_init.h | 3 +-
target/ppc/translate/vmx-impl.c.inc | 102 ++++++++++++++--------------
target/ppc/translate/vmx-ops.c.inc | 18 ++---
6 files changed, 64 insertions(+), 68 deletions(-)
diff --git a/linux-user/ppc/elfload.c b/linux-user/ppc/elfload.c
index 76ab9f43de..8c40f1a663 100644
--- a/linux-user/ppc/elfload.c
+++ b/linux-user/ppc/elfload.c
@@ -116,8 +116,7 @@ abi_ulong get_elf_hwcap2(CPUState *cs)
do { if (cpu->env.insns_flags2 & flag) { features |= feature; } } while (0)
GET_FEATURE(PPC_ISEL, QEMU_PPC_FEATURE2_HAS_ISEL);
- GET_FEATURE2((PPC2_ISA207 | PPC2_ALTIVEC_207 |
- PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_07 |
+ GET_FEATURE2((PPC2_ISA207 | PPC2_ISA207S), (QEMU_PPC_FEATURE2_ARCH_2_07 |
QEMU_PPC_FEATURE2_VEC_CRYPTO | QEMU_PPC_FEATURE2_HAS_TAR));
GET_FEATURE2(PPC2_ISA300, QEMU_PPC_FEATURE2_ARCH_3_00 |
QEMU_PPC_FEATURE2_DARN | QEMU_PPC_FEATURE2_HAS_IEEE128);
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index b3cd8d85df..00676cea2b 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2577,8 +2577,6 @@ enum {
PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
/* ISA 2.06B floating point test instructions */
PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
- /* ISA 2.07 Altivec */
- PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
/* PowerISA 2.07 Book3s specification */
PPC2_ISA207S = 0x0000000000008000ULL,
/* Double precision floating point conversion for signed integer 64 */
@@ -2606,7 +2604,7 @@ enum {
PPC2_ISA205 | PPC2_ISA207 | PPC2_PERM_ISA206 | \
PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
- PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
+ PPC2_ISA207S | PPC2_DFP | \
PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \
PPC2_BCDA_ISA206 | PPC2_PPE42 | PPC2_PPE42X | \
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 4cc8b93dca..c251426b2e 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6349,7 +6349,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *data)
pcc->insns_flags2 = PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX |
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
- PPC2_FP_TST_ISA206 | PPC2_ALTIVEC_207 |
+ PPC2_FP_TST_ISA206 |
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC |
PPC2_BCDA_ISA206;
diff --git a/target/ppc/cpu_init.h b/target/ppc/cpu_init.h
index 6961007926..73f014c82a 100644
--- a/target/ppc/cpu_init.h
+++ b/target/ppc/cpu_init.h
@@ -17,8 +17,7 @@
#define PPC_INSNS_FLAGS2_POWER_COMMON \
(PPC2_VSX | PPC2_ISA207 | PPC2_DFP | PPC2_DBRX | \
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
- PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
- PPC2_ALTIVEC_207 | PPC2_ISA205 | \
+ PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | PPC2_ISA205 | \
PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA300 | PPC2_PRCNTL | \
PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206)
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 4e7fe22156..486f5c2151 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -351,14 +351,14 @@ static bool do_vx_vaddsubm(DisasContext *ctx, arg_VX *a, MemOp vece,
TRANS_FLAGS(ALTIVEC, VADDUBM, do_vx_vaddsubm, MO_8, tcg_gen_gvec_add)
TRANS_FLAGS(ALTIVEC, VADDUHM, do_vx_vaddsubm, MO_16, tcg_gen_gvec_add)
TRANS_FLAGS(ALTIVEC, VADDUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_add)
-TRANS_FLAGS2(ALTIVEC_207, VADDUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_add)
+TRANS_FLAGS2(ISA207, VADDUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_add)
TRANS_FLAGS(ALTIVEC, VSUBUBM, do_vx_vaddsubm, MO_8, tcg_gen_gvec_sub)
TRANS_FLAGS(ALTIVEC, VSUBUHM, do_vx_vaddsubm, MO_16, tcg_gen_gvec_sub)
TRANS_FLAGS(ALTIVEC, VSUBUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_sub)
-TRANS_FLAGS2(ALTIVEC_207, VSUBUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_sub)
+TRANS_FLAGS2(ISA207, VSUBUDM, do_vx_vaddsubm, MO_64, tcg_gen_gvec_sub)
-TRANS_FLAGS2(ALTIVEC_207, VMULUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_mul)
+TRANS_FLAGS2(ISA207, VMULUWM, do_vx_vaddsubm, MO_32, tcg_gen_gvec_mul)
TRANS_FLAGS2(ISA300, VMUL10CUQ, do_vx_vmul10, false, true)
TRANS_FLAGS2(ISA300, VMUL10ECUQ, do_vx_vmul10, true, true)
@@ -699,22 +699,22 @@ static bool do_vector_gvec3_VX(DisasContext *ctx, arg_VX *a, int vece,
TRANS_FLAGS(ALTIVEC, VSLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shlv);
TRANS_FLAGS(ALTIVEC, VSLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shlv);
TRANS_FLAGS(ALTIVEC, VSLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shlv);
-TRANS_FLAGS2(ALTIVEC_207, VSLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shlv);
+TRANS_FLAGS2(ISA207, VSLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shlv);
TRANS_FLAGS(ALTIVEC, VSRB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shrv);
TRANS_FLAGS(ALTIVEC, VSRH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shrv);
TRANS_FLAGS(ALTIVEC, VSRW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shrv);
-TRANS_FLAGS2(ALTIVEC_207, VSRD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shrv);
+TRANS_FLAGS2(ISA207, VSRD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shrv);
TRANS_FLAGS(ALTIVEC, VSRAB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
-TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
+TRANS_FLAGS2(ISA207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VRLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_rotlv)
TRANS_FLAGS(ALTIVEC, VRLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_rotlv)
TRANS_FLAGS(ALTIVEC, VRLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_rotlv)
-TRANS_FLAGS2(ALTIVEC_207, VRLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_rotlv)
+TRANS_FLAGS2(ISA207, VRLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_rotlv)
/* Logical operations */
TRANS_FLAGS(ALTIVEC, VAND, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_and);
@@ -722,30 +722,30 @@ TRANS_FLAGS(ALTIVEC, VANDC, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_andc);
TRANS_FLAGS(ALTIVEC, VOR, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_or);
TRANS_FLAGS(ALTIVEC, VXOR, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_xor);
TRANS_FLAGS(ALTIVEC, VNOR, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_nor);
-TRANS_FLAGS2(ALTIVEC_207, VEQV, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_eqv);
-TRANS_FLAGS2(ALTIVEC_207, VNAND, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_nand);
-TRANS_FLAGS2(ALTIVEC_207, VORC, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_orc);
+TRANS_FLAGS2(ISA207, VEQV, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_eqv);
+TRANS_FLAGS2(ISA207, VNAND, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_nand);
+TRANS_FLAGS2(ISA207, VORC, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_orc);
/* Integer Max/Min operations */
TRANS_FLAGS(ALTIVEC, VMAXUB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_umax);
TRANS_FLAGS(ALTIVEC, VMAXUH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_umax);
TRANS_FLAGS(ALTIVEC, VMAXUW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_umax);
-TRANS_FLAGS2(ALTIVEC_207, VMAXUD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_umax);
+TRANS_FLAGS2(ISA207, VMAXUD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_umax);
TRANS_FLAGS(ALTIVEC, VMAXSB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_smax);
TRANS_FLAGS(ALTIVEC, VMAXSH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_smax);
TRANS_FLAGS(ALTIVEC, VMAXSW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_smax);
-TRANS_FLAGS2(ALTIVEC_207, VMAXSD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_smax);
+TRANS_FLAGS2(ISA207, VMAXSD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_smax);
TRANS_FLAGS(ALTIVEC, VMINUB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_umin);
TRANS_FLAGS(ALTIVEC, VMINUH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_umin);
TRANS_FLAGS(ALTIVEC, VMINUW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_umin);
-TRANS_FLAGS2(ALTIVEC_207, VMINUD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_umin);
+TRANS_FLAGS2(ISA207, VMINUD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_umin);
TRANS_FLAGS(ALTIVEC, VMINSB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_smin);
TRANS_FLAGS(ALTIVEC, VMINSH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_smin);
TRANS_FLAGS(ALTIVEC, VMINSW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_smin);
-TRANS_FLAGS2(ALTIVEC_207, VMINSD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_smin);
+TRANS_FLAGS2(ISA207, VMINSD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_smin);
static TCGv_vec do_vrl_mask_vec(unsigned vece, TCGv_vec vrb)
{
@@ -1091,16 +1091,16 @@ static bool do_vpk(DisasContext *ctx, arg_VX *a,
TRANS_FLAGS(ALTIVEC, VPKUHUM, do_vpk_env, gen_helper_VPKUHUM)
TRANS_FLAGS(ALTIVEC, VPKUWUM, do_vpk_env, gen_helper_VPKUWUM)
-TRANS_FLAGS2(ALTIVEC_207, VPKUDUM, do_vpk_env, gen_helper_VPKUDUM)
+TRANS_FLAGS2(ISA207, VPKUDUM, do_vpk_env, gen_helper_VPKUDUM)
TRANS_FLAGS(ALTIVEC, VPKUHUS, do_vpk_env, gen_helper_VPKUHUS)
TRANS_FLAGS(ALTIVEC, VPKUWUS, do_vpk_env, gen_helper_VPKUWUS)
-TRANS_FLAGS2(ALTIVEC_207, VPKUDUS, do_vpk_env, gen_helper_VPKUDUS)
+TRANS_FLAGS2(ISA207, VPKUDUS, do_vpk_env, gen_helper_VPKUDUS)
TRANS_FLAGS(ALTIVEC, VPKSHUS, do_vpk_env, gen_helper_VPKSHUS)
TRANS_FLAGS(ALTIVEC, VPKSWUS, do_vpk_env, gen_helper_VPKSWUS)
-TRANS_FLAGS2(ALTIVEC_207, VPKSDUS, do_vpk_env, gen_helper_VPKSDUS)
+TRANS_FLAGS2(ISA207, VPKSDUS, do_vpk_env, gen_helper_VPKSDUS)
TRANS_FLAGS(ALTIVEC, VPKSHSS, do_vpk_env, gen_helper_VPKSHSS)
TRANS_FLAGS(ALTIVEC, VPKSWSS, do_vpk_env, gen_helper_VPKSWSS)
-TRANS_FLAGS2(ALTIVEC_207, VPKSDSS, do_vpk_env, gen_helper_VPKSDSS)
+TRANS_FLAGS2(ISA207, VPKSDSS, do_vpk_env, gen_helper_VPKSDSS)
TRANS_FLAGS(ALTIVEC, VPKPX, do_vpk, gen_helper_VPKPX)
GEN_VXFORM_ENV(vsum4ubs, 4, 24);
GEN_VXFORM_ENV(vsum4sbs, 4, 28);
@@ -1114,12 +1114,12 @@ GEN_VXFORM_ENV(vminfp, 5, 17);
GEN_VXFORM_HETRO(vextublx, 6, 24)
GEN_VXFORM_HETRO(vextuhlx, 6, 25)
GEN_VXFORM_HETRO(vextuwlx, 6, 26)
-GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
+GEN_VXFORM_TRANS_DUAL(vmrgow, PPC_NONE, PPC2_ISA207,
vextuwlx, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_HETRO(vextubrx, 6, 28)
GEN_VXFORM_HETRO(vextuhrx, 6, 29)
GEN_VXFORM_HETRO(vextuwrx, 6, 30)
-GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207,
+GEN_VXFORM_TRANS_DUAL(vmrgew, PPC_NONE, PPC2_ISA207,
vextuwrx, PPC_NONE, PPC2_ISA300)
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
@@ -1209,16 +1209,16 @@ static bool do_vcmp(DisasContext *ctx, arg_VC *a, TCGCond cond, int vece)
TRANS_FLAGS(ALTIVEC, VCMPEQUB, do_vcmp, TCG_COND_EQ, MO_8)
TRANS_FLAGS(ALTIVEC, VCMPEQUH, do_vcmp, TCG_COND_EQ, MO_16)
TRANS_FLAGS(ALTIVEC, VCMPEQUW, do_vcmp, TCG_COND_EQ, MO_32)
-TRANS_FLAGS2(ALTIVEC_207, VCMPEQUD, do_vcmp, TCG_COND_EQ, MO_64)
+TRANS_FLAGS2(ISA207, VCMPEQUD, do_vcmp, TCG_COND_EQ, MO_64)
TRANS_FLAGS(ALTIVEC, VCMPGTSB, do_vcmp, TCG_COND_GT, MO_8)
TRANS_FLAGS(ALTIVEC, VCMPGTSH, do_vcmp, TCG_COND_GT, MO_16)
TRANS_FLAGS(ALTIVEC, VCMPGTSW, do_vcmp, TCG_COND_GT, MO_32)
-TRANS_FLAGS2(ALTIVEC_207, VCMPGTSD, do_vcmp, TCG_COND_GT, MO_64)
+TRANS_FLAGS2(ISA207, VCMPGTSD, do_vcmp, TCG_COND_GT, MO_64)
TRANS_FLAGS(ALTIVEC, VCMPGTUB, do_vcmp, TCG_COND_GTU, MO_8)
TRANS_FLAGS(ALTIVEC, VCMPGTUH, do_vcmp, TCG_COND_GTU, MO_16)
TRANS_FLAGS(ALTIVEC, VCMPGTUW, do_vcmp, TCG_COND_GTU, MO_32)
-TRANS_FLAGS2(ALTIVEC_207, VCMPGTUD, do_vcmp, TCG_COND_GTU, MO_64)
+TRANS_FLAGS2(ISA207, VCMPGTUD, do_vcmp, TCG_COND_GTU, MO_64)
TRANS_FLAGS2(ISA300, VCMPNEB, do_vcmp, TCG_COND_NE, MO_8)
TRANS_FLAGS2(ISA300, VCMPNEH, do_vcmp, TCG_COND_NE, MO_16)
@@ -2330,11 +2330,11 @@ static bool do_va_helper(DisasContext *ctx, arg_VA *a,
return true;
}
-TRANS_FLAGS2(ALTIVEC_207, VADDECUQ, do_va_helper, gen_helper_VADDECUQ)
-TRANS_FLAGS2(ALTIVEC_207, VADDEUQM, do_va_helper, gen_helper_VADDEUQM)
+TRANS_FLAGS2(ISA207, VADDECUQ, do_va_helper, gen_helper_VADDECUQ)
+TRANS_FLAGS2(ISA207, VADDEUQM, do_va_helper, gen_helper_VADDEUQM)
-TRANS_FLAGS2(ALTIVEC_207, VSUBEUQM, do_va_helper, gen_helper_VSUBEUQM)
-TRANS_FLAGS2(ALTIVEC_207, VSUBECUQ, do_va_helper, gen_helper_VSUBECUQ)
+TRANS_FLAGS2(ISA207, VSUBEUQM, do_va_helper, gen_helper_VSUBEUQM)
+TRANS_FLAGS2(ISA207, VSUBECUQ, do_va_helper, gen_helper_VSUBECUQ)
TRANS_FLAGS(ALTIVEC, VPERM, do_va_helper, gen_helper_VPERM)
TRANS_FLAGS2(ISA300, VPERMR, do_va_helper, gen_helper_VPERMR)
@@ -2502,14 +2502,14 @@ GEN_VXFORM_NOA(vpopcntb, 1, 28)
GEN_VXFORM_NOA(vpopcnth, 1, 29)
GEN_VXFORM_NOA(vpopcntw, 1, 30)
GEN_VXFORM_NOA(vpopcntd, 1, 31)
-GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
- vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
- vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
- vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
- vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ISA207, \
+ vpopcntb, PPC_NONE, PPC2_ISA207)
+GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ISA207, \
+ vpopcnth, PPC_NONE, PPC2_ISA207)
+GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ISA207, \
+ vpopcntw, PPC_NONE, PPC2_ISA207)
+GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ISA207, \
+ vpopcntd, PPC_NONE, PPC2_ISA207)
GEN_VXFORM(vbpermd, 6, 23);
GEN_VXFORM(vbpermq, 6, 21);
GEN_VXFORM_TRANS(vgbbd, 6, 20);
@@ -2589,8 +2589,8 @@ static bool do_bcd_tb_ps(DisasContext *ctx, arg_VX_tb_ps *a,
return true;
}
-TRANS_FLAGS2(ALTIVEC_207, BCDADD, do_bcd_ps, gen_helper_BCDADD)
-TRANS_FLAGS2(ALTIVEC_207, BCDSUB, do_bcd_ps, gen_helper_BCDSUB)
+TRANS_FLAGS2(ISA207, BCDADD, do_bcd_ps, gen_helper_BCDADD)
+TRANS_FLAGS2(ISA207, BCDSUB, do_bcd_ps, gen_helper_BCDSUB)
TRANS_FLAGS2(ISA300, BCDUS, do_bcd, gen_helper_BCDUS)
TRANS_FLAGS2(ISA300, BCDS, do_bcd_ps, gen_helper_BCDS)
TRANS_FLAGS2(ISA300, BCDCFN, do_bcd_tb_ps, gen_helper_BCDCFN)
@@ -2622,10 +2622,10 @@ GEN_VXFORM(vcipherlast, 4, 20)
GEN_VXFORM(vncipher, 4, 21)
GEN_VXFORM(vncipherlast, 4, 21)
-GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
- vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
- vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ISA207,
+ vcipherlast, PPC_NONE, PPC2_ISA207)
+GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ISA207,
+ vncipherlast, PPC_NONE, PPC2_ISA207)
#define VSHASIGMA(op) \
static void gen_##op(DisasContext *ctx) \
@@ -2647,7 +2647,7 @@ VSHASIGMA(vshasigmad)
GEN_VXFORM3(vpermxor, 22, 0xFF)
GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
- vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
+ vpermxor, PPC_NONE, PPC2_ISA207)
static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
{
@@ -2815,13 +2815,13 @@ static bool do_vx_helper(DisasContext *ctx, arg_VX *a,
return true;
}
-TRANS_FLAGS2(ALTIVEC_207, VADDCUQ, do_vx_helper, gen_helper_VADDCUQ)
-TRANS_FLAGS2(ALTIVEC_207, VADDUQM, do_vx_helper, gen_helper_VADDUQM)
+TRANS_FLAGS2(ISA207, VADDCUQ, do_vx_helper, gen_helper_VADDCUQ)
+TRANS_FLAGS2(ISA207, VADDUQM, do_vx_helper, gen_helper_VADDUQM)
-TRANS_FLAGS2(ALTIVEC_207, VPMSUMD, do_vx_helper, gen_helper_VPMSUMD)
+TRANS_FLAGS2(ISA207, VPMSUMD, do_vx_helper, gen_helper_VPMSUMD)
-TRANS_FLAGS2(ALTIVEC_207, VSUBCUQ, do_vx_helper, gen_helper_VSUBCUQ)
-TRANS_FLAGS2(ALTIVEC_207, VSUBUQM, do_vx_helper, gen_helper_VSUBUQM)
+TRANS_FLAGS2(ISA207, VSUBCUQ, do_vx_helper, gen_helper_VSUBCUQ)
+TRANS_FLAGS2(ISA207, VSUBUQM, do_vx_helper, gen_helper_VSUBUQM)
static void gen_VADDCUW_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
{
@@ -3092,10 +3092,10 @@ TRANS_FLAGS(ALTIVEC, VMULESH, do_vx_helper, gen_helper_VMULESH)
TRANS_FLAGS(ALTIVEC, VMULOSH, do_vx_helper, gen_helper_VMULOSH)
TRANS_FLAGS(ALTIVEC, VMULEUH, do_vx_helper, gen_helper_VMULEUH)
TRANS_FLAGS(ALTIVEC, VMULOUH, do_vx_helper, gen_helper_VMULOUH)
-TRANS_FLAGS2(ALTIVEC_207, VMULESW, do_vx_helper, gen_helper_VMULESW)
-TRANS_FLAGS2(ALTIVEC_207, VMULOSW, do_vx_helper, gen_helper_VMULOSW)
-TRANS_FLAGS2(ALTIVEC_207, VMULEUW, do_vx_helper, gen_helper_VMULEUW)
-TRANS_FLAGS2(ALTIVEC_207, VMULOUW, do_vx_helper, gen_helper_VMULOUW)
+TRANS_FLAGS2(ISA207, VMULESW, do_vx_helper, gen_helper_VMULESW)
+TRANS_FLAGS2(ISA207, VMULOSW, do_vx_helper, gen_helper_VMULOSW)
+TRANS_FLAGS2(ISA207, VMULEUW, do_vx_helper, gen_helper_VMULEUW)
+TRANS_FLAGS2(ISA207, VMULOUW, do_vx_helper, gen_helper_VMULOUW)
TRANS_FLAGS2(ISA310, VMULESD, do_vx_vmuleo, true , tcg_gen_muls2_i64)
TRANS_FLAGS2(ISA310, VMULOSD, do_vx_vmuleo, false, tcg_gen_muls2_i64)
TRANS_FLAGS2(ISA310, VMULEUD, do_vx_vmuleo, true , tcg_gen_mulu2_i64)
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index c1951c6975..2facbc7cb4 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -2,7 +2,7 @@
GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
#define GEN_VXFORM_207(name, opc2, opc3) \
-GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA207)
#define GEN_VXFORM_300(name, opc2, opc3) \
GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300)
@@ -26,10 +26,10 @@ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
GEN_VXFORM_300(vextublx, 6, 24),
GEN_VXFORM_300(vextuhlx, 6, 25),
-GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ISA207),
GEN_VXFORM_300(vextubrx, 6, 28),
GEN_VXFORM_300(vextuhrx, 6, 29),
-GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ISA207),
GEN_VXFORM_300(vsrv, 2, 28),
GEN_VXFORM_300(vslv, 2, 29),
GEN_VXFORM(vslo, 6, 16),
@@ -113,10 +113,10 @@ GEN_VXFORM_UIMM(vctsxs, 5, 15),
GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
-GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ISA207),
+GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ISA207),
+GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ISA207),
+GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ISA207),
GEN_VXFORM_300(vbpermd, 6, 23),
GEN_VXFORM_207(vbpermq, 6, 21),
@@ -127,8 +127,8 @@ GEN_VXFORM_207(vpmsumw, 4, 18),
GEN_VXFORM_207(vsbox, 4, 23),
-GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ISA207),
+GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ISA207),
GEN_VXFORM_207(vshasigmaw, 1, 26),
GEN_VXFORM_207(vshasigmad, 1, 27),
--
2.55.0
next prev parent reply other threads:[~2026-08-26 5:14 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-26 5:08 [PATCH v2 00/37] target/ppc: PPC TCG Improvements (decodetree migrations + ISA 2.07 flag updates) Chinmay Rath
2026-08-26 5:08 ` [PATCH v2 01/37] target/ppc: Migrate extswsli to decodetree Chinmay Rath
2026-08-26 7:33 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 02/37] target/ppc: Migrate atomic loads " Chinmay Rath
2026-08-26 9:20 ` Amit Machhiwal
2026-08-26 12:28 ` Chinmay Rath
2026-08-26 12:30 ` Chinmay Rath
2026-08-26 5:08 ` [PATCH v2 03/37] target/ppc: Convert cache instructions " Chinmay Rath
2026-08-26 10:20 ` Amit Machhiwal
2026-08-26 13:09 ` Chinmay Rath
2026-08-26 13:17 ` Amit Machhiwal
2026-08-27 9:13 ` Chinmay Rath
2026-08-27 8:37 ` Chinmay Rath
2026-08-26 5:08 ` [PATCH v2 04/37] target/ppc: Move vector merge " Chinmay Rath
2026-08-26 10:57 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 05/37] target/ppc: Move vector pack " Chinmay Rath
2026-08-26 11:04 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 06/37] target/ppc: Move st{b, h, w, d, q}cx " Chinmay Rath
2026-08-26 11:18 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 07/37] target/ppc: convert slw, srw instruction via decode spec Chinmay Rath
2026-08-26 11:28 ` Amit Machhiwal
2026-08-26 11:30 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 08/37] target/ppc: convert sraw[i] " Chinmay Rath
2026-08-26 11:41 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 09/37] target/ppc: Convert mcrf to decode tree Chinmay Rath
2026-08-26 11:52 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 10/37] target/ppc: Move fixed-point Shift insns to decodetree Chinmay Rath
2026-08-26 5:08 ` [PATCH v2 11/37] target/ppc: Move fixed-point byte-reversal store " Chinmay Rath
2026-08-26 5:08 ` [PATCH v2 12/37] target/ppc: Move GPR atomic load/store instructions " Chinmay Rath
2026-08-26 12:05 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 13/37] target/ppc: Move isync instruction " Chinmay Rath
2026-08-26 12:20 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 14/37] target/ppc: Convert b{a, l, la} to decode tree Chinmay Rath
2026-08-26 12:24 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 15/37] target/ppc: move various conditional branch insns to decodetree Chinmay Rath
2026-08-26 12:38 ` Amit Machhiwal
2026-08-26 12:45 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 16/37] target/ppc: Fix TRANS* macro variadic arguments handling Chinmay Rath
2026-08-26 12:50 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 17/37] target/ppc: Move wait instruction to decodetree Chinmay Rath
2026-08-26 13:12 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 18/37] target/ppc: Move sleep & friends " Chinmay Rath
2026-08-26 13:26 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 19/37] target/ppc: Refactor sleep and its variants to use a common helper Chinmay Rath
2026-08-26 13:38 ` Amit Machhiwal
2026-08-26 14:30 ` Miles Glenn
2026-08-26 5:08 ` [PATCH v2 20/37] target/ppc: Move Condition Register access instructions to decodetree Chinmay Rath
2026-08-26 14:24 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 21/37] target/ppc: Move Condition Register logical " Chinmay Rath
2026-08-26 14:43 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 22/37] target/ppc: make do_ea_calc_ra available for 32 bit builds Chinmay Rath
2026-08-26 14:48 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 23/37] target/ppc: Move Fixed-Point Load/Store String instructions to decodetree Chinmay Rath
2026-08-26 15:19 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 24/37] target/ppc: Move VMX integer arithmetic and BCD " Chinmay Rath
2026-08-26 15:30 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 25/37] target/ppc: Move rlwimi, rlwinm " Chinmay Rath
2026-08-26 15:41 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 26/37] target/ppc: Move lmw, stmw " Chinmay Rath
2026-08-26 15:44 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 27/37] target/ppc: Move mfmsr, mtmsr[d] " Chinmay Rath
2026-08-26 15:49 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 28/37] target/ppc: Move byte-reverse " Chinmay Rath
2026-08-26 15:54 ` Amit Machhiwal
2026-08-27 10:52 ` Chinmay Rath
2026-08-26 5:08 ` [PATCH v2 29/37] target/ppc: Move system call and rfi " Chinmay Rath
2026-08-26 16:54 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 30/37] target/ppc: Replace PPC2_VSX207 flag with PPC2_ISA207 Chinmay Rath
2026-08-26 16:56 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 31/37] target/ppc: Use PPC2_ISA207 instead of PPC2_BCTAR_ISA207 Chinmay Rath
2026-08-26 16:58 ` Amit Machhiwal
2026-08-26 5:08 ` [PATCH v2 32/37] target/ppc: Use PPC2_ISA207 instead of PPC2_LSQ_ISA207 Chinmay Rath
2026-08-26 17:01 ` Amit Machhiwal
2026-08-26 5:08 ` Chinmay Rath [this message]
2026-08-26 17:23 ` [PATCH v2 33/37] target/ppc: Use PPC2_ISA207 instead of PPC2_ALTIVEC_207 Amit Machhiwal
2026-08-26 5:09 ` [PATCH v2 34/37] target/ppc: Use PPC2_ISA207 instead of PPC2_ISA207S Chinmay Rath
2026-08-26 5:09 ` [PATCH v2 35/37] target/ppc: Reorder PPC2 flags Chinmay Rath
2026-08-26 5:09 ` [PATCH v2 36/37] target/ppc: Add ICBT support for ISA version 2.07 Chinmay Rath
2026-08-26 5:09 ` [PATCH v2 37/37] target/ppc: Add self as maintainer for PowerPC TCG CPUs Chinmay Rath
2026-08-26 5:41 ` Amit Machhiwal
2026-08-26 6:25 ` Gautam Menghani
2026-08-26 9:37 ` Aditya Gupta
2026-08-27 9:50 ` [PATCH v2 00/37] target/ppc: PPC TCG Improvements (decodetree migrations + ISA 2.07 flag updates) Aniket Sahu
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